include/soc/mscc/ocelot_sys.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
   2 /*
   3  * Microsemi Ocelot Switch driver
   4  *
   5  * Copyright (c) 2017 Microsemi Corporation
   6  */
   7
   8 #ifndef _MSCC_OCELOT_SYS_H_
   9 #define _MSCC_OCELOT_SYS_H_
  10
  11 #define SYS_COUNT_RX_OCTETS_RSZ                           0x4
  12
  13 #define SYS_COUNT_TX_OCTETS_RSZ                           0x4
  14
  15 #define SYS_FRONT_PORT_MODE_RSZ                           0x4
  16
  17 #define SYS_FRONT_PORT_MODE_HDX_MODE                      BIT(0)
  18
  19 #define SYS_FRM_AGING_AGE_TX_ENA                          BIT(20)
  20 #define SYS_FRM_AGING_MAX_AGE(x)                          ((x) & GENMASK(19, 0))
  21 #define SYS_FRM_AGING_MAX_AGE_M                           GENMASK(19, 0)
  22
  23 #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x)                   (((x) << 10) & GENMASK(16, 10))
  24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M                    GENMASK(16, 10)
  25 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x)                 (((x) & GENMASK(16, 10)) >> 10)
  26 #define SYS_STAT_CFG_STAT_VIEW(x)                         ((x) & GENMASK(9, 0))
  27 #define SYS_STAT_CFG_STAT_VIEW_M                          GENMASK(9, 0)
  28
  29 #define SYS_SW_STATUS_RSZ                                 0x4
  30
  31 #define SYS_SW_STATUS_PORT_RX_PAUSED                      BIT(0)
  32
  33 #define SYS_MISC_CFG_PTP_RSRV_CLR                         BIT(1)
  34 #define SYS_MISC_CFG_PTP_DIS_NEG_RO                       BIT(0)
  35
  36 #define SYS_REW_MAC_HIGH_CFG_RSZ                          0x4
  37
  38 #define SYS_REW_MAC_LOW_CFG_RSZ                           0x4
  39
  40 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x)              (((x) << 6) & GENMASK(21, 6))
  41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M               GENMASK(21, 6)
  42 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x)            (((x) & GENMASK(21, 6)) >> 6)
  43 #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x)          ((x) & GENMASK(5, 0))
  44 #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M           GENMASK(5, 0)
  45
  46 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x)              (((x) << 9) & GENMASK(17, 9))
  47 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M               GENMASK(17, 9)
  48 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x)            (((x) & GENMASK(17, 9)) >> 9)
  49 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x)               ((x) & GENMASK(8, 0))
  50 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M                GENMASK(8, 0)
  51
  52 #define SYS_ATOP_RSZ                                      0x4
  53
  54 #define SYS_MAC_FC_CFG_RSZ                                0x4
  55
  56 #define SYS_MAC_FC_CFG_FC_LINK_SPEED(x)                   (((x) << 26) & GENMASK(27, 26))
  57 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_M                    GENMASK(27, 26)
  58 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x)                 (((x) & GENMASK(27, 26)) >> 26)
  59 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x)                  (((x) << 20) & GENMASK(25, 20))
  60 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M                   GENMASK(25, 20)
  61 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x)                (((x) & GENMASK(25, 20)) >> 20)
  62 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA                     BIT(18)
  63 #define SYS_MAC_FC_CFG_TX_FC_ENA                          BIT(17)
  64 #define SYS_MAC_FC_CFG_RX_FC_ENA                          BIT(16)
  65 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x)                   ((x) & GENMASK(15, 0))
  66 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M                    GENMASK(15, 0)
  67
  68 #define SYS_MMGT_RELCNT(x)                                (((x) << 16) & GENMASK(31, 16))
  69 #define SYS_MMGT_RELCNT_M                                 GENMASK(31, 16)
  70 #define SYS_MMGT_RELCNT_X(x)                              (((x) & GENMASK(31, 16)) >> 16)
  71 #define SYS_MMGT_FREECNT(x)                               ((x) & GENMASK(15, 0))
  72 #define SYS_MMGT_FREECNT_M                                GENMASK(15, 0)
  73
  74 #define SYS_MMGT_FAST_FREEVLD(x)                          (((x) << 4) & GENMASK(7, 4))
  75 #define SYS_MMGT_FAST_FREEVLD_M                           GENMASK(7, 4)
  76 #define SYS_MMGT_FAST_FREEVLD_X(x)                        (((x) & GENMASK(7, 4)) >> 4)
  77 #define SYS_MMGT_FAST_RELVLD(x)                           ((x) & GENMASK(3, 0))
  78 #define SYS_MMGT_FAST_RELVLD_M                            GENMASK(3, 0)
  79
  80 #define SYS_EVENTS_DIF_RSZ                                0x4
  81
  82 #define SYS_EVENTS_DIF_EV_DRX(x)                          (((x) << 6) & GENMASK(8, 6))
  83 #define SYS_EVENTS_DIF_EV_DRX_M                           GENMASK(8, 6)
  84 #define SYS_EVENTS_DIF_EV_DRX_X(x)                        (((x) & GENMASK(8, 6)) >> 6)
  85 #define SYS_EVENTS_DIF_EV_DTX(x)                          ((x) & GENMASK(5, 0))
  86 #define SYS_EVENTS_DIF_EV_DTX_M                           GENMASK(5, 0)
  87
  88 #define SYS_EVENTS_CORE_EV_FWR                            BIT(2)
  89 #define SYS_EVENTS_CORE_EV_ANA(x)                         ((x) & GENMASK(1, 0))
  90 #define SYS_EVENTS_CORE_EV_ANA_M                          GENMASK(1, 0)
  91
  92 #define SYS_CNT_GSZ                                       0x4
  93
  94 #define SYS_PTP_STATUS_PTP_TXSTAMP_OAM                    BIT(29)
  95 #define SYS_PTP_STATUS_PTP_OVFL                           BIT(28)
  96 #define SYS_PTP_STATUS_PTP_MESS_VLD                       BIT(27)
  97 #define SYS_PTP_STATUS_PTP_MESS_ID(x)                     (((x) << 21) & GENMASK(26, 21))
  98 #define SYS_PTP_STATUS_PTP_MESS_ID_M                      GENMASK(26, 21)
  99 #define SYS_PTP_STATUS_PTP_MESS_ID_X(x)                   (((x) & GENMASK(26, 21)) >> 21)
 100 #define SYS_PTP_STATUS_PTP_MESS_TXPORT(x)                 (((x) << 16) & GENMASK(20, 16))
 101 #define SYS_PTP_STATUS_PTP_MESS_TXPORT_M                  GENMASK(20, 16)
 102 #define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x)               (((x) & GENMASK(20, 16)) >> 16)
 103 #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x)                 ((x) & GENMASK(15, 0))
 104 #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M                  GENMASK(15, 0)
 105
 106 #define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x)                    ((x) & GENMASK(29, 0))
 107 #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M                     GENMASK(29, 0)
 108 #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC                   BIT(31)
 109
 110 #define SYS_PTP_NXT_PTP_NXT                               BIT(0)
 111
 112 #define SYS_PTP_CFG_PTP_STAMP_WID(x)                      (((x) << 2) & GENMASK(7, 2))
 113 #define SYS_PTP_CFG_PTP_STAMP_WID_M                       GENMASK(7, 2)
 114 #define SYS_PTP_CFG_PTP_STAMP_WID_X(x)                    (((x) & GENMASK(7, 2)) >> 2)
 115 #define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x)                   ((x) & GENMASK(1, 0))
 116 #define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M                    GENMASK(1, 0)
 117
 118 #define SYS_RAM_INIT_RAM_INIT                             BIT(1)
 119 #define SYS_RAM_INIT_RAM_CFG_HOOK                         BIT(0)
 120
 121 #endif