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WIP FPC-III support
[linux/fpc-iii.git] / sound / pci / pcxhr / pcxhr_mix22.c
blobf340458fd2e111dffc77e3cde0193d81dbc055f8
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Digigram pcxhr compatible soundcards
4 *
5 * mixer interface for stereo cards
6 *
7 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/pci.h>
13 #include <sound/core.h>
14 #include <sound/control.h>
15 #include <sound/tlv.h>
16 #include <sound/asoundef.h>
17 #include "pcxhr.h"
18 #include "pcxhr_core.h"
19 #include "pcxhr_mix22.h"
20
21
22 /* registers used on the DSP and Xilinx (port 2) : HR stereo cards only */
23 #define PCXHR_DSP_RESET 0x20
24 #define PCXHR_XLX_CFG 0x24
25 #define PCXHR_XLX_RUER 0x28
26 #define PCXHR_XLX_DATA 0x2C
27 #define PCXHR_XLX_STATUS 0x30
28 #define PCXHR_XLX_LOFREQ 0x34
29 #define PCXHR_XLX_HIFREQ 0x38
30 #define PCXHR_XLX_CSUER 0x3C
31 #define PCXHR_XLX_SELMIC 0x40
32
33 #define PCXHR_DSP 2
34
35 /* byte access only ! */
36 #define PCXHR_INPB(mgr, x) inb((mgr)->port[PCXHR_DSP] + (x))
37 #define PCXHR_OUTPB(mgr, x, data) outb((data), (mgr)->port[PCXHR_DSP] + (x))
38
39
40 /* values for PCHR_DSP_RESET register */
41 #define PCXHR_DSP_RESET_DSP 0x01
42 #define PCXHR_DSP_RESET_MUTE 0x02
43 #define PCXHR_DSP_RESET_CODEC 0x08
44 #define PCXHR_DSP_RESET_SMPTE 0x10
45 #define PCXHR_DSP_RESET_GPO_OFFSET 5
46 #define PCXHR_DSP_RESET_GPO_MASK 0x60
47
48 /* values for PCHR_XLX_CFG register */
49 #define PCXHR_CFG_SYNCDSP_MASK 0x80
50 #define PCXHR_CFG_DEPENDENCY_MASK 0x60
51 #define PCXHR_CFG_INDEPENDANT_SEL 0x00
52 #define PCXHR_CFG_MASTER_SEL 0x40
53 #define PCXHR_CFG_SLAVE_SEL 0x20
54 #define PCXHR_CFG_DATA_UER1_SEL_MASK 0x10 /* 0 (UER0), 1(UER1) */
55 #define PCXHR_CFG_DATAIN_SEL_MASK 0x08 /* 0 (ana), 1 (UER) */
56 #define PCXHR_CFG_SRC_MASK 0x04 /* 0 (Bypass), 1 (SRC Actif) */
57 #define PCXHR_CFG_CLOCK_UER1_SEL_MASK 0x02 /* 0 (UER0), 1(UER1) */
58 #define PCXHR_CFG_CLOCKIN_SEL_MASK 0x01 /* 0 (internal), 1 (AES/EBU) */
59
60 /* values for PCHR_XLX_DATA register */
61 #define PCXHR_DATA_CODEC 0x80
62 #define AKM_POWER_CONTROL_CMD 0xA007
63 #define AKM_RESET_ON_CMD 0xA100
64 #define AKM_RESET_OFF_CMD 0xA103
65 #define AKM_CLOCK_INF_55K_CMD 0xA240
66 #define AKM_CLOCK_SUP_55K_CMD 0xA24D
67 #define AKM_MUTE_CMD 0xA38D
68 #define AKM_UNMUTE_CMD 0xA30D
69 #define AKM_LEFT_LEVEL_CMD 0xA600
70 #define AKM_RIGHT_LEVEL_CMD 0xA700
71
72 /* values for PCHR_XLX_STATUS register - READ */
73 #define PCXHR_STAT_SRC_LOCK 0x01
74 #define PCXHR_STAT_LEVEL_IN 0x02
75 #define PCXHR_STAT_GPI_OFFSET 2
76 #define PCXHR_STAT_GPI_MASK 0x0C
77 #define PCXHR_STAT_MIC_CAPS 0x10
78 /* values for PCHR_XLX_STATUS register - WRITE */
79 #define PCXHR_STAT_FREQ_SYNC_MASK 0x01
80 #define PCXHR_STAT_FREQ_UER1_MASK 0x02
81 #define PCXHR_STAT_FREQ_SAVE_MASK 0x80
82
83 /* values for PCHR_XLX_CSUER register */
84 #define PCXHR_SUER1_BIT_U_READ_MASK 0x80
85 #define PCXHR_SUER1_BIT_C_READ_MASK 0x40
86 #define PCXHR_SUER1_DATA_PRESENT_MASK 0x20
87 #define PCXHR_SUER1_CLOCK_PRESENT_MASK 0x10
88 #define PCXHR_SUER_BIT_U_READ_MASK 0x08
89 #define PCXHR_SUER_BIT_C_READ_MASK 0x04
90 #define PCXHR_SUER_DATA_PRESENT_MASK 0x02
91 #define PCXHR_SUER_CLOCK_PRESENT_MASK 0x01
92
93 #define PCXHR_SUER_BIT_U_WRITE_MASK 0x02
94 #define PCXHR_SUER_BIT_C_WRITE_MASK 0x01
95
96 /* values for PCXHR_XLX_SELMIC register - WRITE */
97 #define PCXHR_SELMIC_PREAMPLI_OFFSET 2
98 #define PCXHR_SELMIC_PREAMPLI_MASK 0x0C
99 #define PCXHR_SELMIC_PHANTOM_ALIM 0x80
100
101
102 static const unsigned char g_hr222_p_level[] = {
103 0x00, /* [000] -49.5 dB: AKM[000] = -1.#INF dB (mute) */
104 0x01, /* [001] -49.0 dB: AKM[001] = -48.131 dB (diff=0.86920 dB) */
105 0x01, /* [002] -48.5 dB: AKM[001] = -48.131 dB (diff=0.36920 dB) */
106 0x01, /* [003] -48.0 dB: AKM[001] = -48.131 dB (diff=0.13080 dB) */
107 0x01, /* [004] -47.5 dB: AKM[001] = -48.131 dB (diff=0.63080 dB) */
108 0x01, /* [005] -46.5 dB: AKM[001] = -48.131 dB (diff=1.63080 dB) */
109 0x01, /* [006] -47.0 dB: AKM[001] = -48.131 dB (diff=1.13080 dB) */
110 0x01, /* [007] -46.0 dB: AKM[001] = -48.131 dB (diff=2.13080 dB) */
111 0x01, /* [008] -45.5 dB: AKM[001] = -48.131 dB (diff=2.63080 dB) */
112 0x02, /* [009] -45.0 dB: AKM[002] = -42.110 dB (diff=2.88980 dB) */
113 0x02, /* [010] -44.5 dB: AKM[002] = -42.110 dB (diff=2.38980 dB) */
114 0x02, /* [011] -44.0 dB: AKM[002] = -42.110 dB (diff=1.88980 dB) */
115 0x02, /* [012] -43.5 dB: AKM[002] = -42.110 dB (diff=1.38980 dB) */
116 0x02, /* [013] -43.0 dB: AKM[002] = -42.110 dB (diff=0.88980 dB) */
117 0x02, /* [014] -42.5 dB: AKM[002] = -42.110 dB (diff=0.38980 dB) */
118 0x02, /* [015] -42.0 dB: AKM[002] = -42.110 dB (diff=0.11020 dB) */
119 0x02, /* [016] -41.5 dB: AKM[002] = -42.110 dB (diff=0.61020 dB) */
120 0x02, /* [017] -41.0 dB: AKM[002] = -42.110 dB (diff=1.11020 dB) */
121 0x02, /* [018] -40.5 dB: AKM[002] = -42.110 dB (diff=1.61020 dB) */
122 0x03, /* [019] -40.0 dB: AKM[003] = -38.588 dB (diff=1.41162 dB) */
123 0x03, /* [020] -39.5 dB: AKM[003] = -38.588 dB (diff=0.91162 dB) */
124 0x03, /* [021] -39.0 dB: AKM[003] = -38.588 dB (diff=0.41162 dB) */
125 0x03, /* [022] -38.5 dB: AKM[003] = -38.588 dB (diff=0.08838 dB) */
126 0x03, /* [023] -38.0 dB: AKM[003] = -38.588 dB (diff=0.58838 dB) */
127 0x03, /* [024] -37.5 dB: AKM[003] = -38.588 dB (diff=1.08838 dB) */
128 0x04, /* [025] -37.0 dB: AKM[004] = -36.090 dB (diff=0.91040 dB) */
129 0x04, /* [026] -36.5 dB: AKM[004] = -36.090 dB (diff=0.41040 dB) */
130 0x04, /* [027] -36.0 dB: AKM[004] = -36.090 dB (diff=0.08960 dB) */
131 0x04, /* [028] -35.5 dB: AKM[004] = -36.090 dB (diff=0.58960 dB) */
132 0x05, /* [029] -35.0 dB: AKM[005] = -34.151 dB (diff=0.84860 dB) */
133 0x05, /* [030] -34.5 dB: AKM[005] = -34.151 dB (diff=0.34860 dB) */
134 0x05, /* [031] -34.0 dB: AKM[005] = -34.151 dB (diff=0.15140 dB) */
135 0x05, /* [032] -33.5 dB: AKM[005] = -34.151 dB (diff=0.65140 dB) */
136 0x06, /* [033] -33.0 dB: AKM[006] = -32.568 dB (diff=0.43222 dB) */
137 0x06, /* [034] -32.5 dB: AKM[006] = -32.568 dB (diff=0.06778 dB) */
138 0x06, /* [035] -32.0 dB: AKM[006] = -32.568 dB (diff=0.56778 dB) */
139 0x07, /* [036] -31.5 dB: AKM[007] = -31.229 dB (diff=0.27116 dB) */
140 0x07, /* [037] -31.0 dB: AKM[007] = -31.229 dB (diff=0.22884 dB) */
141 0x08, /* [038] -30.5 dB: AKM[008] = -30.069 dB (diff=0.43100 dB) */
142 0x08, /* [039] -30.0 dB: AKM[008] = -30.069 dB (diff=0.06900 dB) */
143 0x09, /* [040] -29.5 dB: AKM[009] = -29.046 dB (diff=0.45405 dB) */
144 0x09, /* [041] -29.0 dB: AKM[009] = -29.046 dB (diff=0.04595 dB) */
145 0x0a, /* [042] -28.5 dB: AKM[010] = -28.131 dB (diff=0.36920 dB) */
146 0x0a, /* [043] -28.0 dB: AKM[010] = -28.131 dB (diff=0.13080 dB) */
147 0x0b, /* [044] -27.5 dB: AKM[011] = -27.303 dB (diff=0.19705 dB) */
148 0x0b, /* [045] -27.0 dB: AKM[011] = -27.303 dB (diff=0.30295 dB) */
149 0x0c, /* [046] -26.5 dB: AKM[012] = -26.547 dB (diff=0.04718 dB) */
150 0x0d, /* [047] -26.0 dB: AKM[013] = -25.852 dB (diff=0.14806 dB) */
151 0x0e, /* [048] -25.5 dB: AKM[014] = -25.208 dB (diff=0.29176 dB) */
152 0x0e, /* [049] -25.0 dB: AKM[014] = -25.208 dB (diff=0.20824 dB) */
153 0x0f, /* [050] -24.5 dB: AKM[015] = -24.609 dB (diff=0.10898 dB) */
154 0x10, /* [051] -24.0 dB: AKM[016] = -24.048 dB (diff=0.04840 dB) */
155 0x11, /* [052] -23.5 dB: AKM[017] = -23.522 dB (diff=0.02183 dB) */
156 0x12, /* [053] -23.0 dB: AKM[018] = -23.025 dB (diff=0.02535 dB) */
157 0x13, /* [054] -22.5 dB: AKM[019] = -22.556 dB (diff=0.05573 dB) */
158 0x14, /* [055] -22.0 dB: AKM[020] = -22.110 dB (diff=0.11020 dB) */
159 0x15, /* [056] -21.5 dB: AKM[021] = -21.686 dB (diff=0.18642 dB) */
160 0x17, /* [057] -21.0 dB: AKM[023] = -20.896 dB (diff=0.10375 dB) */
161 0x18, /* [058] -20.5 dB: AKM[024] = -20.527 dB (diff=0.02658 dB) */
162 0x1a, /* [059] -20.0 dB: AKM[026] = -19.831 dB (diff=0.16866 dB) */
163 0x1b, /* [060] -19.5 dB: AKM[027] = -19.504 dB (diff=0.00353 dB) */
164 0x1d, /* [061] -19.0 dB: AKM[029] = -18.883 dB (diff=0.11716 dB) */
165 0x1e, /* [062] -18.5 dB: AKM[030] = -18.588 dB (diff=0.08838 dB) */
166 0x20, /* [063] -18.0 dB: AKM[032] = -18.028 dB (diff=0.02780 dB) */
167 0x22, /* [064] -17.5 dB: AKM[034] = -17.501 dB (diff=0.00123 dB) */
168 0x24, /* [065] -17.0 dB: AKM[036] = -17.005 dB (diff=0.00475 dB) */
169 0x26, /* [066] -16.5 dB: AKM[038] = -16.535 dB (diff=0.03513 dB) */
170 0x28, /* [067] -16.0 dB: AKM[040] = -16.090 dB (diff=0.08960 dB) */
171 0x2b, /* [068] -15.5 dB: AKM[043] = -15.461 dB (diff=0.03857 dB) */
172 0x2d, /* [069] -15.0 dB: AKM[045] = -15.067 dB (diff=0.06655 dB) */
173 0x30, /* [070] -14.5 dB: AKM[048] = -14.506 dB (diff=0.00598 dB) */
174 0x33, /* [071] -14.0 dB: AKM[051] = -13.979 dB (diff=0.02060 dB) */
175 0x36, /* [072] -13.5 dB: AKM[054] = -13.483 dB (diff=0.01707 dB) */
176 0x39, /* [073] -13.0 dB: AKM[057] = -13.013 dB (diff=0.01331 dB) */
177 0x3c, /* [074] -12.5 dB: AKM[060] = -12.568 dB (diff=0.06778 dB) */
178 0x40, /* [075] -12.0 dB: AKM[064] = -12.007 dB (diff=0.00720 dB) */
179 0x44, /* [076] -11.5 dB: AKM[068] = -11.481 dB (diff=0.01937 dB) */
180 0x48, /* [077] -11.0 dB: AKM[072] = -10.984 dB (diff=0.01585 dB) */
181 0x4c, /* [078] -10.5 dB: AKM[076] = -10.515 dB (diff=0.01453 dB) */
182 0x51, /* [079] -10.0 dB: AKM[081] = -9.961 dB (diff=0.03890 dB) */
183 0x55, /* [080] -9.5 dB: AKM[085] = -9.542 dB (diff=0.04243 dB) */
184 0x5a, /* [081] -9.0 dB: AKM[090] = -9.046 dB (diff=0.04595 dB) */
185 0x60, /* [082] -8.5 dB: AKM[096] = -8.485 dB (diff=0.01462 dB) */
186 0x66, /* [083] -8.0 dB: AKM[102] = -7.959 dB (diff=0.04120 dB) */
187 0x6c, /* [084] -7.5 dB: AKM[108] = -7.462 dB (diff=0.03767 dB) */
188 0x72, /* [085] -7.0 dB: AKM[114] = -6.993 dB (diff=0.00729 dB) */
189 0x79, /* [086] -6.5 dB: AKM[121] = -6.475 dB (diff=0.02490 dB) */
190 0x80, /* [087] -6.0 dB: AKM[128] = -5.987 dB (diff=0.01340 dB) */
191 0x87, /* [088] -5.5 dB: AKM[135] = -5.524 dB (diff=0.02413 dB) */
192 0x8f, /* [089] -5.0 dB: AKM[143] = -5.024 dB (diff=0.02408 dB) */
193 0x98, /* [090] -4.5 dB: AKM[152] = -4.494 dB (diff=0.00607 dB) */
194 0xa1, /* [091] -4.0 dB: AKM[161] = -3.994 dB (diff=0.00571 dB) */
195 0xaa, /* [092] -3.5 dB: AKM[170] = -3.522 dB (diff=0.02183 dB) */
196 0xb5, /* [093] -3.0 dB: AKM[181] = -2.977 dB (diff=0.02277 dB) */
197 0xbf, /* [094] -2.5 dB: AKM[191] = -2.510 dB (diff=0.01014 dB) */
198 0xcb, /* [095] -2.0 dB: AKM[203] = -1.981 dB (diff=0.01912 dB) */
199 0xd7, /* [096] -1.5 dB: AKM[215] = -1.482 dB (diff=0.01797 dB) */
200 0xe3, /* [097] -1.0 dB: AKM[227] = -1.010 dB (diff=0.01029 dB) */
201 0xf1, /* [098] -0.5 dB: AKM[241] = -0.490 dB (diff=0.00954 dB) */
202 0xff, /* [099] +0.0 dB: AKM[255] = +0.000 dB (diff=0.00000 dB) */
203 };
204
205
206 static void hr222_config_akm(struct pcxhr_mgr *mgr, unsigned short data)
207 {
208 unsigned short mask = 0x8000;
209 /* activate access to codec registers */
210 PCXHR_INPB(mgr, PCXHR_XLX_HIFREQ);
211
212 while (mask) {
213 PCXHR_OUTPB(mgr, PCXHR_XLX_DATA,
214 data & mask ? PCXHR_DATA_CODEC : 0);
215 mask >>= 1;
216 }
217 /* termiate access to codec registers */
218 PCXHR_INPB(mgr, PCXHR_XLX_RUER);
219 }
220
221
222 static int hr222_set_hw_playback_level(struct pcxhr_mgr *mgr,
223 int idx, int level)
224 {
225 unsigned short cmd;
226 if (idx > 1 ||
227 level < 0 ||
228 level >= ARRAY_SIZE(g_hr222_p_level))
229 return -EINVAL;
230
231 if (idx == 0)
232 cmd = AKM_LEFT_LEVEL_CMD;
233 else
234 cmd = AKM_RIGHT_LEVEL_CMD;
235
236 /* conversion from PmBoardCodedLevel to AKM nonlinear programming */
237 cmd += g_hr222_p_level[level];
238
239 hr222_config_akm(mgr, cmd);
240 return 0;
241 }
242
243
244 static int hr222_set_hw_capture_level(struct pcxhr_mgr *mgr,
245 int level_l, int level_r, int level_mic)
246 {
247 /* program all input levels at the same time */
248 unsigned int data;
249 int i;
250
251 if (!mgr->capture_chips)
252 return -EINVAL; /* no PCX22 */
253
254 data = ((level_mic & 0xff) << 24); /* micro is mono, but apply */
255 data |= ((level_mic & 0xff) << 16); /* level on both channels */
256 data |= ((level_r & 0xff) << 8); /* line input right channel */
257 data |= (level_l & 0xff); /* line input left channel */
258
259 PCXHR_INPB(mgr, PCXHR_XLX_DATA); /* activate input codec */
260 /* send 32 bits (4 x 8 bits) */
261 for (i = 0; i < 32; i++, data <<= 1) {
262 PCXHR_OUTPB(mgr, PCXHR_XLX_DATA,
263 (data & 0x80000000) ? PCXHR_DATA_CODEC : 0);
264 }
265 PCXHR_INPB(mgr, PCXHR_XLX_RUER); /* close input level codec */
266 return 0;
267 }
268
269 static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level);
270
271 int hr222_sub_init(struct pcxhr_mgr *mgr)
272 {
273 unsigned char reg;
274
275 mgr->board_has_analog = 1; /* analog always available */
276 mgr->xlx_cfg = PCXHR_CFG_SYNCDSP_MASK;
277
278 reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS);
279 if (reg & PCXHR_STAT_MIC_CAPS)
280 mgr->board_has_mic = 1; /* microphone available */
281 dev_dbg(&mgr->pci->dev,
282 "MIC input available = %d\n", mgr->board_has_mic);
283
284 /* reset codec */
285 PCXHR_OUTPB(mgr, PCXHR_DSP_RESET,
286 PCXHR_DSP_RESET_DSP);
287 msleep(5);
288 mgr->dsp_reset = PCXHR_DSP_RESET_DSP |
289 PCXHR_DSP_RESET_MUTE |
290 PCXHR_DSP_RESET_CODEC;
291 PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, mgr->dsp_reset);
292 /* hr222_write_gpo(mgr, 0); does the same */
293 msleep(5);
294
295 /* config AKM */
296 hr222_config_akm(mgr, AKM_POWER_CONTROL_CMD);
297 hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD);
298 hr222_config_akm(mgr, AKM_UNMUTE_CMD);
299 hr222_config_akm(mgr, AKM_RESET_OFF_CMD);
300
301 /* init micro boost */
302 hr222_micro_boost(mgr, 0);
303
304 return 0;
305 }
306
307
308 /* calc PLL register */
309 /* TODO : there is a very similar fct in pcxhr.c */
310 static int hr222_pll_freq_register(unsigned int freq,
311 unsigned int *pllreg,
312 unsigned int *realfreq)
313 {
314 unsigned int reg;
315
316 if (freq < 6900 || freq > 219000)
317 return -EINVAL;
318 reg = (28224000 * 2) / freq;
319 reg = (reg - 1) / 2;
320 if (reg < 0x100)
321 *pllreg = reg + 0xC00;
322 else if (reg < 0x200)
323 *pllreg = reg + 0x800;
324 else if (reg < 0x400)
325 *pllreg = reg & 0x1ff;
326 else if (reg < 0x800) {
327 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
328 reg &= ~1;
329 } else {
330 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
331 reg &= ~3;
332 }
333 if (realfreq)
334 *realfreq = (28224000 / (reg + 1));
335 return 0;
336 }
337
338 int hr222_sub_set_clock(struct pcxhr_mgr *mgr,
339 unsigned int rate,
340 int *changed)
341 {
342 unsigned int speed, pllreg = 0;
343 int err;
344 unsigned realfreq = rate;
345
346 switch (mgr->use_clock_type) {
347 case HR22_CLOCK_TYPE_INTERNAL:
348 err = hr222_pll_freq_register(rate, &pllreg, &realfreq);
349 if (err)
350 return err;
351
352 mgr->xlx_cfg &= ~(PCXHR_CFG_CLOCKIN_SEL_MASK |
353 PCXHR_CFG_CLOCK_UER1_SEL_MASK);
354 break;
355 case HR22_CLOCK_TYPE_AES_SYNC:
356 mgr->xlx_cfg |= PCXHR_CFG_CLOCKIN_SEL_MASK;
357 mgr->xlx_cfg &= ~PCXHR_CFG_CLOCK_UER1_SEL_MASK;
358 break;
359 case HR22_CLOCK_TYPE_AES_1:
360 if (!mgr->board_has_aes1)
361 return -EINVAL;
362
363 mgr->xlx_cfg |= (PCXHR_CFG_CLOCKIN_SEL_MASK |
364 PCXHR_CFG_CLOCK_UER1_SEL_MASK);
365 break;
366 default:
367 return -EINVAL;
368 }
369 hr222_config_akm(mgr, AKM_MUTE_CMD);
370
371 if (mgr->use_clock_type == HR22_CLOCK_TYPE_INTERNAL) {
372 PCXHR_OUTPB(mgr, PCXHR_XLX_HIFREQ, pllreg >> 8);
373 PCXHR_OUTPB(mgr, PCXHR_XLX_LOFREQ, pllreg & 0xff);
374 }
375
376 /* set clock source */
377 PCXHR_OUTPB(mgr, PCXHR_XLX_CFG, mgr->xlx_cfg);
378
379 /* codec speed modes */
380 speed = rate < 55000 ? 0 : 1;
381 if (mgr->codec_speed != speed) {
382 mgr->codec_speed = speed;
383 if (speed == 0)
384 hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD);
385 else
386 hr222_config_akm(mgr, AKM_CLOCK_SUP_55K_CMD);
387 }
388
389 mgr->sample_rate_real = realfreq;
390 mgr->cur_clock_type = mgr->use_clock_type;
391
392 if (changed)
393 *changed = 1;
394
395 hr222_config_akm(mgr, AKM_UNMUTE_CMD);
396
397 dev_dbg(&mgr->pci->dev, "set_clock to %dHz (realfreq=%d pllreg=%x)\n",
398 rate, realfreq, pllreg);
399 return 0;
400 }
401
402 int hr222_get_external_clock(struct pcxhr_mgr *mgr,
403 enum pcxhr_clock_type clock_type,
404 int *sample_rate)
405 {
406 int rate, calc_rate = 0;
407 unsigned int ticks;
408 unsigned char mask, reg;
409
410 if (clock_type == HR22_CLOCK_TYPE_AES_SYNC) {
411
412 mask = (PCXHR_SUER_CLOCK_PRESENT_MASK |
413 PCXHR_SUER_DATA_PRESENT_MASK);
414 reg = PCXHR_STAT_FREQ_SYNC_MASK;
415
416 } else if (clock_type == HR22_CLOCK_TYPE_AES_1 && mgr->board_has_aes1) {
417
418 mask = (PCXHR_SUER1_CLOCK_PRESENT_MASK |
419 PCXHR_SUER1_DATA_PRESENT_MASK);
420 reg = PCXHR_STAT_FREQ_UER1_MASK;
421
422 } else {
423 dev_dbg(&mgr->pci->dev,
424 "get_external_clock : type %d not supported\n",
425 clock_type);
426 return -EINVAL; /* other clocks not supported */
427 }
428
429 if ((PCXHR_INPB(mgr, PCXHR_XLX_CSUER) & mask) != mask) {
430 dev_dbg(&mgr->pci->dev,
431 "get_external_clock(%d) = 0 Hz\n", clock_type);
432 *sample_rate = 0;
433 return 0; /* no external clock locked */
434 }
435
436 PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* calculate freq */
437
438 /* save the measured clock frequency */
439 reg |= PCXHR_STAT_FREQ_SAVE_MASK;
440
441 if (mgr->last_reg_stat != reg) {
442 udelay(500); /* wait min 2 cycles of lowest freq (8000) */
443 mgr->last_reg_stat = reg;
444 }
445
446 PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* save */
447
448 /* get the frequency */
449 ticks = (unsigned int)PCXHR_INPB(mgr, PCXHR_XLX_CFG);
450 ticks = (ticks & 0x03) << 8;
451 ticks |= (unsigned int)PCXHR_INPB(mgr, PCXHR_DSP_RESET);
452
453 if (ticks != 0)
454 calc_rate = 28224000 / ticks;
455 /* rounding */
456 if (calc_rate > 184200)
457 rate = 192000;
458 else if (calc_rate > 152200)
459 rate = 176400;
460 else if (calc_rate > 112000)
461 rate = 128000;
462 else if (calc_rate > 92100)
463 rate = 96000;
464 else if (calc_rate > 76100)
465 rate = 88200;
466 else if (calc_rate > 56000)
467 rate = 64000;
468 else if (calc_rate > 46050)
469 rate = 48000;
470 else if (calc_rate > 38050)
471 rate = 44100;
472 else if (calc_rate > 28000)
473 rate = 32000;
474 else if (calc_rate > 23025)
475 rate = 24000;
476 else if (calc_rate > 19025)
477 rate = 22050;
478 else if (calc_rate > 14000)
479 rate = 16000;
480 else if (calc_rate > 11512)
481 rate = 12000;
482 else if (calc_rate > 9512)
483 rate = 11025;
484 else if (calc_rate > 7000)
485 rate = 8000;
486 else
487 rate = 0;
488
489 dev_dbg(&mgr->pci->dev, "External clock is at %d Hz (measured %d Hz)\n",
490 rate, calc_rate);
491 *sample_rate = rate;
492 return 0;
493 }
494
495
496 int hr222_read_gpio(struct pcxhr_mgr *mgr, int is_gpi, int *value)
497 {
498 if (is_gpi) {
499 unsigned char reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS);
500 *value = (int)(reg & PCXHR_STAT_GPI_MASK) >>
501 PCXHR_STAT_GPI_OFFSET;
502 } else {
503 *value = (int)(mgr->dsp_reset & PCXHR_DSP_RESET_GPO_MASK) >>
504 PCXHR_DSP_RESET_GPO_OFFSET;
505 }
506 return 0;
507 }
508
509
510 int hr222_write_gpo(struct pcxhr_mgr *mgr, int value)
511 {
512 unsigned char reg = mgr->dsp_reset & ~PCXHR_DSP_RESET_GPO_MASK;
513
514 reg |= (unsigned char)(value << PCXHR_DSP_RESET_GPO_OFFSET) &
515 PCXHR_DSP_RESET_GPO_MASK;
516
517 PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, reg);
518 mgr->dsp_reset = reg;
519 return 0;
520 }
521
522 int hr222_manage_timecode(struct pcxhr_mgr *mgr, int enable)
523 {
524 if (enable)
525 mgr->dsp_reset |= PCXHR_DSP_RESET_SMPTE;
526 else
527 mgr->dsp_reset &= ~PCXHR_DSP_RESET_SMPTE;
528
529 PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, mgr->dsp_reset);
530 return 0;
531 }
532
533 int hr222_update_analog_audio_level(struct snd_pcxhr *chip,
534 int is_capture, int channel)
535 {
536 dev_dbg(chip->card->dev,
537 "hr222_update_analog_audio_level(%s chan=%d)\n",
538 is_capture ? "capture" : "playback", channel);
539 if (is_capture) {
540 int level_l, level_r, level_mic;
541 /* we have to update all levels */
542 if (chip->analog_capture_active) {
543 level_l = chip->analog_capture_volume[0];
544 level_r = chip->analog_capture_volume[1];
545 } else {
546 level_l = HR222_LINE_CAPTURE_LEVEL_MIN;
547 level_r = HR222_LINE_CAPTURE_LEVEL_MIN;
548 }
549 if (chip->mic_active)
550 level_mic = chip->mic_volume;
551 else
552 level_mic = HR222_MICRO_CAPTURE_LEVEL_MIN;
553 return hr222_set_hw_capture_level(chip->mgr,
554 level_l, level_r, level_mic);
555 } else {
556 int vol;
557 if (chip->analog_playback_active[channel])
558 vol = chip->analog_playback_volume[channel];
559 else
560 vol = HR222_LINE_PLAYBACK_LEVEL_MIN;
561 return hr222_set_hw_playback_level(chip->mgr, channel, vol);
562 }
563 }
564
565
566 /*texts[5] = {"Line", "Digital", "Digi+SRC", "Mic", "Line+Mic"}*/
567 #define SOURCE_LINE 0
568 #define SOURCE_DIGITAL 1
569 #define SOURCE_DIGISRC 2
570 #define SOURCE_MIC 3
571 #define SOURCE_LINEMIC 4
572
573 int hr222_set_audio_source(struct snd_pcxhr *chip)
574 {
575 int digital = 0;
576 /* default analog source */
577 chip->mgr->xlx_cfg &= ~(PCXHR_CFG_SRC_MASK |
578 PCXHR_CFG_DATAIN_SEL_MASK |
579 PCXHR_CFG_DATA_UER1_SEL_MASK);
580
581 if (chip->audio_capture_source == SOURCE_DIGISRC) {
582 chip->mgr->xlx_cfg |= PCXHR_CFG_SRC_MASK;
583 digital = 1;
584 } else {
585 if (chip->audio_capture_source == SOURCE_DIGITAL)
586 digital = 1;
587 }
588 if (digital) {
589 chip->mgr->xlx_cfg |= PCXHR_CFG_DATAIN_SEL_MASK;
590 if (chip->mgr->board_has_aes1) {
591 /* get data from the AES1 plug */
592 chip->mgr->xlx_cfg |= PCXHR_CFG_DATA_UER1_SEL_MASK;
593 }
594 /* chip->mic_active = 0; */
595 /* chip->analog_capture_active = 0; */
596 } else {
597 int update_lvl = 0;
598 chip->analog_capture_active = 0;
599 chip->mic_active = 0;
600 if (chip->audio_capture_source == SOURCE_LINE ||
601 chip->audio_capture_source == SOURCE_LINEMIC) {
602 if (chip->analog_capture_active == 0)
603 update_lvl = 1;
604 chip->analog_capture_active = 1;
605 }
606 if (chip->audio_capture_source == SOURCE_MIC ||
607 chip->audio_capture_source == SOURCE_LINEMIC) {
608 if (chip->mic_active == 0)
609 update_lvl = 1;
610 chip->mic_active = 1;
611 }
612 if (update_lvl) {
613 /* capture: update all 3 mutes/unmutes with one call */
614 hr222_update_analog_audio_level(chip, 1, 0);
615 }
616 }
617 /* set the source infos (max 3 bits modified) */
618 PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CFG, chip->mgr->xlx_cfg);
619 return 0;
620 }
621
622
623 int hr222_iec958_capture_byte(struct snd_pcxhr *chip,
624 int aes_idx, unsigned char *aes_bits)
625 {
626 unsigned char idx = (unsigned char)(aes_idx * 8);
627 unsigned char temp = 0;
628 unsigned char mask = chip->mgr->board_has_aes1 ?
629 PCXHR_SUER1_BIT_C_READ_MASK : PCXHR_SUER_BIT_C_READ_MASK;
630 int i;
631 for (i = 0; i < 8; i++) {
632 PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx++); /* idx < 192 */
633 temp <<= 1;
634 if (PCXHR_INPB(chip->mgr, PCXHR_XLX_CSUER) & mask)
635 temp |= 1;
636 }
637 dev_dbg(chip->card->dev, "read iec958 AES %d byte %d = 0x%x\n",
638 chip->chip_idx, aes_idx, temp);
639 *aes_bits = temp;
640 return 0;
641 }
642
643
644 int hr222_iec958_update_byte(struct snd_pcxhr *chip,
645 int aes_idx, unsigned char aes_bits)
646 {
647 int i;
648 unsigned char new_bits = aes_bits;
649 unsigned char old_bits = chip->aes_bits[aes_idx];
650 unsigned char idx = (unsigned char)(aes_idx * 8);
651 for (i = 0; i < 8; i++) {
652 if ((old_bits & 0x01) != (new_bits & 0x01)) {
653 /* idx < 192 */
654 PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx);
655 /* write C and U bit */
656 PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CSUER, new_bits&0x01 ?
657 PCXHR_SUER_BIT_C_WRITE_MASK : 0);
658 }
659 idx++;
660 old_bits >>= 1;
661 new_bits >>= 1;
662 }
663 chip->aes_bits[aes_idx] = aes_bits;
664 return 0;
665 }
666
667 static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level)
668 {
669 unsigned char boost_mask;
670 boost_mask = (unsigned char) (level << PCXHR_SELMIC_PREAMPLI_OFFSET);
671 if (boost_mask & (~PCXHR_SELMIC_PREAMPLI_MASK))
672 return; /* only values form 0 to 3 accepted */
673
674 mgr->xlx_selmic &= ~PCXHR_SELMIC_PREAMPLI_MASK;
675 mgr->xlx_selmic |= boost_mask;
676
677 PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic);
678
679 dev_dbg(&mgr->pci->dev, "hr222_micro_boost : set %x\n", boost_mask);
680 }
681
682 static void hr222_phantom_power(struct pcxhr_mgr *mgr, int power)
683 {
684 if (power)
685 mgr->xlx_selmic |= PCXHR_SELMIC_PHANTOM_ALIM;
686 else
687 mgr->xlx_selmic &= ~PCXHR_SELMIC_PHANTOM_ALIM;
688
689 PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic);
690
691 dev_dbg(&mgr->pci->dev, "hr222_phantom_power : set %d\n", power);
692 }
693
694
695 /* mic level */
696 static const DECLARE_TLV_DB_SCALE(db_scale_mic_hr222, -9850, 50, 650);
697
698 static int hr222_mic_vol_info(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_info *uinfo)
700 {
701 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
702 uinfo->count = 1;
703 uinfo->value.integer.min = HR222_MICRO_CAPTURE_LEVEL_MIN; /* -98 dB */
704 /* gains from 9 dB to 31.5 dB not recommended; use micboost instead */
705 uinfo->value.integer.max = HR222_MICRO_CAPTURE_LEVEL_MAX; /* +7 dB */
706 return 0;
707 }
708
709 static int hr222_mic_vol_get(struct snd_kcontrol *kcontrol,
710 struct snd_ctl_elem_value *ucontrol)
711 {
712 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
713 mutex_lock(&chip->mgr->mixer_mutex);
714 ucontrol->value.integer.value[0] = chip->mic_volume;
715 mutex_unlock(&chip->mgr->mixer_mutex);
716 return 0;
717 }
718
719 static int hr222_mic_vol_put(struct snd_kcontrol *kcontrol,
720 struct snd_ctl_elem_value *ucontrol)
721 {
722 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
723 int changed = 0;
724 mutex_lock(&chip->mgr->mixer_mutex);
725 if (chip->mic_volume != ucontrol->value.integer.value[0]) {
726 changed = 1;
727 chip->mic_volume = ucontrol->value.integer.value[0];
728 hr222_update_analog_audio_level(chip, 1, 0);
729 }
730 mutex_unlock(&chip->mgr->mixer_mutex);
731 return changed;
732 }
733
734 static const struct snd_kcontrol_new hr222_control_mic_level = {
735 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
736 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
737 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
738 .name = "Mic Capture Volume",
739 .info = hr222_mic_vol_info,
740 .get = hr222_mic_vol_get,
741 .put = hr222_mic_vol_put,
742 .tlv = { .p = db_scale_mic_hr222 },
743 };
744
745
746 /* mic boost level */
747 static const DECLARE_TLV_DB_SCALE(db_scale_micboost_hr222, 0, 1800, 5400);
748
749 static int hr222_mic_boost_info(struct snd_kcontrol *kcontrol,
750 struct snd_ctl_elem_info *uinfo)
751 {
752 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
753 uinfo->count = 1;
754 uinfo->value.integer.min = 0; /* 0 dB */
755 uinfo->value.integer.max = 3; /* 54 dB */
756 return 0;
757 }
758
759 static int hr222_mic_boost_get(struct snd_kcontrol *kcontrol,
760 struct snd_ctl_elem_value *ucontrol)
761 {
762 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
763 mutex_lock(&chip->mgr->mixer_mutex);
764 ucontrol->value.integer.value[0] = chip->mic_boost;
765 mutex_unlock(&chip->mgr->mixer_mutex);
766 return 0;
767 }
768
769 static int hr222_mic_boost_put(struct snd_kcontrol *kcontrol,
770 struct snd_ctl_elem_value *ucontrol)
771 {
772 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
773 int changed = 0;
774 mutex_lock(&chip->mgr->mixer_mutex);
775 if (chip->mic_boost != ucontrol->value.integer.value[0]) {
776 changed = 1;
777 chip->mic_boost = ucontrol->value.integer.value[0];
778 hr222_micro_boost(chip->mgr, chip->mic_boost);
779 }
780 mutex_unlock(&chip->mgr->mixer_mutex);
781 return changed;
782 }
783
784 static const struct snd_kcontrol_new hr222_control_mic_boost = {
785 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
786 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
787 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
788 .name = "MicBoost Capture Volume",
789 .info = hr222_mic_boost_info,
790 .get = hr222_mic_boost_get,
791 .put = hr222_mic_boost_put,
792 .tlv = { .p = db_scale_micboost_hr222 },
793 };
794
795
796 /******************* Phantom power switch *******************/
797 #define hr222_phantom_power_info snd_ctl_boolean_mono_info
798
799 static int hr222_phantom_power_get(struct snd_kcontrol *kcontrol,
800 struct snd_ctl_elem_value *ucontrol)
801 {
802 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
803 mutex_lock(&chip->mgr->mixer_mutex);
804 ucontrol->value.integer.value[0] = chip->phantom_power;
805 mutex_unlock(&chip->mgr->mixer_mutex);
806 return 0;
807 }
808
809 static int hr222_phantom_power_put(struct snd_kcontrol *kcontrol,
810 struct snd_ctl_elem_value *ucontrol)
811 {
812 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
813 int power, changed = 0;
814
815 mutex_lock(&chip->mgr->mixer_mutex);
816 power = !!ucontrol->value.integer.value[0];
817 if (chip->phantom_power != power) {
818 hr222_phantom_power(chip->mgr, power);
819 chip->phantom_power = power;
820 changed = 1;
821 }
822 mutex_unlock(&chip->mgr->mixer_mutex);
823 return changed;
824 }
825
826 static const struct snd_kcontrol_new hr222_phantom_power_switch = {
827 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
828 .name = "Phantom Power Switch",
829 .info = hr222_phantom_power_info,
830 .get = hr222_phantom_power_get,
831 .put = hr222_phantom_power_put,
832 };
833
834
835 int hr222_add_mic_controls(struct snd_pcxhr *chip)
836 {
837 int err;
838 if (!chip->mgr->board_has_mic)
839 return 0;
840
841 /* controls */
842 err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_level,
843 chip));
844 if (err < 0)
845 return err;
846
847 err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_boost,
848 chip));
849 if (err < 0)
850 return err;
851
852 err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_phantom_power_switch,
853 chip));
854 return err;
855 }
Linux with added FPC-III support