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WIP FPC-III support
[linux/fpc-iii.git] / sound / soc / codecs / adau1977.c
blob8260f49caa2468691746bb8a9cbd42c456503ae4
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADAU1977/ADAU1978/ADAU1979 driver
4 *
5 * Copyright 2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/slab.h>
18
19 #include <sound/core.h>
20 #include <sound/initval.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/tlv.h>
25
26 #include <dt-bindings/sound/adi,adau1977.h>
27
28 #include "adau1977.h"
29
30 #define ADAU1977_REG_POWER 0x00
31 #define ADAU1977_REG_PLL 0x01
32 #define ADAU1977_REG_BOOST 0x02
33 #define ADAU1977_REG_MICBIAS 0x03
34 #define ADAU1977_REG_BLOCK_POWER_SAI 0x04
35 #define ADAU1977_REG_SAI_CTRL0 0x05
36 #define ADAU1977_REG_SAI_CTRL1 0x06
37 #define ADAU1977_REG_CMAP12 0x07
38 #define ADAU1977_REG_CMAP34 0x08
39 #define ADAU1977_REG_SAI_OVERTEMP 0x09
40 #define ADAU1977_REG_POST_ADC_GAIN(x) (0x0a + (x))
41 #define ADAU1977_REG_MISC_CONTROL 0x0e
42 #define ADAU1977_REG_DIAG_CONTROL 0x10
43 #define ADAU1977_REG_STATUS(x) (0x11 + (x))
44 #define ADAU1977_REG_DIAG_IRQ1 0x15
45 #define ADAU1977_REG_DIAG_IRQ2 0x16
46 #define ADAU1977_REG_ADJUST1 0x17
47 #define ADAU1977_REG_ADJUST2 0x18
48 #define ADAU1977_REG_ADC_CLIP 0x19
49 #define ADAU1977_REG_DC_HPF_CAL 0x1a
50
51 #define ADAU1977_POWER_RESET BIT(7)
52 #define ADAU1977_POWER_PWUP BIT(0)
53
54 #define ADAU1977_PLL_CLK_S BIT(4)
55 #define ADAU1977_PLL_MCS_MASK 0x7
56
57 #define ADAU1977_MICBIAS_MB_VOLTS_MASK 0xf0
58 #define ADAU1977_MICBIAS_MB_VOLTS_OFFSET 4
59
60 #define ADAU1977_BLOCK_POWER_SAI_LR_POL BIT(7)
61 #define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE BIT(6)
62 #define ADAU1977_BLOCK_POWER_SAI_LDO_EN BIT(5)
63
64 #define ADAU1977_SAI_CTRL0_FMT_MASK (0x3 << 6)
65 #define ADAU1977_SAI_CTRL0_FMT_I2S (0x0 << 6)
66 #define ADAU1977_SAI_CTRL0_FMT_LJ (0x1 << 6)
67 #define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT (0x2 << 6)
68 #define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT (0x3 << 6)
69
70 #define ADAU1977_SAI_CTRL0_SAI_MASK (0x7 << 3)
71 #define ADAU1977_SAI_CTRL0_SAI_I2S (0x0 << 3)
72 #define ADAU1977_SAI_CTRL0_SAI_TDM_2 (0x1 << 3)
73 #define ADAU1977_SAI_CTRL0_SAI_TDM_4 (0x2 << 3)
74 #define ADAU1977_SAI_CTRL0_SAI_TDM_8 (0x3 << 3)
75 #define ADAU1977_SAI_CTRL0_SAI_TDM_16 (0x4 << 3)
76
77 #define ADAU1977_SAI_CTRL0_FS_MASK (0x7)
78 #define ADAU1977_SAI_CTRL0_FS_8000_12000 (0x0)
79 #define ADAU1977_SAI_CTRL0_FS_16000_24000 (0x1)
80 #define ADAU1977_SAI_CTRL0_FS_32000_48000 (0x2)
81 #define ADAU1977_SAI_CTRL0_FS_64000_96000 (0x3)
82 #define ADAU1977_SAI_CTRL0_FS_128000_192000 (0x4)
83
84 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK (0x3 << 5)
85 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32 (0x0 << 5)
86 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24 (0x1 << 5)
87 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16 (0x2 << 5)
88 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK (0x1 << 4)
89 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT (0x1 << 4)
90 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT (0x0 << 4)
91 #define ADAU1977_SAI_CTRL1_LRCLK_PULSE BIT(3)
92 #define ADAU1977_SAI_CTRL1_MSB BIT(2)
93 #define ADAU1977_SAI_CTRL1_BCLKRATE_16 (0x1 << 1)
94 #define ADAU1977_SAI_CTRL1_BCLKRATE_32 (0x0 << 1)
95 #define ADAU1977_SAI_CTRL1_BCLKRATE_MASK (0x1 << 1)
96 #define ADAU1977_SAI_CTRL1_MASTER BIT(0)
97
98 #define ADAU1977_SAI_OVERTEMP_DRV_C(x) BIT(4 + (x))
99 #define ADAU1977_SAI_OVERTEMP_DRV_HIZ BIT(3)
100
101 #define ADAU1977_MISC_CONTROL_SUM_MODE_MASK (0x3 << 6)
102 #define ADAU1977_MISC_CONTROL_SUM_MODE_1CH (0x2 << 6)
103 #define ADAU1977_MISC_CONTROL_SUM_MODE_2CH (0x1 << 6)
104 #define ADAU1977_MISC_CONTROL_SUM_MODE_4CH (0x0 << 6)
105 #define ADAU1977_MISC_CONTROL_MMUTE BIT(4)
106 #define ADAU1977_MISC_CONTROL_DC_CAL BIT(0)
107
108 #define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET 4
109 #define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET 0
110
111 struct adau1977 {
112 struct regmap *regmap;
113 bool right_j;
114 unsigned int sysclk;
115 enum adau1977_sysclk_src sysclk_src;
116 struct gpio_desc *reset_gpio;
117 enum adau1977_type type;
118
119 struct regulator *avdd_reg;
120 struct regulator *dvdd_reg;
121
122 struct snd_pcm_hw_constraint_list constraints;
123
124 struct device *dev;
125 void (*switch_mode)(struct device *dev);
126
127 unsigned int max_master_fs;
128 unsigned int slot_width;
129 bool enabled;
130 bool master;
131 };
132
133 static const struct reg_default adau1977_reg_defaults[] = {
134 { 0x00, 0x00 },
135 { 0x01, 0x41 },
136 { 0x02, 0x4a },
137 { 0x03, 0x7d },
138 { 0x04, 0x3d },
139 { 0x05, 0x02 },
140 { 0x06, 0x00 },
141 { 0x07, 0x10 },
142 { 0x08, 0x32 },
143 { 0x09, 0xf0 },
144 { 0x0a, 0xa0 },
145 { 0x0b, 0xa0 },
146 { 0x0c, 0xa0 },
147 { 0x0d, 0xa0 },
148 { 0x0e, 0x02 },
149 { 0x10, 0x0f },
150 { 0x15, 0x20 },
151 { 0x16, 0x00 },
152 { 0x17, 0x00 },
153 { 0x18, 0x00 },
154 { 0x1a, 0x00 },
155 };
156
157 static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
158
159 static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
160 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
161 3, 0, NULL, 0)
162 };
163
164 static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
165 SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
166 4, 0, NULL, 0),
167
168 SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
169 SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
170 SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
171 SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
172
173 SND_SOC_DAPM_INPUT("AIN1"),
174 SND_SOC_DAPM_INPUT("AIN2"),
175 SND_SOC_DAPM_INPUT("AIN3"),
176 SND_SOC_DAPM_INPUT("AIN4"),
177
178 SND_SOC_DAPM_OUTPUT("VREF"),
179 };
180
181 static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
182 { "ADC1", NULL, "AIN1" },
183 { "ADC2", NULL, "AIN2" },
184 { "ADC3", NULL, "AIN3" },
185 { "ADC4", NULL, "AIN4" },
186
187 { "ADC1", NULL, "Vref" },
188 { "ADC2", NULL, "Vref" },
189 { "ADC3", NULL, "Vref" },
190 { "ADC4", NULL, "Vref" },
191
192 { "VREF", NULL, "Vref" },
193 };
194
195 #define ADAU1977_VOLUME(x) \
196 SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
197 ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
198 0, 255, 1, adau1977_adc_gain)
199
200 #define ADAU1977_HPF_SWITCH(x) \
201 SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
202 ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
203
204 #define ADAU1977_DC_SUB_SWITCH(x) \
205 SOC_SINGLE("ADC" #x " DC Subtraction Capture Switch", \
206 ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
207
208 static const struct snd_kcontrol_new adau1977_snd_controls[] = {
209 ADAU1977_VOLUME(1),
210 ADAU1977_VOLUME(2),
211 ADAU1977_VOLUME(3),
212 ADAU1977_VOLUME(4),
213
214 ADAU1977_HPF_SWITCH(1),
215 ADAU1977_HPF_SWITCH(2),
216 ADAU1977_HPF_SWITCH(3),
217 ADAU1977_HPF_SWITCH(4),
218
219 ADAU1977_DC_SUB_SWITCH(1),
220 ADAU1977_DC_SUB_SWITCH(2),
221 ADAU1977_DC_SUB_SWITCH(3),
222 ADAU1977_DC_SUB_SWITCH(4),
223 };
224
225 static int adau1977_reset(struct adau1977 *adau1977)
226 {
227 int ret;
228
229 /*
230 * The reset bit is obviously volatile, but we need to be able to cache
231 * the other bits in the register, so we can't just mark the whole
232 * register as volatile. Since this is the only place where we'll ever
233 * touch the reset bit just bypass the cache for this operation.
234 */
235 regcache_cache_bypass(adau1977->regmap, true);
236 ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
237 ADAU1977_POWER_RESET);
238 regcache_cache_bypass(adau1977->regmap, false);
239 if (ret)
240 return ret;
241
242 return ret;
243 }
244
245 /*
246 * Returns the appropriate setting for ths FS field in the CTRL0 register
247 * depending on the rate.
248 */
249 static int adau1977_lookup_fs(unsigned int rate)
250 {
251 if (rate >= 8000 && rate <= 12000)
252 return ADAU1977_SAI_CTRL0_FS_8000_12000;
253 else if (rate >= 16000 && rate <= 24000)
254 return ADAU1977_SAI_CTRL0_FS_16000_24000;
255 else if (rate >= 32000 && rate <= 48000)
256 return ADAU1977_SAI_CTRL0_FS_32000_48000;
257 else if (rate >= 64000 && rate <= 96000)
258 return ADAU1977_SAI_CTRL0_FS_64000_96000;
259 else if (rate >= 128000 && rate <= 192000)
260 return ADAU1977_SAI_CTRL0_FS_128000_192000;
261 else
262 return -EINVAL;
263 }
264
265 static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
266 unsigned int fs)
267 {
268 unsigned int mcs;
269
270 /*
271 * rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
272 * => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
273 * => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
274 */
275
276 rate *= 512 >> fs;
277
278 if (adau1977->sysclk % rate != 0)
279 return -EINVAL;
280
281 mcs = adau1977->sysclk / rate;
282
283 /* The factors configured by MCS are 1, 2, 3, 4, 6 */
284 if (mcs < 1 || mcs > 6 || mcs == 5)
285 return -EINVAL;
286
287 mcs = mcs - 1;
288 if (mcs == 5)
289 mcs = 4;
290
291 return mcs;
292 }
293
294 static int adau1977_hw_params(struct snd_pcm_substream *substream,
295 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
296 {
297 struct snd_soc_component *component = dai->component;
298 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
299 unsigned int rate = params_rate(params);
300 unsigned int slot_width;
301 unsigned int ctrl0, ctrl0_mask;
302 unsigned int ctrl1;
303 int mcs, fs;
304 int ret;
305
306 fs = adau1977_lookup_fs(rate);
307 if (fs < 0)
308 return fs;
309
310 if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
311 mcs = adau1977_lookup_mcs(adau1977, rate, fs);
312 if (mcs < 0)
313 return mcs;
314 } else {
315 mcs = 0;
316 }
317
318 ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
319 ctrl0 = fs;
320
321 if (adau1977->right_j) {
322 switch (params_width(params)) {
323 case 16:
324 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
325 break;
326 case 24:
327 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
328 break;
329 default:
330 return -EINVAL;
331 }
332 ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
333 }
334
335 if (adau1977->master) {
336 switch (params_width(params)) {
337 case 16:
338 ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
339 slot_width = 16;
340 break;
341 case 24:
342 case 32:
343 ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
344 slot_width = 32;
345 break;
346 default:
347 return -EINVAL;
348 }
349
350 /* In TDM mode there is a fixed slot width */
351 if (adau1977->slot_width)
352 slot_width = adau1977->slot_width;
353
354 if (slot_width == 16)
355 ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
356 else
357 ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
358
359 ret = regmap_update_bits(adau1977->regmap,
360 ADAU1977_REG_SAI_CTRL1,
361 ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
362 ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
363 ctrl1);
364 if (ret < 0)
365 return ret;
366 }
367
368 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
369 ctrl0_mask, ctrl0);
370 if (ret < 0)
371 return ret;
372
373 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
374 ADAU1977_PLL_MCS_MASK, mcs);
375 }
376
377 static int adau1977_power_disable(struct adau1977 *adau1977)
378 {
379 int ret = 0;
380
381 if (!adau1977->enabled)
382 return 0;
383
384 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
385 ADAU1977_POWER_PWUP, 0);
386 if (ret)
387 return ret;
388
389 regcache_mark_dirty(adau1977->regmap);
390
391 gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
392
393 regcache_cache_only(adau1977->regmap, true);
394
395 regulator_disable(adau1977->avdd_reg);
396 if (adau1977->dvdd_reg)
397 regulator_disable(adau1977->dvdd_reg);
398
399 adau1977->enabled = false;
400
401 return 0;
402 }
403
404 static int adau1977_power_enable(struct adau1977 *adau1977)
405 {
406 unsigned int val;
407 int ret = 0;
408
409 if (adau1977->enabled)
410 return 0;
411
412 ret = regulator_enable(adau1977->avdd_reg);
413 if (ret)
414 return ret;
415
416 if (adau1977->dvdd_reg) {
417 ret = regulator_enable(adau1977->dvdd_reg);
418 if (ret)
419 goto err_disable_avdd;
420 }
421
422 gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
423
424 regcache_cache_only(adau1977->regmap, false);
425
426 if (adau1977->switch_mode)
427 adau1977->switch_mode(adau1977->dev);
428
429 ret = adau1977_reset(adau1977);
430 if (ret)
431 goto err_disable_dvdd;
432
433 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
434 ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
435 if (ret)
436 goto err_disable_dvdd;
437
438 ret = regcache_sync(adau1977->regmap);
439 if (ret)
440 goto err_disable_dvdd;
441
442 /*
443 * The PLL register is not affected by the software reset. It is
444 * possible that the value of the register was changed to the
445 * default value while we were in cache only mode. In this case
446 * regcache_sync will skip over it and we have to manually sync
447 * it.
448 */
449 ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
450 if (ret)
451 goto err_disable_dvdd;
452
453 if (val == 0x41) {
454 regcache_cache_bypass(adau1977->regmap, true);
455 ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
456 0x41);
457 if (ret)
458 goto err_disable_dvdd;
459 regcache_cache_bypass(adau1977->regmap, false);
460 }
461
462 adau1977->enabled = true;
463
464 return ret;
465
466 err_disable_dvdd:
467 if (adau1977->dvdd_reg)
468 regulator_disable(adau1977->dvdd_reg);
469 err_disable_avdd:
470 regulator_disable(adau1977->avdd_reg);
471 return ret;
472 }
473
474 static int adau1977_set_bias_level(struct snd_soc_component *component,
475 enum snd_soc_bias_level level)
476 {
477 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
478 int ret = 0;
479
480 switch (level) {
481 case SND_SOC_BIAS_ON:
482 break;
483 case SND_SOC_BIAS_PREPARE:
484 break;
485 case SND_SOC_BIAS_STANDBY:
486 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
487 ret = adau1977_power_enable(adau1977);
488 break;
489 case SND_SOC_BIAS_OFF:
490 ret = adau1977_power_disable(adau1977);
491 break;
492 }
493
494 return ret;
495 }
496
497 static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
498 unsigned int rx_mask, int slots, int width)
499 {
500 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
501 unsigned int ctrl0, ctrl1, drv;
502 unsigned int slot[4];
503 unsigned int i;
504 int ret;
505
506 if (slots == 0) {
507 /* 0 = No fixed slot width */
508 adau1977->slot_width = 0;
509 adau1977->max_master_fs = 192000;
510 return regmap_update_bits(adau1977->regmap,
511 ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
512 ADAU1977_SAI_CTRL0_SAI_I2S);
513 }
514
515 if (rx_mask == 0 || tx_mask != 0)
516 return -EINVAL;
517
518 drv = 0;
519 for (i = 0; i < 4; i++) {
520 slot[i] = __ffs(rx_mask);
521 drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
522 rx_mask &= ~(1 << slot[i]);
523 if (slot[i] >= slots)
524 return -EINVAL;
525 if (rx_mask == 0)
526 break;
527 }
528
529 if (rx_mask != 0)
530 return -EINVAL;
531
532 switch (width) {
533 case 16:
534 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
535 break;
536 case 24:
537 /* We can only generate 16 bit or 32 bit wide slots */
538 if (adau1977->master)
539 return -EINVAL;
540 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
541 break;
542 case 32:
543 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
544 break;
545 default:
546 return -EINVAL;
547 }
548
549 switch (slots) {
550 case 2:
551 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
552 break;
553 case 4:
554 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
555 break;
556 case 8:
557 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
558 break;
559 case 16:
560 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
561 break;
562 default:
563 return -EINVAL;
564 }
565
566 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
567 ADAU1977_SAI_OVERTEMP_DRV_C(0) |
568 ADAU1977_SAI_OVERTEMP_DRV_C(1) |
569 ADAU1977_SAI_OVERTEMP_DRV_C(2) |
570 ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
571 if (ret)
572 return ret;
573
574 ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
575 (slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
576 (slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
577 if (ret)
578 return ret;
579
580 ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
581 (slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
582 (slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
583 if (ret)
584 return ret;
585
586 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
587 ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
588 if (ret)
589 return ret;
590
591 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
592 ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
593 if (ret)
594 return ret;
595
596 adau1977->slot_width = width;
597
598 /* In master mode the maximum bitclock is 24.576 MHz */
599 adau1977->max_master_fs = min(192000, 24576000 / width / slots);
600
601 return 0;
602 }
603
604 static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
605 {
606 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
607 unsigned int val;
608
609 if (mute)
610 val = ADAU1977_MISC_CONTROL_MMUTE;
611 else
612 val = 0;
613
614 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
615 ADAU1977_MISC_CONTROL_MMUTE, val);
616 }
617
618 static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
619 {
620 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
621 unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
622 bool invert_lrclk;
623 int ret;
624
625 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
626 case SND_SOC_DAIFMT_CBS_CFS:
627 adau1977->master = false;
628 break;
629 case SND_SOC_DAIFMT_CBM_CFM:
630 ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
631 adau1977->master = true;
632 break;
633 default:
634 return -EINVAL;
635 }
636
637 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
638 case SND_SOC_DAIFMT_NB_NF:
639 invert_lrclk = false;
640 break;
641 case SND_SOC_DAIFMT_IB_NF:
642 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
643 invert_lrclk = false;
644 break;
645 case SND_SOC_DAIFMT_NB_IF:
646 invert_lrclk = true;
647 break;
648 case SND_SOC_DAIFMT_IB_IF:
649 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
650 invert_lrclk = true;
651 break;
652 default:
653 return -EINVAL;
654 }
655
656 adau1977->right_j = false;
657 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
658 case SND_SOC_DAIFMT_I2S:
659 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
660 break;
661 case SND_SOC_DAIFMT_LEFT_J:
662 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
663 invert_lrclk = !invert_lrclk;
664 break;
665 case SND_SOC_DAIFMT_RIGHT_J:
666 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
667 adau1977->right_j = true;
668 invert_lrclk = !invert_lrclk;
669 break;
670 case SND_SOC_DAIFMT_DSP_A:
671 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
672 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
673 invert_lrclk = false;
674 break;
675 case SND_SOC_DAIFMT_DSP_B:
676 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
677 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
678 invert_lrclk = false;
679 break;
680 default:
681 return -EINVAL;
682 }
683
684 if (invert_lrclk)
685 block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
686
687 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
688 ADAU1977_BLOCK_POWER_SAI_LR_POL |
689 ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
690 if (ret)
691 return ret;
692
693 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
694 ADAU1977_SAI_CTRL0_FMT_MASK,
695 ctrl0);
696 if (ret)
697 return ret;
698
699 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
700 ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
701 ctrl1);
702 }
703
704 static int adau1977_startup(struct snd_pcm_substream *substream,
705 struct snd_soc_dai *dai)
706 {
707 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
708 u64 formats = 0;
709
710 if (adau1977->slot_width == 16)
711 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
712 else if (adau1977->right_j || adau1977->slot_width == 24)
713 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
714 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
715
716 snd_pcm_hw_constraint_list(substream->runtime, 0,
717 SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
718
719 if (adau1977->master)
720 snd_pcm_hw_constraint_minmax(substream->runtime,
721 SNDRV_PCM_HW_PARAM_RATE, 8000, adau1977->max_master_fs);
722
723 if (formats != 0)
724 snd_pcm_hw_constraint_mask64(substream->runtime,
725 SNDRV_PCM_HW_PARAM_FORMAT, formats);
726
727 return 0;
728 }
729
730 static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
731 {
732 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
733 unsigned int val;
734
735 if (tristate)
736 val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
737 else
738 val = 0;
739
740 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
741 ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
742 }
743
744 static const struct snd_soc_dai_ops adau1977_dai_ops = {
745 .startup = adau1977_startup,
746 .hw_params = adau1977_hw_params,
747 .mute_stream = adau1977_mute,
748 .set_fmt = adau1977_set_dai_fmt,
749 .set_tdm_slot = adau1977_set_tdm_slot,
750 .set_tristate = adau1977_set_tristate,
751 };
752
753 static struct snd_soc_dai_driver adau1977_dai = {
754 .name = "adau1977-hifi",
755 .capture = {
756 .stream_name = "Capture",
757 .channels_min = 1,
758 .channels_max = 4,
759 .rates = SNDRV_PCM_RATE_KNOT,
760 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
761 SNDRV_PCM_FMTBIT_S32_LE,
762 .sig_bits = 24,
763 },
764 .ops = &adau1977_dai_ops,
765 };
766
767 static const unsigned int adau1977_rates[] = {
768 8000, 16000, 32000, 64000, 128000,
769 11025, 22050, 44100, 88200, 172400,
770 12000, 24000, 48000, 96000, 192000,
771 };
772
773 #define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
774 #define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
775 #define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
776 /* All rates >= 32000 */
777 #define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
778
779 static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
780 {
781 unsigned int mcs;
782
783 if (mclk % (base_freq * 128) != 0)
784 return false;
785
786 mcs = mclk / (128 * base_freq);
787 if (mcs < 1 || mcs > 6 || mcs == 5)
788 return false;
789
790 return true;
791 }
792
793 static int adau1977_set_sysclk(struct snd_soc_component *component,
794 int clk_id, int source, unsigned int freq, int dir)
795 {
796 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
797 unsigned int mask = 0;
798 unsigned int clk_src;
799 unsigned int ret;
800
801 if (dir != SND_SOC_CLOCK_IN)
802 return -EINVAL;
803
804 if (clk_id != ADAU1977_SYSCLK)
805 return -EINVAL;
806
807 switch (source) {
808 case ADAU1977_SYSCLK_SRC_MCLK:
809 clk_src = 0;
810 break;
811 case ADAU1977_SYSCLK_SRC_LRCLK:
812 clk_src = ADAU1977_PLL_CLK_S;
813 break;
814 default:
815 return -EINVAL;
816 }
817
818 if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
819 if (freq < 4000000 || freq > 36864000)
820 return -EINVAL;
821
822 if (adau1977_check_sysclk(freq, 32000))
823 mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
824 if (adau1977_check_sysclk(freq, 44100))
825 mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
826 if (adau1977_check_sysclk(freq, 48000))
827 mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
828
829 if (mask == 0)
830 return -EINVAL;
831 } else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
832 mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
833 }
834
835 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
836 ADAU1977_PLL_CLK_S, clk_src);
837 if (ret)
838 return ret;
839
840 adau1977->constraints.mask = mask;
841 adau1977->sysclk_src = source;
842 adau1977->sysclk = freq;
843
844 return 0;
845 }
846
847 static int adau1977_component_probe(struct snd_soc_component *component)
848 {
849 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
850 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
851 int ret;
852
853 switch (adau1977->type) {
854 case ADAU1977:
855 ret = snd_soc_dapm_new_controls(dapm,
856 adau1977_micbias_dapm_widgets,
857 ARRAY_SIZE(adau1977_micbias_dapm_widgets));
858 if (ret < 0)
859 return ret;
860 break;
861 default:
862 break;
863 }
864
865 return 0;
866 }
867
868 static const struct snd_soc_component_driver adau1977_component_driver = {
869 .probe = adau1977_component_probe,
870 .set_bias_level = adau1977_set_bias_level,
871 .set_sysclk = adau1977_set_sysclk,
872 .controls = adau1977_snd_controls,
873 .num_controls = ARRAY_SIZE(adau1977_snd_controls),
874 .dapm_widgets = adau1977_dapm_widgets,
875 .num_dapm_widgets = ARRAY_SIZE(adau1977_dapm_widgets),
876 .dapm_routes = adau1977_dapm_routes,
877 .num_dapm_routes = ARRAY_SIZE(adau1977_dapm_routes),
878 .use_pmdown_time = 1,
879 .endianness = 1,
880 .non_legacy_dai_naming = 1,
881 };
882
883 static int adau1977_setup_micbias(struct adau1977 *adau1977)
884 {
885 unsigned int micbias;
886
887 if (device_property_read_u32(adau1977->dev, "adi,micbias", &micbias))
888 micbias = ADAU1977_MICBIAS_8V5;
889
890 if (micbias > ADAU1977_MICBIAS_9V0) {
891 dev_err(adau1977->dev, "Invalid value for 'adi,micbias'\n");
892 return -EINVAL;
893 }
894
895 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
896 ADAU1977_MICBIAS_MB_VOLTS_MASK,
897 micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
898 }
899
900 int adau1977_probe(struct device *dev, struct regmap *regmap,
901 enum adau1977_type type, void (*switch_mode)(struct device *dev))
902 {
903 unsigned int power_off_mask;
904 struct adau1977 *adau1977;
905 int ret;
906
907 if (IS_ERR(regmap))
908 return PTR_ERR(regmap);
909
910 adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
911 if (adau1977 == NULL)
912 return -ENOMEM;
913
914 adau1977->dev = dev;
915 adau1977->type = type;
916 adau1977->regmap = regmap;
917 adau1977->switch_mode = switch_mode;
918 adau1977->max_master_fs = 192000;
919
920 adau1977->constraints.list = adau1977_rates;
921 adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
922
923 adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
924 if (IS_ERR(adau1977->avdd_reg))
925 return PTR_ERR(adau1977->avdd_reg);
926
927 adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
928 if (IS_ERR(adau1977->dvdd_reg)) {
929 if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
930 return PTR_ERR(adau1977->dvdd_reg);
931 adau1977->dvdd_reg = NULL;
932 }
933
934 adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
935 GPIOD_OUT_LOW);
936 if (IS_ERR(adau1977->reset_gpio))
937 return PTR_ERR(adau1977->reset_gpio);
938
939 dev_set_drvdata(dev, adau1977);
940
941 if (adau1977->reset_gpio)
942 ndelay(100);
943
944 ret = adau1977_power_enable(adau1977);
945 if (ret)
946 return ret;
947
948 if (type == ADAU1977) {
949 ret = adau1977_setup_micbias(adau1977);
950 if (ret)
951 goto err_poweroff;
952 }
953
954 if (adau1977->dvdd_reg)
955 power_off_mask = ~0;
956 else
957 power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
958
959 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
960 power_off_mask, 0x00);
961 if (ret)
962 goto err_poweroff;
963
964 ret = adau1977_power_disable(adau1977);
965 if (ret)
966 return ret;
967
968 return devm_snd_soc_register_component(dev, &adau1977_component_driver,
969 &adau1977_dai, 1);
970
971 err_poweroff:
972 adau1977_power_disable(adau1977);
973 return ret;
974
975 }
976 EXPORT_SYMBOL_GPL(adau1977_probe);
977
978 static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
979 {
980 switch (reg) {
981 case ADAU1977_REG_STATUS(0):
982 case ADAU1977_REG_STATUS(1):
983 case ADAU1977_REG_STATUS(2):
984 case ADAU1977_REG_STATUS(3):
985 case ADAU1977_REG_ADC_CLIP:
986 return true;
987 }
988
989 return false;
990 }
991
992 const struct regmap_config adau1977_regmap_config = {
993 .max_register = ADAU1977_REG_DC_HPF_CAL,
994 .volatile_reg = adau1977_register_volatile,
995
996 .cache_type = REGCACHE_RBTREE,
997 .reg_defaults = adau1977_reg_defaults,
998 .num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
999 };
1000 EXPORT_SYMBOL_GPL(adau1977_regmap_config);
1001
1002 MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
1003 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1004 MODULE_LICENSE("GPL");
Linux with added FPC-III support