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WIP FPC-III support
[linux/fpc-iii.git] / sound / soc / codecs / max98090.c
blob06276ff5f8a3cc115c908d332d5dd434277b8bf4
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
4 *
5 * Copyright 2011-2012 Maxim Integrated Products
6 */
7
8 #include <linux/delay.h>
9 #include <linux/i2c.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/pm.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/acpi.h>
17 #include <linux/clk.h>
18 #include <sound/jack.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23 #include <sound/max98090.h>
24 #include "max98090.h"
25
26 /* Allows for sparsely populated register maps */
27 static const struct reg_default max98090_reg[] = {
28 { 0x00, 0x00 }, /* 00 Software Reset */
29 { 0x03, 0x04 }, /* 03 Interrupt Masks */
30 { 0x04, 0x00 }, /* 04 System Clock Quick */
31 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
32 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
33 { 0x07, 0x00 }, /* 07 DAC Path Quick */
34 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
35 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
36 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
37 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
38 { 0x0C, 0x00 }, /* 0C Reserved */
39 { 0x0D, 0x00 }, /* 0D Input Config */
40 { 0x0E, 0x1B }, /* 0E Line Input Level */
41 { 0x0F, 0x00 }, /* 0F Line Config */
42
43 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
44 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
45 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
46 { 0x13, 0x00 }, /* 13 Digital Mic Config */
47 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
48 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
49 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
50 { 0x17, 0x03 }, /* 17 Left ADC Level */
51 { 0x18, 0x03 }, /* 18 Right ADC Level */
52 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
53 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
54 { 0x1B, 0x00 }, /* 1B System Clock */
55 { 0x1C, 0x00 }, /* 1C Clock Mode */
56 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
57 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
58 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
59
60 { 0x20, 0x00 }, /* 20 Any Clock 4 */
61 { 0x21, 0x00 }, /* 21 Master Mode */
62 { 0x22, 0x00 }, /* 22 Interface Format */
63 { 0x23, 0x00 }, /* 23 TDM Format 1*/
64 { 0x24, 0x00 }, /* 24 TDM Format 2*/
65 { 0x25, 0x00 }, /* 25 I/O Configuration */
66 { 0x26, 0x80 }, /* 26 Filter Config */
67 { 0x27, 0x00 }, /* 27 DAI Playback Level */
68 { 0x28, 0x00 }, /* 28 EQ Playback Level */
69 { 0x29, 0x00 }, /* 29 Left HP Mixer */
70 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
71 { 0x2B, 0x00 }, /* 2B HP Control */
72 { 0x2C, 0x1A }, /* 2C Left HP Volume */
73 { 0x2D, 0x1A }, /* 2D Right HP Volume */
74 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
75 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
76
77 { 0x30, 0x00 }, /* 30 Spk Control */
78 { 0x31, 0x2C }, /* 31 Left Spk Volume */
79 { 0x32, 0x2C }, /* 32 Right Spk Volume */
80 { 0x33, 0x00 }, /* 33 ALC Timing */
81 { 0x34, 0x00 }, /* 34 ALC Compressor */
82 { 0x35, 0x00 }, /* 35 ALC Expander */
83 { 0x36, 0x00 }, /* 36 ALC Gain */
84 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
85 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
86 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
87 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
88 { 0x3B, 0x00 }, /* 3B Line OutR Control */
89 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
90 { 0x3D, 0x00 }, /* 3D Jack Detect */
91 { 0x3E, 0x00 }, /* 3E Input Enable */
92 { 0x3F, 0x00 }, /* 3F Output Enable */
93
94 { 0x40, 0x00 }, /* 40 Level Control */
95 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
96 { 0x42, 0x00 }, /* 42 Bias Control */
97 { 0x43, 0x00 }, /* 43 DAC Control */
98 { 0x44, 0x06 }, /* 44 ADC Control */
99 { 0x45, 0x00 }, /* 45 Device Shutdown */
100 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
101 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
102 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
103 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
104 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
105 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
106 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
107 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
108 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
109 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
110
111 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
112 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
113 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
114 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
115 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
116 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
117 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
118 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
119 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
120 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
121 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
122 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
123 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
124 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
125 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
126 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
127
128 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
129 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
130 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
131 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
132 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
133 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
134 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
135 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
136 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
137 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
138 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
139 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
140 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
141 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
142 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
143 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
144
145 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
146 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
147 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
148 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
149 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
150 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
151 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
152 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
153 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
154 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
155 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
156 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
157 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
158 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
159 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
160 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
161
162 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
163 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
164 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
165 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
166 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
167 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
168 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
169 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
170 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
171 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
172 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
173 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
174 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
175 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
176 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
177 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
178
179 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
180 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
181 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
182 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
183 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
184 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
185 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
186 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
187 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
188 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
189 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
190 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
191 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
192 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
193 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
194 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
195
196 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
197 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
198 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
199 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
200 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
201 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
202 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
203 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
204 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
205 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
206 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
207 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
208 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
209 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
210 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
211 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
212
213 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
214 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
215 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
216 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
217 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
218 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
219 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
220 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
221 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
222 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
223 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
224 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
225 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
226 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
227 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
228 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
229
230 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
231 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
232 { 0xC2, 0x00 }, /* C2 Sample Rate */
233 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
234 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
235 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
236 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
237 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
238 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
239 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
240 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
241 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
242 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
243 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
244 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
245 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
246
247 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
248 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
249 };
250
251 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
252 {
253 switch (reg) {
254 case M98090_REG_SOFTWARE_RESET:
255 case M98090_REG_DEVICE_STATUS:
256 case M98090_REG_JACK_STATUS:
257 case M98090_REG_REVISION_ID:
258 return true;
259 default:
260 return false;
261 }
262 }
263
264 static bool max98090_readable_register(struct device *dev, unsigned int reg)
265 {
266 switch (reg) {
267 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
268 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
269 case M98090_REG_REVISION_ID:
270 return true;
271 default:
272 return false;
273 }
274 }
275
276 static int max98090_reset(struct max98090_priv *max98090)
277 {
278 int ret;
279
280 /* Reset the codec by writing to this write-only reset register */
281 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
282 M98090_SWRESET_MASK);
283 if (ret < 0) {
284 dev_err(max98090->component->dev,
285 "Failed to reset codec: %d\n", ret);
286 return ret;
287 }
288
289 msleep(20);
290 return ret;
291 }
292
293 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
294 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
295 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
296 );
297
298 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
299
300 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
301 -600, 600, 0);
302
303 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
304 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
305 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
306 );
307
308 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
309 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
310
311 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
312 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
313
314 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
316 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
317 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
318
319 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
320 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
321 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
322 );
323
324 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
325 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
326 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
327 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
328 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
329 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
330 );
331
332 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
333 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
334 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
335 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
336 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
337 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
338 );
339
340 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
341 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
342 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
343 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
344 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
345 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
346 );
347
348 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
349 struct snd_ctl_elem_value *ucontrol)
350 {
351 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
352 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
353 struct soc_mixer_control *mc =
354 (struct soc_mixer_control *)kcontrol->private_value;
355 unsigned int mask = (1 << fls(mc->max)) - 1;
356 unsigned int val = snd_soc_component_read(component, mc->reg);
357 unsigned int *select;
358
359 switch (mc->reg) {
360 case M98090_REG_MIC1_INPUT_LEVEL:
361 select = &(max98090->pa1en);
362 break;
363 case M98090_REG_MIC2_INPUT_LEVEL:
364 select = &(max98090->pa2en);
365 break;
366 case M98090_REG_ADC_SIDETONE:
367 select = &(max98090->sidetone);
368 break;
369 default:
370 return -EINVAL;
371 }
372
373 val = (val >> mc->shift) & mask;
374
375 if (val >= 1) {
376 /* If on, return the volume */
377 val = val - 1;
378 *select = val;
379 } else {
380 /* If off, return last stored value */
381 val = *select;
382 }
383
384 ucontrol->value.integer.value[0] = val;
385 return 0;
386 }
387
388 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
389 struct snd_ctl_elem_value *ucontrol)
390 {
391 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
392 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
393 struct soc_mixer_control *mc =
394 (struct soc_mixer_control *)kcontrol->private_value;
395 unsigned int mask = (1 << fls(mc->max)) - 1;
396 unsigned int sel = ucontrol->value.integer.value[0];
397 unsigned int val = snd_soc_component_read(component, mc->reg);
398 unsigned int *select;
399
400 switch (mc->reg) {
401 case M98090_REG_MIC1_INPUT_LEVEL:
402 select = &(max98090->pa1en);
403 break;
404 case M98090_REG_MIC2_INPUT_LEVEL:
405 select = &(max98090->pa2en);
406 break;
407 case M98090_REG_ADC_SIDETONE:
408 select = &(max98090->sidetone);
409 break;
410 default:
411 return -EINVAL;
412 }
413
414 val = (val >> mc->shift) & mask;
415
416 *select = sel;
417
418 /* Setting a volume is only valid if it is already On */
419 if (val >= 1) {
420 sel = sel + 1;
421 } else {
422 /* Write what was already there */
423 sel = val;
424 }
425
426 snd_soc_component_update_bits(component, mc->reg,
427 mask << mc->shift,
428 sel << mc->shift);
429
430 return 0;
431 }
432
433 static const char *max98090_perf_pwr_text[] =
434 { "High Performance", "Low Power" };
435 static const char *max98090_pwr_perf_text[] =
436 { "Low Power", "High Performance" };
437
438 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
439 M98090_REG_BIAS_CONTROL,
440 M98090_VCM_MODE_SHIFT,
441 max98090_pwr_perf_text);
442
443 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
444
445 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
446 M98090_REG_ADC_CONTROL,
447 M98090_OSR128_SHIFT,
448 max98090_osr128_text);
449
450 static const char *max98090_mode_text[] = { "Voice", "Music" };
451
452 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
453 M98090_REG_FILTER_CONFIG,
454 M98090_MODE_SHIFT,
455 max98090_mode_text);
456
457 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
458 M98090_REG_FILTER_CONFIG,
459 M98090_FLT_DMIC34MODE_SHIFT,
460 max98090_mode_text);
461
462 static const char *max98090_drcatk_text[] =
463 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
464
465 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
466 M98090_REG_DRC_TIMING,
467 M98090_DRCATK_SHIFT,
468 max98090_drcatk_text);
469
470 static const char *max98090_drcrls_text[] =
471 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
472
473 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
474 M98090_REG_DRC_TIMING,
475 M98090_DRCRLS_SHIFT,
476 max98090_drcrls_text);
477
478 static const char *max98090_alccmp_text[] =
479 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
480
481 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
482 M98090_REG_DRC_COMPRESSOR,
483 M98090_DRCCMP_SHIFT,
484 max98090_alccmp_text);
485
486 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
487
488 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
489 M98090_REG_DRC_EXPANDER,
490 M98090_DRCEXP_SHIFT,
491 max98090_drcexp_text);
492
493 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
494 M98090_REG_DAC_CONTROL,
495 M98090_PERFMODE_SHIFT,
496 max98090_perf_pwr_text);
497
498 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
499 M98090_REG_DAC_CONTROL,
500 M98090_DACHP_SHIFT,
501 max98090_pwr_perf_text);
502
503 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
504 M98090_REG_ADC_CONTROL,
505 M98090_ADCHP_SHIFT,
506 max98090_pwr_perf_text);
507
508 static const struct snd_kcontrol_new max98090_snd_controls[] = {
509 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
510
511 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
512 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
513
514 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
515 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
516 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
517 max98090_put_enab_tlv, max98090_micboost_tlv),
518
519 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
520 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
521 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
522 max98090_put_enab_tlv, max98090_micboost_tlv),
523
524 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
525 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
526 max98090_mic_tlv),
527
528 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
529 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
530 max98090_mic_tlv),
531
532 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
533 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
534 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
535
536 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
537 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
538 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
539
540 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
541 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
542 max98090_line_tlv),
543
544 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
545 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
546 max98090_line_tlv),
547
548 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
549 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
550 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
551 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
552
553 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
554 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
555 max98090_avg_tlv),
556 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
557 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
558 max98090_avg_tlv),
559
560 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
561 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
562 max98090_av_tlv),
563 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
564 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
565 max98090_av_tlv),
566
567 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
568 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
569 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
570 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
571
572 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
573 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
574 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
575 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
576 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
577 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
578 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
579 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
580 SOC_ENUM("Filter Mode", max98090_mode_enum),
581 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
582 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
583 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
584 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
585 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
586 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
587 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
588 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
589 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
590 max98090_put_enab_tlv, max98090_sdg_tlv),
591 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
592 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
593 max98090_dvg_tlv),
594 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
595 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
596 max98090_dv_tlv),
597 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
598 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
599 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
600 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
601 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
602 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
603 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
604 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
605 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
606 1),
607 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
608 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
609 max98090_dv_tlv),
610
611 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
612 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
613 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
614 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
615 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
616 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
617 max98090_alcmakeup_tlv),
618 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
619 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
620 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
621 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
622 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
623 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
624 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
625 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
626
627 SOC_ENUM("DAC HP Playback Performance Mode",
628 max98090_dac_perfmode_enum),
629 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
630
631 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
632 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
633 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
634 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
635 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
636 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
637
638 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
639 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
640 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
641 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
642 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
643 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
644
645 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
646 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
647 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
648 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
649 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
650 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
651
652 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
653 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
654 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
655
656 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
657 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
658 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
659 0, max98090_spk_tlv),
660
661 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
662 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
663 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
664
665 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
666 M98090_HPLM_SHIFT, 1, 1),
667 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
668 M98090_HPRM_SHIFT, 1, 1),
669
670 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
671 M98090_SPLM_SHIFT, 1, 1),
672 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
673 M98090_SPRM_SHIFT, 1, 1),
674
675 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
676 M98090_RCVLM_SHIFT, 1, 1),
677 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
678 M98090_RCVRM_SHIFT, 1, 1),
679
680 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
681 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
682 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
683 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
684 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
685 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
686
687 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
688 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
689 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
690 };
691
692 static const struct snd_kcontrol_new max98091_snd_controls[] = {
693
694 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
695 M98090_DMIC34_ZEROPAD_SHIFT,
696 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
697
698 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
699 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
700 M98090_FLT_DMIC34HPF_SHIFT,
701 M98090_FLT_DMIC34HPF_NUM - 1, 0),
702
703 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
704 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
705 max98090_avg_tlv),
706 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
707 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
708 max98090_avg_tlv),
709
710 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
711 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
712 max98090_av_tlv),
713 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
714 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
715 max98090_av_tlv),
716
717 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
718 M98090_REG_DMIC34_BIQUAD_BASE, 15),
719 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
720 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
721
722 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
723 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
724 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
725 };
726
727 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
728 struct snd_kcontrol *kcontrol, int event)
729 {
730 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
731 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
732
733 unsigned int val = snd_soc_component_read(component, w->reg);
734
735 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
736 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
737 else
738 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
739
740 if (val >= 1) {
741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
742 max98090->pa1en = val - 1; /* Update for volatile */
743 } else {
744 max98090->pa2en = val - 1; /* Update for volatile */
745 }
746 }
747
748 switch (event) {
749 case SND_SOC_DAPM_POST_PMU:
750 /* If turning on, set to most recently selected volume */
751 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
752 val = max98090->pa1en + 1;
753 else
754 val = max98090->pa2en + 1;
755 break;
756 case SND_SOC_DAPM_POST_PMD:
757 /* If turning off, turn off */
758 val = 0;
759 break;
760 default:
761 return -EINVAL;
762 }
763
764 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
765 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
766 val << M98090_MIC_PA1EN_SHIFT);
767 else
768 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
769 val << M98090_MIC_PA2EN_SHIFT);
770
771 return 0;
772 }
773
774 static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
775 struct snd_kcontrol *kcontrol, int event)
776 {
777 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
778 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
779
780 if (event & SND_SOC_DAPM_POST_PMU)
781 max98090->shdn_pending = true;
782
783 return 0;
784
785 }
786
787 static const char *mic1_mux_text[] = { "IN12", "IN56" };
788
789 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
790 M98090_REG_INPUT_MODE,
791 M98090_EXTMIC1_SHIFT,
792 mic1_mux_text);
793
794 static const struct snd_kcontrol_new max98090_mic1_mux =
795 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
796
797 static const char *mic2_mux_text[] = { "IN34", "IN56" };
798
799 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
800 M98090_REG_INPUT_MODE,
801 M98090_EXTMIC2_SHIFT,
802 mic2_mux_text);
803
804 static const struct snd_kcontrol_new max98090_mic2_mux =
805 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
806
807 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
808
809 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
810
811 static const struct snd_kcontrol_new max98090_dmic_mux =
812 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
813
814 /* LINEA mixer switch */
815 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
816 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
817 M98090_IN1SEEN_SHIFT, 1, 0),
818 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
819 M98090_IN3SEEN_SHIFT, 1, 0),
820 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
821 M98090_IN5SEEN_SHIFT, 1, 0),
822 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
823 M98090_IN34DIFF_SHIFT, 1, 0),
824 };
825
826 /* LINEB mixer switch */
827 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
828 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
829 M98090_IN2SEEN_SHIFT, 1, 0),
830 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
831 M98090_IN4SEEN_SHIFT, 1, 0),
832 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
833 M98090_IN6SEEN_SHIFT, 1, 0),
834 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
835 M98090_IN56DIFF_SHIFT, 1, 0),
836 };
837
838 /* Left ADC mixer switch */
839 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
840 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
841 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
842 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
843 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
844 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
845 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
846 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
847 M98090_MIXADL_LINEA_SHIFT, 1, 0),
848 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
849 M98090_MIXADL_LINEB_SHIFT, 1, 0),
850 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
851 M98090_MIXADL_MIC1_SHIFT, 1, 0),
852 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
853 M98090_MIXADL_MIC2_SHIFT, 1, 0),
854 };
855
856 /* Right ADC mixer switch */
857 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
858 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
859 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
860 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
861 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
862 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
863 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
864 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
865 M98090_MIXADR_LINEA_SHIFT, 1, 0),
866 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
867 M98090_MIXADR_LINEB_SHIFT, 1, 0),
868 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
869 M98090_MIXADR_MIC1_SHIFT, 1, 0),
870 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
871 M98090_MIXADR_MIC2_SHIFT, 1, 0),
872 };
873
874 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
875
876 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
877 M98090_REG_IO_CONFIGURATION,
878 M98090_LTEN_SHIFT,
879 lten_mux_text);
880
881 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
882 M98090_REG_IO_CONFIGURATION,
883 M98090_LTEN_SHIFT,
884 lten_mux_text);
885
886 static const struct snd_kcontrol_new max98090_ltenl_mux =
887 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
888
889 static const struct snd_kcontrol_new max98090_ltenr_mux =
890 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
891
892 static const char *lben_mux_text[] = { "Normal", "Loopback" };
893
894 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
895 M98090_REG_IO_CONFIGURATION,
896 M98090_LBEN_SHIFT,
897 lben_mux_text);
898
899 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
900 M98090_REG_IO_CONFIGURATION,
901 M98090_LBEN_SHIFT,
902 lben_mux_text);
903
904 static const struct snd_kcontrol_new max98090_lbenl_mux =
905 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
906
907 static const struct snd_kcontrol_new max98090_lbenr_mux =
908 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
909
910 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
911
912 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
913
914 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
915 M98090_REG_ADC_SIDETONE,
916 M98090_DSTSL_SHIFT,
917 stenl_mux_text);
918
919 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
920 M98090_REG_ADC_SIDETONE,
921 M98090_DSTSR_SHIFT,
922 stenr_mux_text);
923
924 static const struct snd_kcontrol_new max98090_stenl_mux =
925 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
926
927 static const struct snd_kcontrol_new max98090_stenr_mux =
928 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
929
930 /* Left speaker mixer switch */
931 static const struct
932 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
933 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
934 M98090_MIXSPL_DACL_SHIFT, 1, 0),
935 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
936 M98090_MIXSPL_DACR_SHIFT, 1, 0),
937 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
938 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
939 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
940 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
941 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
942 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
943 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
944 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
945 };
946
947 /* Right speaker mixer switch */
948 static const struct
949 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
950 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
951 M98090_MIXSPR_DACL_SHIFT, 1, 0),
952 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
953 M98090_MIXSPR_DACR_SHIFT, 1, 0),
954 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
955 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
956 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
957 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
958 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
959 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
960 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
961 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
962 };
963
964 /* Left headphone mixer switch */
965 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
966 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
967 M98090_MIXHPL_DACL_SHIFT, 1, 0),
968 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
969 M98090_MIXHPL_DACR_SHIFT, 1, 0),
970 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
971 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
972 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
973 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
974 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
975 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
976 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
977 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
978 };
979
980 /* Right headphone mixer switch */
981 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
982 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
983 M98090_MIXHPR_DACL_SHIFT, 1, 0),
984 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
985 M98090_MIXHPR_DACR_SHIFT, 1, 0),
986 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
987 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
988 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
989 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
990 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
991 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
992 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
993 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
994 };
995
996 /* Left receiver mixer switch */
997 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
998 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
999 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1000 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1001 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1002 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1003 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1004 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1005 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1006 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1007 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1008 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1009 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1010 };
1011
1012 /* Right receiver mixer switch */
1013 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1014 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1015 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1016 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1017 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1018 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1019 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1020 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1021 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1022 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1023 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1024 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1025 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1026 };
1027
1028 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1029
1030 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1031 M98090_REG_LOUTR_MIXER,
1032 M98090_LINMOD_SHIFT,
1033 linmod_mux_text);
1034
1035 static const struct snd_kcontrol_new max98090_linmod_mux =
1036 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1037
1038 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1039
1040 /*
1041 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1042 */
1043 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1044 M98090_REG_HP_CONTROL,
1045 M98090_MIXHPLSEL_SHIFT,
1046 mixhpsel_mux_text);
1047
1048 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1049 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1050
1051 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1052 M98090_REG_HP_CONTROL,
1053 M98090_MIXHPRSEL_SHIFT,
1054 mixhpsel_mux_text);
1055
1056 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1057 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1058
1059 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1060 SND_SOC_DAPM_INPUT("MIC1"),
1061 SND_SOC_DAPM_INPUT("MIC2"),
1062 SND_SOC_DAPM_INPUT("DMICL"),
1063 SND_SOC_DAPM_INPUT("DMICR"),
1064 SND_SOC_DAPM_INPUT("IN1"),
1065 SND_SOC_DAPM_INPUT("IN2"),
1066 SND_SOC_DAPM_INPUT("IN3"),
1067 SND_SOC_DAPM_INPUT("IN4"),
1068 SND_SOC_DAPM_INPUT("IN5"),
1069 SND_SOC_DAPM_INPUT("IN6"),
1070 SND_SOC_DAPM_INPUT("IN12"),
1071 SND_SOC_DAPM_INPUT("IN34"),
1072 SND_SOC_DAPM_INPUT("IN56"),
1073
1074 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1075 M98090_MBEN_SHIFT, 0, NULL, 0),
1076 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1077 M98090_SHDNN_SHIFT, 0, NULL, 0),
1078 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1079 M98090_SDIEN_SHIFT, 0, NULL, 0),
1080 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1081 M98090_SDOEN_SHIFT, 0, NULL, 0),
1082 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1083 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
1084 SND_SOC_DAPM_POST_PMU),
1085 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1086 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
1087 SND_SOC_DAPM_POST_PMU),
1088 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1089 M98090_AHPF_SHIFT, 0, NULL, 0),
1090
1091 /*
1092 * Note: Sysclk and misc power supplies are taken care of by SHDN
1093 */
1094
1095 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1096 0, 0, &max98090_mic1_mux),
1097
1098 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1099 0, 0, &max98090_mic2_mux),
1100
1101 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1102
1103 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1104 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1105 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1106
1107 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1108 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1109 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1110
1111 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1112 &max98090_linea_mixer_controls[0],
1113 ARRAY_SIZE(max98090_linea_mixer_controls)),
1114
1115 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1116 &max98090_lineb_mixer_controls[0],
1117 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1118
1119 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1120 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1121 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1122 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1123
1124 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1125 &max98090_left_adc_mixer_controls[0],
1126 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1127
1128 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1129 &max98090_right_adc_mixer_controls[0],
1130 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1131
1132 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1133 M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
1134 SND_SOC_DAPM_POST_PMU),
1135 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1136 M98090_ADREN_SHIFT, 0, max98090_shdn_event,
1137 SND_SOC_DAPM_POST_PMU),
1138
1139 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1140 SND_SOC_NOPM, 0, 0),
1141 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1142 SND_SOC_NOPM, 0, 0),
1143
1144 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1145 0, 0, &max98090_lbenl_mux),
1146
1147 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1148 0, 0, &max98090_lbenr_mux),
1149
1150 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1151 0, 0, &max98090_ltenl_mux),
1152
1153 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1154 0, 0, &max98090_ltenr_mux),
1155
1156 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1157 0, 0, &max98090_stenl_mux),
1158
1159 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1160 0, 0, &max98090_stenr_mux),
1161
1162 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1163 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1164
1165 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1166 M98090_DALEN_SHIFT, 0),
1167 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1168 M98090_DAREN_SHIFT, 0),
1169
1170 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1171 &max98090_left_hp_mixer_controls[0],
1172 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1173
1174 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1175 &max98090_right_hp_mixer_controls[0],
1176 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1177
1178 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1179 &max98090_left_speaker_mixer_controls[0],
1180 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1181
1182 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1183 &max98090_right_speaker_mixer_controls[0],
1184 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1185
1186 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1187 &max98090_left_rcv_mixer_controls[0],
1188 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1189
1190 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1191 &max98090_right_rcv_mixer_controls[0],
1192 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1193
1194 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0,
1195 &max98090_linmod_mux),
1196
1197 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
1198 &max98090_mixhplsel_mux),
1199
1200 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
1201 &max98090_mixhprsel_mux),
1202
1203 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1204 M98090_HPLEN_SHIFT, 0, NULL, 0),
1205 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1206 M98090_HPREN_SHIFT, 0, NULL, 0),
1207
1208 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1209 M98090_SPLEN_SHIFT, 0, NULL, 0),
1210 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1211 M98090_SPREN_SHIFT, 0, NULL, 0),
1212
1213 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1214 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1215 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1216 M98090_RCVREN_SHIFT, 0, NULL, 0),
1217
1218 SND_SOC_DAPM_OUTPUT("HPL"),
1219 SND_SOC_DAPM_OUTPUT("HPR"),
1220 SND_SOC_DAPM_OUTPUT("SPKL"),
1221 SND_SOC_DAPM_OUTPUT("SPKR"),
1222 SND_SOC_DAPM_OUTPUT("RCVL"),
1223 SND_SOC_DAPM_OUTPUT("RCVR"),
1224 };
1225
1226 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1227 SND_SOC_DAPM_INPUT("DMIC3"),
1228 SND_SOC_DAPM_INPUT("DMIC4"),
1229
1230 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1231 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1232 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1233 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1234 };
1235
1236 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1237 {"MIC1 Input", NULL, "MIC1"},
1238 {"MIC2 Input", NULL, "MIC2"},
1239
1240 {"DMICL", NULL, "DMICL_ENA"},
1241 {"DMICL", NULL, "DMICR_ENA"},
1242 {"DMICR", NULL, "DMICL_ENA"},
1243 {"DMICR", NULL, "DMICR_ENA"},
1244 {"DMICL", NULL, "AHPF"},
1245 {"DMICR", NULL, "AHPF"},
1246
1247 /* MIC1 input mux */
1248 {"MIC1 Mux", "IN12", "IN12"},
1249 {"MIC1 Mux", "IN56", "IN56"},
1250
1251 /* MIC2 input mux */
1252 {"MIC2 Mux", "IN34", "IN34"},
1253 {"MIC2 Mux", "IN56", "IN56"},
1254
1255 {"MIC1 Input", NULL, "MIC1 Mux"},
1256 {"MIC2 Input", NULL, "MIC2 Mux"},
1257
1258 /* Left ADC input mixer */
1259 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1260 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1261 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1262 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1263 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1264 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1265 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1266
1267 /* Right ADC input mixer */
1268 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1269 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1270 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1271 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1272 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1273 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1274 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1275
1276 /* Line A input mixer */
1277 {"LINEA Mixer", "IN1 Switch", "IN1"},
1278 {"LINEA Mixer", "IN3 Switch", "IN3"},
1279 {"LINEA Mixer", "IN5 Switch", "IN5"},
1280 {"LINEA Mixer", "IN34 Switch", "IN34"},
1281
1282 /* Line B input mixer */
1283 {"LINEB Mixer", "IN2 Switch", "IN2"},
1284 {"LINEB Mixer", "IN4 Switch", "IN4"},
1285 {"LINEB Mixer", "IN6 Switch", "IN6"},
1286 {"LINEB Mixer", "IN56 Switch", "IN56"},
1287
1288 {"LINEA Input", NULL, "LINEA Mixer"},
1289 {"LINEB Input", NULL, "LINEB Mixer"},
1290
1291 /* Inputs */
1292 {"ADCL", NULL, "Left ADC Mixer"},
1293 {"ADCR", NULL, "Right ADC Mixer"},
1294 {"ADCL", NULL, "SHDN"},
1295 {"ADCR", NULL, "SHDN"},
1296
1297 {"DMIC Mux", "ADC", "ADCL"},
1298 {"DMIC Mux", "ADC", "ADCR"},
1299 {"DMIC Mux", "DMIC", "DMICL"},
1300 {"DMIC Mux", "DMIC", "DMICR"},
1301
1302 {"LBENL Mux", "Normal", "DMIC Mux"},
1303 {"LBENL Mux", "Loopback", "LTENL Mux"},
1304 {"LBENR Mux", "Normal", "DMIC Mux"},
1305 {"LBENR Mux", "Loopback", "LTENR Mux"},
1306
1307 {"AIFOUTL", NULL, "LBENL Mux"},
1308 {"AIFOUTR", NULL, "LBENR Mux"},
1309 {"AIFOUTL", NULL, "SHDN"},
1310 {"AIFOUTR", NULL, "SHDN"},
1311 {"AIFOUTL", NULL, "SDOEN"},
1312 {"AIFOUTR", NULL, "SDOEN"},
1313
1314 {"LTENL Mux", "Normal", "AIFINL"},
1315 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1316 {"LTENR Mux", "Normal", "AIFINR"},
1317 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1318
1319 {"DACL", NULL, "LTENL Mux"},
1320 {"DACR", NULL, "LTENR Mux"},
1321
1322 {"STENL Mux", "Sidetone Left", "ADCL"},
1323 {"STENL Mux", "Sidetone Left", "DMICL"},
1324 {"STENR Mux", "Sidetone Right", "ADCR"},
1325 {"STENR Mux", "Sidetone Right", "DMICR"},
1326 {"DACL", NULL, "STENL Mux"},
1327 {"DACR", NULL, "STENR Mux"},
1328
1329 {"AIFINL", NULL, "SHDN"},
1330 {"AIFINR", NULL, "SHDN"},
1331 {"AIFINL", NULL, "SDIEN"},
1332 {"AIFINR", NULL, "SDIEN"},
1333 {"DACL", NULL, "SHDN"},
1334 {"DACR", NULL, "SHDN"},
1335
1336 /* Left headphone output mixer */
1337 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1338 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1339 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1340 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1341 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1342 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1343
1344 /* Right headphone output mixer */
1345 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1346 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1347 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1348 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1349 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1350 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1351
1352 /* Left speaker output mixer */
1353 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1354 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1355 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1356 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1357 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1358 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1359
1360 /* Right speaker output mixer */
1361 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1362 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1363 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1364 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1365 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1366 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1367
1368 /* Left Receiver output mixer */
1369 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1370 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1371 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1372 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1373 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1374 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1375
1376 /* Right Receiver output mixer */
1377 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1378 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1379 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1380 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1381 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1382 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1383
1384 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1385
1386 /*
1387 * Disable this for lowest power if bypassing
1388 * the DAC with an analog signal
1389 */
1390 {"HP Left Out", NULL, "DACL"},
1391 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1392
1393 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1394
1395 /*
1396 * Disable this for lowest power if bypassing
1397 * the DAC with an analog signal
1398 */
1399 {"HP Right Out", NULL, "DACR"},
1400 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1401
1402 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1403 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1404 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1405
1406 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1407 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1408 {"RCV Right Out", NULL, "LINMOD Mux"},
1409
1410 {"HPL", NULL, "HP Left Out"},
1411 {"HPR", NULL, "HP Right Out"},
1412 {"SPKL", NULL, "SPK Left Out"},
1413 {"SPKR", NULL, "SPK Right Out"},
1414 {"RCVL", NULL, "RCV Left Out"},
1415 {"RCVR", NULL, "RCV Right Out"},
1416 };
1417
1418 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1419 /* DMIC inputs */
1420 {"DMIC3", NULL, "DMIC3_ENA"},
1421 {"DMIC4", NULL, "DMIC4_ENA"},
1422 {"DMIC3", NULL, "AHPF"},
1423 {"DMIC4", NULL, "AHPF"},
1424 };
1425
1426 static int max98090_add_widgets(struct snd_soc_component *component)
1427 {
1428 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1429 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1430
1431 snd_soc_add_component_controls(component, max98090_snd_controls,
1432 ARRAY_SIZE(max98090_snd_controls));
1433
1434 if (max98090->devtype == MAX98091) {
1435 snd_soc_add_component_controls(component, max98091_snd_controls,
1436 ARRAY_SIZE(max98091_snd_controls));
1437 }
1438
1439 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1440 ARRAY_SIZE(max98090_dapm_widgets));
1441
1442 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1443 ARRAY_SIZE(max98090_dapm_routes));
1444
1445 if (max98090->devtype == MAX98091) {
1446 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1447 ARRAY_SIZE(max98091_dapm_widgets));
1448
1449 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1450 ARRAY_SIZE(max98091_dapm_routes));
1451 }
1452
1453 return 0;
1454 }
1455
1456 static const int pclk_rates[] = {
1457 12000000, 12000000, 13000000, 13000000,
1458 16000000, 16000000, 19200000, 19200000
1459 };
1460
1461 static const int lrclk_rates[] = {
1462 8000, 16000, 8000, 16000,
1463 8000, 16000, 8000, 16000
1464 };
1465
1466 static const int user_pclk_rates[] = {
1467 13000000, 13000000, 19200000, 19200000,
1468 };
1469
1470 static const int user_lrclk_rates[] = {
1471 44100, 48000, 44100, 48000,
1472 };
1473
1474 static const unsigned long long ni_value[] = {
1475 3528, 768, 441, 8
1476 };
1477
1478 static const unsigned long long mi_value[] = {
1479 8125, 1625, 1500, 25
1480 };
1481
1482 static void max98090_configure_bclk(struct snd_soc_component *component)
1483 {
1484 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1485 unsigned long long ni;
1486 int i;
1487
1488 if (!max98090->sysclk) {
1489 dev_err(component->dev, "No SYSCLK configured\n");
1490 return;
1491 }
1492
1493 if (!max98090->bclk || !max98090->lrclk) {
1494 dev_err(component->dev, "No audio clocks configured\n");
1495 return;
1496 }
1497
1498 /* Skip configuration when operating as slave */
1499 if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) &
1500 M98090_MAS_MASK)) {
1501 return;
1502 }
1503
1504 /* Check for supported PCLK to LRCLK ratios */
1505 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1506 if ((pclk_rates[i] == max98090->sysclk) &&
1507 (lrclk_rates[i] == max98090->lrclk)) {
1508 dev_dbg(component->dev,
1509 "Found supported PCLK to LRCLK rates 0x%x\n",
1510 i + 0x8);
1511
1512 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1513 M98090_FREQ_MASK,
1514 (i + 0x8) << M98090_FREQ_SHIFT);
1515 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1516 M98090_USE_M1_MASK, 0);
1517 return;
1518 }
1519 }
1520
1521 /* Check for user calculated MI and NI ratios */
1522 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1523 if ((user_pclk_rates[i] == max98090->sysclk) &&
1524 (user_lrclk_rates[i] == max98090->lrclk)) {
1525 dev_dbg(component->dev,
1526 "Found user supported PCLK to LRCLK rates\n");
1527 dev_dbg(component->dev, "i %d ni %lld mi %lld\n",
1528 i, ni_value[i], mi_value[i]);
1529
1530 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1531 M98090_FREQ_MASK, 0);
1532 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1533 M98090_USE_M1_MASK,
1534 1 << M98090_USE_M1_SHIFT);
1535
1536 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1537 (ni_value[i] >> 8) & 0x7F);
1538 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB,
1539 ni_value[i] & 0xFF);
1540 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB,
1541 (mi_value[i] >> 8) & 0x7F);
1542 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB,
1543 mi_value[i] & 0xFF);
1544
1545 return;
1546 }
1547 }
1548
1549 /*
1550 * Calculate based on MI = 65536 (not as good as either method above)
1551 */
1552 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1553 M98090_FREQ_MASK, 0);
1554 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1555 M98090_USE_M1_MASK, 0);
1556
1557 /*
1558 * Configure NI when operating as master
1559 * Note: There is a small, but significant audio quality improvement
1560 * by calculating ni and mi.
1561 */
1562 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1563 * (unsigned long long int)max98090->lrclk;
1564 do_div(ni, (unsigned long long int)max98090->sysclk);
1565 dev_info(component->dev, "No better method found\n");
1566 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni);
1567 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1568 (ni >> 8) & 0x7F);
1569 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1570 }
1571
1572 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1573 unsigned int fmt)
1574 {
1575 struct snd_soc_component *component = codec_dai->component;
1576 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1577 struct max98090_cdata *cdata;
1578 u8 regval;
1579
1580 max98090->dai_fmt = fmt;
1581 cdata = &max98090->dai[0];
1582
1583 if (fmt != cdata->fmt) {
1584 cdata->fmt = fmt;
1585
1586 regval = 0;
1587 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1588 case SND_SOC_DAIFMT_CBS_CFS:
1589 /* Set to slave mode PLL - MAS mode off */
1590 snd_soc_component_write(component,
1591 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1592 snd_soc_component_write(component,
1593 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1594 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1595 M98090_USE_M1_MASK, 0);
1596 max98090->master = false;
1597 break;
1598 case SND_SOC_DAIFMT_CBM_CFM:
1599 /* Set to master mode */
1600 if (max98090->tdm_slots == 4) {
1601 /* TDM */
1602 regval |= M98090_MAS_MASK |
1603 M98090_BSEL_64;
1604 } else if (max98090->tdm_slots == 3) {
1605 /* TDM */
1606 regval |= M98090_MAS_MASK |
1607 M98090_BSEL_48;
1608 } else {
1609 /* Few TDM slots, or No TDM */
1610 regval |= M98090_MAS_MASK |
1611 M98090_BSEL_32;
1612 }
1613 max98090->master = true;
1614 break;
1615 case SND_SOC_DAIFMT_CBS_CFM:
1616 case SND_SOC_DAIFMT_CBM_CFS:
1617 default:
1618 dev_err(component->dev, "DAI clock mode unsupported");
1619 return -EINVAL;
1620 }
1621 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
1622
1623 regval = 0;
1624 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1625 case SND_SOC_DAIFMT_I2S:
1626 regval |= M98090_DLY_MASK;
1627 break;
1628 case SND_SOC_DAIFMT_LEFT_J:
1629 break;
1630 case SND_SOC_DAIFMT_RIGHT_J:
1631 regval |= M98090_RJ_MASK;
1632 break;
1633 case SND_SOC_DAIFMT_DSP_A:
1634 /* Not supported mode */
1635 default:
1636 dev_err(component->dev, "DAI format unsupported");
1637 return -EINVAL;
1638 }
1639
1640 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1641 case SND_SOC_DAIFMT_NB_NF:
1642 break;
1643 case SND_SOC_DAIFMT_NB_IF:
1644 regval |= M98090_WCI_MASK;
1645 break;
1646 case SND_SOC_DAIFMT_IB_NF:
1647 regval |= M98090_BCI_MASK;
1648 break;
1649 case SND_SOC_DAIFMT_IB_IF:
1650 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1651 break;
1652 default:
1653 dev_err(component->dev, "DAI invert mode unsupported");
1654 return -EINVAL;
1655 }
1656
1657 /*
1658 * This accommodates an inverted logic in the MAX98090 chip
1659 * for Bit Clock Invert (BCI). The inverted logic is only
1660 * seen for the case of TDM mode. The remaining cases have
1661 * normal logic.
1662 */
1663 if (max98090->tdm_slots > 1)
1664 regval ^= M98090_BCI_MASK;
1665
1666 snd_soc_component_write(component,
1667 M98090_REG_INTERFACE_FORMAT, regval);
1668 }
1669
1670 return 0;
1671 }
1672
1673 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1674 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1675 {
1676 struct snd_soc_component *component = codec_dai->component;
1677 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1678 struct max98090_cdata *cdata;
1679 cdata = &max98090->dai[0];
1680
1681 if (slots < 0 || slots > 4)
1682 return -EINVAL;
1683
1684 max98090->tdm_slots = slots;
1685 max98090->tdm_width = slot_width;
1686
1687 if (max98090->tdm_slots > 1) {
1688 /* SLOTL SLOTR SLOTDLY */
1689 snd_soc_component_write(component, M98090_REG_TDM_FORMAT,
1690 0 << M98090_TDM_SLOTL_SHIFT |
1691 1 << M98090_TDM_SLOTR_SHIFT |
1692 0 << M98090_TDM_SLOTDLY_SHIFT);
1693
1694 /* FSW TDM */
1695 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL,
1696 M98090_TDM_MASK,
1697 M98090_TDM_MASK);
1698 }
1699
1700 /*
1701 * Normally advisable to set TDM first, but this permits either order
1702 */
1703 cdata->fmt = 0;
1704 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1705
1706 return 0;
1707 }
1708
1709 static int max98090_set_bias_level(struct snd_soc_component *component,
1710 enum snd_soc_bias_level level)
1711 {
1712 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1713 int ret;
1714
1715 switch (level) {
1716 case SND_SOC_BIAS_ON:
1717 break;
1718
1719 case SND_SOC_BIAS_PREPARE:
1720 /*
1721 * SND_SOC_BIAS_PREPARE is called while preparing for a
1722 * transition to ON or away from ON. If current bias_level
1723 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1724 * away from ON. Disable the clock in that case, otherwise
1725 * enable it.
1726 */
1727 if (IS_ERR(max98090->mclk))
1728 break;
1729
1730 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1731 clk_disable_unprepare(max98090->mclk);
1732 } else {
1733 ret = clk_prepare_enable(max98090->mclk);
1734 if (ret)
1735 return ret;
1736 }
1737 break;
1738
1739 case SND_SOC_BIAS_STANDBY:
1740 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1741 ret = regcache_sync(max98090->regmap);
1742 if (ret != 0) {
1743 dev_err(component->dev,
1744 "Failed to sync cache: %d\n", ret);
1745 return ret;
1746 }
1747 }
1748 break;
1749
1750 case SND_SOC_BIAS_OFF:
1751 /* Set internal pull-up to lowest power mode */
1752 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
1753 M98090_JDWK_MASK, M98090_JDWK_MASK);
1754 regcache_mark_dirty(max98090->regmap);
1755 break;
1756 }
1757 return 0;
1758 }
1759
1760 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1761
1762 static const int comp_lrclk_rates[] = {
1763 8000, 16000, 32000, 44100, 48000, 96000
1764 };
1765
1766 struct dmic_table {
1767 int pclk;
1768 struct {
1769 int freq;
1770 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1771 } settings[6]; /* One for each dmic divisor. */
1772 };
1773
1774 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1775 {
1776 .pclk = 11289600,
1777 .settings = {
1778 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1779 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1780 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1781 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1782 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1783 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1784 },
1785 },
1786 {
1787 .pclk = 12000000,
1788 .settings = {
1789 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1790 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1791 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1792 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1793 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1794 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1795 }
1796 },
1797 {
1798 .pclk = 12288000,
1799 .settings = {
1800 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1801 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1802 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1803 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1804 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1805 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1806 }
1807 },
1808 {
1809 .pclk = 13000000,
1810 .settings = {
1811 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1812 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1813 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1814 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1815 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1816 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1817 }
1818 },
1819 {
1820 .pclk = 19200000,
1821 .settings = {
1822 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1823 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1824 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1825 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1826 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1827 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1828 }
1829 },
1830 };
1831
1832 static int max98090_find_divisor(int target_freq, int pclk)
1833 {
1834 int current_diff = INT_MAX;
1835 int test_diff = INT_MAX;
1836 int divisor_index = 0;
1837 int i;
1838
1839 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1840 test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1841 if (test_diff < current_diff) {
1842 current_diff = test_diff;
1843 divisor_index = i;
1844 }
1845 }
1846
1847 return divisor_index;
1848 }
1849
1850 static int max98090_find_closest_pclk(int pclk)
1851 {
1852 int m1;
1853 int m2;
1854 int i;
1855
1856 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1857 if (pclk == dmic_table[i].pclk)
1858 return i;
1859 if (pclk < dmic_table[i].pclk) {
1860 if (i == 0)
1861 return i;
1862 m1 = pclk - dmic_table[i-1].pclk;
1863 m2 = dmic_table[i].pclk - pclk;
1864 if (m1 < m2)
1865 return i - 1;
1866 else
1867 return i;
1868 }
1869 }
1870
1871 return -EINVAL;
1872 }
1873
1874 static int max98090_configure_dmic(struct max98090_priv *max98090,
1875 int target_dmic_clk, int pclk, int fs)
1876 {
1877 int micclk_index;
1878 int pclk_index;
1879 int dmic_freq;
1880 int dmic_comp;
1881 int i;
1882
1883 pclk_index = max98090_find_closest_pclk(pclk);
1884 if (pclk_index < 0)
1885 return pclk_index;
1886
1887 micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1888
1889 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1890 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1891 break;
1892 }
1893
1894 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1895 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1896
1897 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1898 M98090_MICCLK_MASK,
1899 micclk_index << M98090_MICCLK_SHIFT);
1900
1901 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1902 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1903 dmic_comp << M98090_DMIC_COMP_SHIFT |
1904 dmic_freq << M98090_DMIC_FREQ_SHIFT);
1905
1906 return 0;
1907 }
1908
1909 static int max98090_dai_startup(struct snd_pcm_substream *substream,
1910 struct snd_soc_dai *dai)
1911 {
1912 struct snd_soc_component *component = dai->component;
1913 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1914 unsigned int fmt = max98090->dai_fmt;
1915
1916 /* Remove 24-bit format support if it is not in right justified mode. */
1917 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) {
1918 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
1919 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
1920 }
1921 return 0;
1922 }
1923
1924 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1925 struct snd_pcm_hw_params *params,
1926 struct snd_soc_dai *dai)
1927 {
1928 struct snd_soc_component *component = dai->component;
1929 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1930 struct max98090_cdata *cdata;
1931
1932 cdata = &max98090->dai[0];
1933 max98090->bclk = snd_soc_params_to_bclk(params);
1934 if (params_channels(params) == 1)
1935 max98090->bclk *= 2;
1936
1937 max98090->lrclk = params_rate(params);
1938
1939 switch (params_width(params)) {
1940 case 16:
1941 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
1942 M98090_WS_MASK, 0);
1943 break;
1944 default:
1945 return -EINVAL;
1946 }
1947
1948 if (max98090->master)
1949 max98090_configure_bclk(component);
1950
1951 cdata->rate = max98090->lrclk;
1952
1953 /* Update filter mode */
1954 if (max98090->lrclk < 24000)
1955 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1956 M98090_MODE_MASK, 0);
1957 else
1958 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1959 M98090_MODE_MASK, M98090_MODE_MASK);
1960
1961 /* Update sample rate mode */
1962 if (max98090->lrclk < 50000)
1963 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1964 M98090_DHF_MASK, 0);
1965 else
1966 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1967 M98090_DHF_MASK, M98090_DHF_MASK);
1968
1969 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1970 max98090->lrclk);
1971
1972 return 0;
1973 }
1974
1975 /*
1976 * PLL / Sysclk
1977 */
1978 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1979 int clk_id, unsigned int freq, int dir)
1980 {
1981 struct snd_soc_component *component = dai->component;
1982 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1983
1984 /* Requested clock frequency is already setup */
1985 if (freq == max98090->sysclk)
1986 return 0;
1987
1988 if (!IS_ERR(max98090->mclk)) {
1989 freq = clk_round_rate(max98090->mclk, freq);
1990 clk_set_rate(max98090->mclk, freq);
1991 }
1992
1993 /* Setup clocks for slave mode, and using the PLL
1994 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1995 * 0x02 (when master clk is 20MHz to 40MHz)..
1996 * 0x03 (when master clk is 40MHz to 60MHz)..
1997 */
1998 if ((freq >= 10000000) && (freq <= 20000000)) {
1999 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2000 M98090_PSCLK_DIV1);
2001 max98090->pclk = freq;
2002 } else if ((freq > 20000000) && (freq <= 40000000)) {
2003 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2004 M98090_PSCLK_DIV2);
2005 max98090->pclk = freq >> 1;
2006 } else if ((freq > 40000000) && (freq <= 60000000)) {
2007 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2008 M98090_PSCLK_DIV4);
2009 max98090->pclk = freq >> 2;
2010 } else {
2011 dev_err(component->dev, "Invalid master clock frequency\n");
2012 return -EINVAL;
2013 }
2014
2015 max98090->sysclk = freq;
2016
2017 return 0;
2018 }
2019
2020 static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute,
2021 int direction)
2022 {
2023 struct snd_soc_component *component = codec_dai->component;
2024 int regval;
2025
2026 regval = mute ? M98090_DVM_MASK : 0;
2027 snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL,
2028 M98090_DVM_MASK, regval);
2029
2030 return 0;
2031 }
2032
2033 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2034 struct snd_soc_dai *dai)
2035 {
2036 struct snd_soc_component *component = dai->component;
2037 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2038
2039 switch (cmd) {
2040 case SNDRV_PCM_TRIGGER_START:
2041 case SNDRV_PCM_TRIGGER_RESUME:
2042 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2043 if (!max98090->master && snd_soc_dai_active(dai) == 1)
2044 queue_delayed_work(system_power_efficient_wq,
2045 &max98090->pll_det_enable_work,
2046 msecs_to_jiffies(10));
2047 break;
2048 case SNDRV_PCM_TRIGGER_STOP:
2049 case SNDRV_PCM_TRIGGER_SUSPEND:
2050 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2051 if (!max98090->master && snd_soc_dai_active(dai) == 1)
2052 schedule_work(&max98090->pll_det_disable_work);
2053 break;
2054 default:
2055 break;
2056 }
2057
2058 return 0;
2059 }
2060
2061 static void max98090_pll_det_enable_work(struct work_struct *work)
2062 {
2063 struct max98090_priv *max98090 =
2064 container_of(work, struct max98090_priv,
2065 pll_det_enable_work.work);
2066 struct snd_soc_component *component = max98090->component;
2067 unsigned int status, mask;
2068
2069 /*
2070 * Clear status register in order to clear possibly already occurred
2071 * PLL unlock. If PLL hasn't still locked, the status will be set
2072 * again and PLL unlock interrupt will occur.
2073 * Note this will clear all status bits
2074 */
2075 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2076
2077 /*
2078 * Queue jack work in case jack state has just changed but handler
2079 * hasn't run yet
2080 */
2081 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2082 status &= mask;
2083 if (status & M98090_JDET_MASK)
2084 queue_delayed_work(system_power_efficient_wq,
2085 &max98090->jack_work,
2086 msecs_to_jiffies(100));
2087
2088 /* Enable PLL unlock interrupt */
2089 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2090 M98090_IULK_MASK,
2091 1 << M98090_IULK_SHIFT);
2092 }
2093
2094 static void max98090_pll_det_disable_work(struct work_struct *work)
2095 {
2096 struct max98090_priv *max98090 =
2097 container_of(work, struct max98090_priv, pll_det_disable_work);
2098 struct snd_soc_component *component = max98090->component;
2099
2100 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2101
2102 /* Disable PLL unlock interrupt */
2103 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2104 M98090_IULK_MASK, 0);
2105 }
2106
2107 static void max98090_pll_work(struct max98090_priv *max98090)
2108 {
2109 struct snd_soc_component *component = max98090->component;
2110 unsigned int pll;
2111 int i;
2112
2113 if (!snd_soc_component_active(component))
2114 return;
2115
2116 dev_info_ratelimited(component->dev, "PLL unlocked\n");
2117
2118 /*
2119 * As the datasheet suggested, the maximum PLL lock time should be
2120 * 7 msec. The workaround resets the codec softly by toggling SHDN
2121 * off and on if PLL failed to lock for 10 msec. Notably, there is
2122 * no suggested hold time for SHDN off.
2123 */
2124
2125 /* Toggle shutdown OFF then ON */
2126 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2127 M98090_SHDNN_MASK, 0);
2128 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2129 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2130
2131 for (i = 0; i < 10; ++i) {
2132 /* Give PLL time to lock */
2133 usleep_range(1000, 1200);
2134
2135 /* Check lock status */
2136 pll = snd_soc_component_read(
2137 component, M98090_REG_DEVICE_STATUS);
2138 if (!(pll & M98090_ULK_MASK))
2139 break;
2140 }
2141 }
2142
2143 static void max98090_jack_work(struct work_struct *work)
2144 {
2145 struct max98090_priv *max98090 = container_of(work,
2146 struct max98090_priv,
2147 jack_work.work);
2148 struct snd_soc_component *component = max98090->component;
2149 int status = 0;
2150 int reg;
2151
2152 /* Read a second time */
2153 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2154
2155 /* Strong pull up allows mic detection */
2156 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2157 M98090_JDWK_MASK, 0);
2158
2159 msleep(50);
2160
2161 reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
2162
2163 /* Weak pull up allows only insertion detection */
2164 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2165 M98090_JDWK_MASK, M98090_JDWK_MASK);
2166 } else {
2167 reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
2168 }
2169
2170 reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
2171
2172 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2173 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2174 dev_dbg(component->dev, "No Headset Detected\n");
2175
2176 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2177
2178 status |= 0;
2179
2180 break;
2181
2182 case 0:
2183 if (max98090->jack_state ==
2184 M98090_JACK_STATE_HEADSET) {
2185
2186 dev_dbg(component->dev,
2187 "Headset Button Down Detected\n");
2188
2189 /*
2190 * max98090_headset_button_event(codec)
2191 * could be defined, then called here.
2192 */
2193
2194 status |= SND_JACK_HEADSET;
2195 status |= SND_JACK_BTN_0;
2196
2197 break;
2198 }
2199
2200 /* Line is reported as Headphone */
2201 /* Nokia Headset is reported as Headphone */
2202 /* Mono Headphone is reported as Headphone */
2203 dev_dbg(component->dev, "Headphone Detected\n");
2204
2205 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2206
2207 status |= SND_JACK_HEADPHONE;
2208
2209 break;
2210
2211 case M98090_JKSNS_MASK:
2212 dev_dbg(component->dev, "Headset Detected\n");
2213
2214 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2215
2216 status |= SND_JACK_HEADSET;
2217
2218 break;
2219
2220 default:
2221 dev_dbg(component->dev, "Unrecognized Jack Status\n");
2222 break;
2223 }
2224
2225 snd_soc_jack_report(max98090->jack, status,
2226 SND_JACK_HEADSET | SND_JACK_BTN_0);
2227 }
2228
2229 static irqreturn_t max98090_interrupt(int irq, void *data)
2230 {
2231 struct max98090_priv *max98090 = data;
2232 struct snd_soc_component *component = max98090->component;
2233 int ret;
2234 unsigned int mask;
2235 unsigned int active;
2236
2237 /* Treat interrupt before codec is initialized as spurious */
2238 if (component == NULL)
2239 return IRQ_NONE;
2240
2241 dev_dbg(component->dev, "***** max98090_interrupt *****\n");
2242
2243 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2244
2245 if (ret != 0) {
2246 dev_err(component->dev,
2247 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2248 ret);
2249 return IRQ_NONE;
2250 }
2251
2252 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2253
2254 if (ret != 0) {
2255 dev_err(component->dev,
2256 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2257 ret);
2258 return IRQ_NONE;
2259 }
2260
2261 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2262 active, mask, active & mask);
2263
2264 active &= mask;
2265
2266 if (!active)
2267 return IRQ_NONE;
2268
2269 if (active & M98090_CLD_MASK)
2270 dev_err(component->dev, "M98090_CLD_MASK\n");
2271
2272 if (active & M98090_SLD_MASK)
2273 dev_dbg(component->dev, "M98090_SLD_MASK\n");
2274
2275 if (active & M98090_ULK_MASK) {
2276 dev_dbg(component->dev, "M98090_ULK_MASK\n");
2277 max98090_pll_work(max98090);
2278 }
2279
2280 if (active & M98090_JDET_MASK) {
2281 dev_dbg(component->dev, "M98090_JDET_MASK\n");
2282
2283 pm_wakeup_event(component->dev, 100);
2284
2285 queue_delayed_work(system_power_efficient_wq,
2286 &max98090->jack_work,
2287 msecs_to_jiffies(100));
2288 }
2289
2290 if (active & M98090_DRCACT_MASK)
2291 dev_dbg(component->dev, "M98090_DRCACT_MASK\n");
2292
2293 if (active & M98090_DRCCLP_MASK)
2294 dev_err(component->dev, "M98090_DRCCLP_MASK\n");
2295
2296 return IRQ_HANDLED;
2297 }
2298
2299 /**
2300 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2301 *
2302 * @component: MAX98090 component
2303 * @jack: jack to report detection events on
2304 *
2305 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2306 * being used to bring out signals to the processor then only platform
2307 * data configuration is needed for MAX98090 and processor GPIOs should
2308 * be configured using snd_soc_jack_add_gpios() instead.
2309 *
2310 * If no jack is supplied detection will be disabled.
2311 */
2312 int max98090_mic_detect(struct snd_soc_component *component,
2313 struct snd_soc_jack *jack)
2314 {
2315 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2316
2317 dev_dbg(component->dev, "max98090_mic_detect\n");
2318
2319 max98090->jack = jack;
2320 if (jack) {
2321 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2322 M98090_IJDET_MASK,
2323 1 << M98090_IJDET_SHIFT);
2324 } else {
2325 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2326 M98090_IJDET_MASK,
2327 0);
2328 }
2329
2330 /* Send an initial empty report */
2331 snd_soc_jack_report(max98090->jack, 0,
2332 SND_JACK_HEADSET | SND_JACK_BTN_0);
2333
2334 queue_delayed_work(system_power_efficient_wq,
2335 &max98090->jack_work,
2336 msecs_to_jiffies(100));
2337
2338 return 0;
2339 }
2340 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2341
2342 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2343 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2344
2345 static const struct snd_soc_dai_ops max98090_dai_ops = {
2346 .startup = max98090_dai_startup,
2347 .set_sysclk = max98090_dai_set_sysclk,
2348 .set_fmt = max98090_dai_set_fmt,
2349 .set_tdm_slot = max98090_set_tdm_slot,
2350 .hw_params = max98090_dai_hw_params,
2351 .mute_stream = max98090_dai_mute,
2352 .trigger = max98090_dai_trigger,
2353 .no_capture_mute = 1,
2354 };
2355
2356 static struct snd_soc_dai_driver max98090_dai[] = {
2357 {
2358 .name = "HiFi",
2359 .playback = {
2360 .stream_name = "HiFi Playback",
2361 .channels_min = 2,
2362 .channels_max = 2,
2363 .rates = MAX98090_RATES,
2364 .formats = MAX98090_FORMATS,
2365 },
2366 .capture = {
2367 .stream_name = "HiFi Capture",
2368 .channels_min = 1,
2369 .channels_max = 2,
2370 .rates = MAX98090_RATES,
2371 .formats = MAX98090_FORMATS,
2372 },
2373 .ops = &max98090_dai_ops,
2374 }
2375 };
2376
2377 static int max98090_probe(struct snd_soc_component *component)
2378 {
2379 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2380 struct max98090_cdata *cdata;
2381 enum max98090_type devtype;
2382 int ret = 0;
2383 int err;
2384 unsigned int micbias;
2385
2386 dev_dbg(component->dev, "max98090_probe\n");
2387
2388 max98090->mclk = devm_clk_get(component->dev, "mclk");
2389 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2390 return -EPROBE_DEFER;
2391
2392 max98090->component = component;
2393
2394 /* Reset the codec, the DSP core, and disable all interrupts */
2395 max98090_reset(max98090);
2396
2397 /* Initialize private data */
2398
2399 max98090->sysclk = (unsigned)-1;
2400 max98090->pclk = (unsigned)-1;
2401 max98090->master = false;
2402
2403 cdata = &max98090->dai[0];
2404 cdata->rate = (unsigned)-1;
2405 cdata->fmt = (unsigned)-1;
2406
2407 max98090->lin_state = 0;
2408 max98090->pa1en = 0;
2409 max98090->pa2en = 0;
2410
2411 ret = snd_soc_component_read(component, M98090_REG_REVISION_ID);
2412 if (ret < 0) {
2413 dev_err(component->dev, "Failed to read device revision: %d\n",
2414 ret);
2415 goto err_access;
2416 }
2417
2418 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2419 devtype = MAX98090;
2420 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret);
2421 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2422 devtype = MAX98091;
2423 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret);
2424 } else {
2425 devtype = MAX98090;
2426 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret);
2427 }
2428
2429 if (max98090->devtype != devtype) {
2430 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n");
2431 max98090->devtype = devtype;
2432 }
2433
2434 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2435
2436 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2437 INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2438 max98090_pll_det_enable_work);
2439 INIT_WORK(&max98090->pll_det_disable_work,
2440 max98090_pll_det_disable_work);
2441
2442 /* Enable jack detection */
2443 snd_soc_component_write(component, M98090_REG_JACK_DETECT,
2444 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2445
2446 /*
2447 * Clear any old interrupts.
2448 * An old interrupt ocurring prior to installing the ISR
2449 * can keep a new interrupt from generating a trigger.
2450 */
2451 snd_soc_component_read(component, M98090_REG_DEVICE_STATUS);
2452
2453 /* High Performance is default */
2454 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2455 M98090_DACHP_MASK,
2456 1 << M98090_DACHP_SHIFT);
2457 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2458 M98090_PERFMODE_MASK,
2459 0 << M98090_PERFMODE_SHIFT);
2460 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
2461 M98090_ADCHP_MASK,
2462 1 << M98090_ADCHP_SHIFT);
2463
2464 /* Turn on VCM bandgap reference */
2465 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
2466 M98090_VCM_MODE_MASK);
2467
2468 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
2469 if (err) {
2470 micbias = M98090_MBVSEL_2V8;
2471 dev_info(component->dev, "use default 2.8v micbias\n");
2472 } else if (micbias > M98090_MBVSEL_2V8) {
2473 dev_err(component->dev, "micbias out of range 0x%x\n", micbias);
2474 micbias = M98090_MBVSEL_2V8;
2475 }
2476
2477 snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE,
2478 M98090_MBVSEL_MASK, micbias);
2479
2480 max98090_add_widgets(component);
2481
2482 err_access:
2483 return ret;
2484 }
2485
2486 static void max98090_remove(struct snd_soc_component *component)
2487 {
2488 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2489
2490 cancel_delayed_work_sync(&max98090->jack_work);
2491 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2492 cancel_work_sync(&max98090->pll_det_disable_work);
2493 max98090->component = NULL;
2494 }
2495
2496 static void max98090_seq_notifier(struct snd_soc_component *component,
2497 enum snd_soc_dapm_type event, int subseq)
2498 {
2499 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2500
2501 if (max98090->shdn_pending) {
2502 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2503 M98090_SHDNN_MASK, 0);
2504 msleep(40);
2505 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2506 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2507 max98090->shdn_pending = false;
2508 }
2509 }
2510
2511 static const struct snd_soc_component_driver soc_component_dev_max98090 = {
2512 .probe = max98090_probe,
2513 .remove = max98090_remove,
2514 .seq_notifier = max98090_seq_notifier,
2515 .set_bias_level = max98090_set_bias_level,
2516 .idle_bias_on = 1,
2517 .use_pmdown_time = 1,
2518 .endianness = 1,
2519 .non_legacy_dai_naming = 1,
2520 };
2521
2522 static const struct regmap_config max98090_regmap = {
2523 .reg_bits = 8,
2524 .val_bits = 8,
2525
2526 .max_register = MAX98090_MAX_REGISTER,
2527 .reg_defaults = max98090_reg,
2528 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2529 .volatile_reg = max98090_volatile_register,
2530 .readable_reg = max98090_readable_register,
2531 .cache_type = REGCACHE_RBTREE,
2532 };
2533
2534 static int max98090_i2c_probe(struct i2c_client *i2c,
2535 const struct i2c_device_id *i2c_id)
2536 {
2537 struct max98090_priv *max98090;
2538 const struct acpi_device_id *acpi_id;
2539 kernel_ulong_t driver_data = 0;
2540 int ret;
2541
2542 pr_debug("max98090_i2c_probe\n");
2543
2544 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2545 GFP_KERNEL);
2546 if (max98090 == NULL)
2547 return -ENOMEM;
2548
2549 if (ACPI_HANDLE(&i2c->dev)) {
2550 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2551 &i2c->dev);
2552 if (!acpi_id) {
2553 dev_err(&i2c->dev, "No driver data\n");
2554 return -EINVAL;
2555 }
2556 driver_data = acpi_id->driver_data;
2557 } else if (i2c_id) {
2558 driver_data = i2c_id->driver_data;
2559 }
2560
2561 max98090->devtype = driver_data;
2562 i2c_set_clientdata(i2c, max98090);
2563 max98090->pdata = i2c->dev.platform_data;
2564
2565 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2566 &max98090->dmic_freq);
2567 if (ret < 0)
2568 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2569
2570 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2571 if (IS_ERR(max98090->regmap)) {
2572 ret = PTR_ERR(max98090->regmap);
2573 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2574 goto err_enable;
2575 }
2576
2577 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2578 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2579 "max98090_interrupt", max98090);
2580 if (ret < 0) {
2581 dev_err(&i2c->dev, "request_irq failed: %d\n",
2582 ret);
2583 return ret;
2584 }
2585
2586 ret = devm_snd_soc_register_component(&i2c->dev,
2587 &soc_component_dev_max98090, max98090_dai,
2588 ARRAY_SIZE(max98090_dai));
2589 err_enable:
2590 return ret;
2591 }
2592
2593 static void max98090_i2c_shutdown(struct i2c_client *i2c)
2594 {
2595 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2596
2597 /*
2598 * Enable volume smoothing, disable zero cross. This will cause
2599 * a quick 40ms ramp to mute on shutdown.
2600 */
2601 regmap_write(max98090->regmap,
2602 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
2603 regmap_write(max98090->regmap,
2604 M98090_REG_DEVICE_SHUTDOWN, 0x00);
2605 msleep(40);
2606 }
2607
2608 static int max98090_i2c_remove(struct i2c_client *client)
2609 {
2610 max98090_i2c_shutdown(client);
2611
2612 return 0;
2613 }
2614
2615 #ifdef CONFIG_PM
2616 static int max98090_runtime_resume(struct device *dev)
2617 {
2618 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2619
2620 regcache_cache_only(max98090->regmap, false);
2621
2622 max98090_reset(max98090);
2623
2624 regcache_sync(max98090->regmap);
2625
2626 return 0;
2627 }
2628
2629 static int max98090_runtime_suspend(struct device *dev)
2630 {
2631 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2632
2633 regcache_cache_only(max98090->regmap, true);
2634
2635 return 0;
2636 }
2637 #endif
2638
2639 #ifdef CONFIG_PM_SLEEP
2640 static int max98090_resume(struct device *dev)
2641 {
2642 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2643 unsigned int status;
2644
2645 regcache_mark_dirty(max98090->regmap);
2646
2647 max98090_reset(max98090);
2648
2649 /* clear IRQ status */
2650 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2651
2652 regcache_sync(max98090->regmap);
2653
2654 return 0;
2655 }
2656 #endif
2657
2658 static const struct dev_pm_ops max98090_pm = {
2659 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2660 max98090_runtime_resume, NULL)
2661 SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume)
2662 };
2663
2664 static const struct i2c_device_id max98090_i2c_id[] = {
2665 { "max98090", MAX98090 },
2666 { "max98091", MAX98091 },
2667 { }
2668 };
2669 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2670
2671 #ifdef CONFIG_OF
2672 static const struct of_device_id max98090_of_match[] = {
2673 { .compatible = "maxim,max98090", },
2674 { .compatible = "maxim,max98091", },
2675 { }
2676 };
2677 MODULE_DEVICE_TABLE(of, max98090_of_match);
2678 #endif
2679
2680 #ifdef CONFIG_ACPI
2681 static const struct acpi_device_id max98090_acpi_match[] = {
2682 { "193C9890", MAX98090 },
2683 { }
2684 };
2685 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2686 #endif
2687
2688 static struct i2c_driver max98090_i2c_driver = {
2689 .driver = {
2690 .name = "max98090",
2691 .pm = &max98090_pm,
2692 .of_match_table = of_match_ptr(max98090_of_match),
2693 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
2694 },
2695 .probe = max98090_i2c_probe,
2696 .shutdown = max98090_i2c_shutdown,
2697 .remove = max98090_i2c_remove,
2698 .id_table = max98090_i2c_id,
2699 };
2700
2701 module_i2c_driver(max98090_i2c_driver);
2702
2703 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2704 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2705 MODULE_LICENSE("GPL");
Linux with added FPC-III support