sound/soc/codecs/nau8810.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * NAU8810 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Nuvoton Technology Corp.
   6  * Author: David Lin <ctlin0@nuvoton.com>
   7  */
   8
   9 #ifndef __NAU8810_H__
  10 #define __NAU8810_H__
  11
  12 #define NAU8810_REG_RESET               0x00
  13 #define NAU8810_REG_POWER1              0x01
  14 #define NAU8810_REG_POWER2              0x02
  15 #define NAU8810_REG_POWER3              0x03
  16 #define NAU8810_REG_IFACE               0x04
  17 #define NAU8810_REG_COMP                0x05
  18 #define NAU8810_REG_CLOCK               0x06
  19 #define NAU8810_REG_SMPLR               0x07
  20 #define NAU8810_REG_DAC         0x0A
  21 #define NAU8810_REG_DACGAIN             0x0B
  22 #define NAU8810_REG_ADC         0x0E
  23 #define NAU8810_REG_ADCGAIN             0x0F
  24 #define NAU8810_REG_EQ1         0x12
  25 #define NAU8810_REG_EQ2         0x13
  26 #define NAU8810_REG_EQ3         0x14
  27 #define NAU8810_REG_EQ4         0x15
  28 #define NAU8810_REG_EQ5         0x16
  29 #define NAU8810_REG_DACLIM1             0x18
  30 #define NAU8810_REG_DACLIM2             0x19
  31 #define NAU8810_REG_NOTCH1              0x1B
  32 #define NAU8810_REG_NOTCH2              0x1C
  33 #define NAU8810_REG_NOTCH3              0x1D
  34 #define NAU8810_REG_NOTCH4              0x1E
  35 #define NAU8810_REG_ALC1                0x20
  36 #define NAU8810_REG_ALC2                0x21
  37 #define NAU8810_REG_ALC3                0x22
  38 #define NAU8810_REG_NOISEGATE           0x23
  39 #define NAU8810_REG_PLLN                0x24
  40 #define NAU8810_REG_PLLK1               0x25
  41 #define NAU8810_REG_PLLK2               0x26
  42 #define NAU8810_REG_PLLK3               0x27
  43 #define NAU8810_REG_ATTEN               0x28
  44 #define NAU8810_REG_INPUT_SIGNAL        0x2C
  45 #define NAU8810_REG_PGAGAIN             0x2D
  46 #define NAU8810_REG_ADCBOOST            0x2F
  47 #define NAU8810_REG_OUTPUT              0x31
  48 #define NAU8810_REG_SPKMIX              0x32
  49 #define NAU8810_REG_SPKGAIN             0x36
  50 #define NAU8810_REG_MONOMIX             0x38
  51 #define NAU8810_REG_POWER4              0x3A
  52 #define NAU8810_REG_TSLOTCTL1           0x3B
  53 #define NAU8810_REG_TSLOTCTL2           0x3C
  54 #define NAU8810_REG_DEVICE_REVID        0x3E
  55 #define NAU8810_REG_I2C_DEVICEID        0x3F
  56 #define NAU8810_REG_ADDITIONID  0x40
  57 #define NAU8810_REG_RESERVE             0x41
  58 #define NAU8810_REG_OUTCTL              0x45
  59 #define NAU8810_REG_ALC1ENHAN1  0x46
  60 #define NAU8810_REG_ALC1ENHAN2  0x47
  61 #define NAU8810_REG_MISCCTL             0x49
  62 #define NAU8810_REG_OUTTIEOFF           0x4B
  63 #define NAU8810_REG_AGCP2POUT   0x4C
  64 #define NAU8810_REG_AGCPOUT             0x4D
  65 #define NAU8810_REG_AMTCTL              0x4E
  66 #define NAU8810_REG_OUTTIEOFFMAN        0x4F
  67 #define NAU8810_REG_MAX         NAU8810_REG_OUTTIEOFFMAN
  68
  69
  70 /* NAU8810_REG_POWER1 (0x1) */
  71 #define NAU8810_DCBUF_EN                (0x1 << 8)
  72 #define NAU8810_AUX_EN_SFT              6
  73 #define NAU8810_PLL_EN_SFT              5
  74 #define NAU8810_MICBIAS_EN_SFT  4
  75 #define NAU8810_ABIAS_EN                (0x1 << 3)
  76 #define NAU8810_IOBUF_EN                (0x1 << 2)
  77 #define NAU8810_REFIMP_MASK             0x3
  78 #define NAU8810_REFIMP_DIS              0x0
  79 #define NAU8810_REFIMP_80K              0x1
  80 #define NAU8810_REFIMP_300K             0x2
  81 #define NAU8810_REFIMP_3K               0x3
  82
  83 /* NAU8810_REG_POWER2 (0x2) */
  84 #define NAU8810_BST_EN_SFT              4
  85 #define NAU8810_PGA_EN_SFT              2
  86 #define NAU8810_ADC_EN_SFT              0
  87
  88 /* NAU8810_REG_POWER3 (0x3) */
  89 #define NAU8810_DAC_EN_SFT              0
  90 #define NAU8810_SPKMX_EN_SFT            2
  91 #define NAU8810_MOUTMX_EN_SFT   3
  92 #define NAU8810_PSPK_EN_SFT             5
  93 #define NAU8810_NSPK_EN_SFT             6
  94 #define NAU8810_MOUT_EN_SFT             7
  95
  96 /* NAU8810_REG_IFACE (0x4) */
  97 #define NAU8810_AIFMT_SFT               3
  98 #define NAU8810_AIFMT_MASK              (0x3 << NAU8810_AIFMT_SFT)
  99 #define NAU8810_AIFMT_RIGHT             (0x0 << NAU8810_AIFMT_SFT)
 100 #define NAU8810_AIFMT_LEFT              (0x1 << NAU8810_AIFMT_SFT)
 101 #define NAU8810_AIFMT_I2S               (0x2 << NAU8810_AIFMT_SFT)
 102 #define NAU8810_AIFMT_PCM_A             (0x3 << NAU8810_AIFMT_SFT)
 103 #define NAU8810_WLEN_SFT                5
 104 #define NAU8810_WLEN_MASK               (0x3 << NAU8810_WLEN_SFT)
 105 #define NAU8810_WLEN_16         (0x0 << NAU8810_WLEN_SFT)
 106 #define NAU8810_WLEN_20         (0x1 << NAU8810_WLEN_SFT)
 107 #define NAU8810_WLEN_24         (0x2 << NAU8810_WLEN_SFT)
 108 #define NAU8810_WLEN_32         (0x3 << NAU8810_WLEN_SFT)
 109 #define NAU8810_FSP_IF                  (0x1 << 7)
 110 #define NAU8810_BCLKP_IB                (0x1 << 8)
 111
 112 /* NAU8810_REG_COMP (0x5) */
 113 #define NAU8810_ADDAP_SFT               0
 114 #define NAU8810_ADCCM_SFT               1
 115 #define NAU8810_DACCM_SFT               3
 116
 117 /* NAU8810_REG_CLOCK (0x6) */
 118 #define NAU8810_CLKIO_MASK              0x1
 119 #define NAU8810_CLKIO_SLAVE             0x0
 120 #define NAU8810_CLKIO_MASTER            0x1
 121 #define NAU8810_BCLKSEL_SFT             2
 122 #define NAU8810_BCLKSEL_MASK            (0x7 << NAU8810_BCLKSEL_SFT)
 123 #define NAU8810_BCLKDIV_1               (0x0 << NAU8810_BCLKSEL_SFT)
 124 #define NAU8810_BCLKDIV_2               (0x1 << NAU8810_BCLKSEL_SFT)
 125 #define NAU8810_BCLKDIV_4               (0x2 << NAU8810_BCLKSEL_SFT)
 126 #define NAU8810_BCLKDIV_8               (0x3 << NAU8810_BCLKSEL_SFT)
 127 #define NAU8810_BCLKDIV_16              (0x4 << NAU8810_BCLKSEL_SFT)
 128 #define NAU8810_BCLKDIV_32              (0x5 << NAU8810_BCLKSEL_SFT)
 129 #define NAU8810_MCLKSEL_SFT             5
 130 #define NAU8810_MCLKSEL_MASK            (0x7 << NAU8810_MCLKSEL_SFT)
 131 #define NAU8810_CLKM_SFT                8
 132 #define NAU8810_CLKM_MASK               (0x1 << NAU8810_CLKM_SFT)
 133 #define NAU8810_CLKM_MCLK               (0x0 << NAU8810_CLKM_SFT)
 134 #define NAU8810_CLKM_PLL                (0x1 << NAU8810_CLKM_SFT)
 135
 136 /* NAU8810_REG_SMPLR (0x7) */
 137 #define NAU8810_SMPLR_SFT               1
 138 #define NAU8810_SMPLR_MASK              (0x7 << NAU8810_SMPLR_SFT)
 139 #define NAU8810_SMPLR_48K               (0x0 << NAU8810_SMPLR_SFT)
 140 #define NAU8810_SMPLR_32K               (0x1 << NAU8810_SMPLR_SFT)
 141 #define NAU8810_SMPLR_24K               (0x2 << NAU8810_SMPLR_SFT)
 142 #define NAU8810_SMPLR_16K               (0x3 << NAU8810_SMPLR_SFT)
 143 #define NAU8810_SMPLR_12K               (0x4 << NAU8810_SMPLR_SFT)
 144 #define NAU8810_SMPLR_8K                (0x5 << NAU8810_SMPLR_SFT)
 145
 146 /* NAU8810_REG_DAC (0xA) */
 147 #define NAU8810_DACPL_SFT               0
 148 #define NAU8810_DACOS_SFT               3
 149 #define NAU8810_DEEMP_SFT               4
 150
 151 /* NAU8810_REG_DACGAIN (0xB) */
 152 #define NAU8810_DACGAIN_SFT             0
 153
 154 /* NAU8810_REG_ADC (0xE) */
 155 #define NAU8810_ADCPL_SFT               0
 156 #define NAU8810_ADCOS_SFT               3
 157 #define NAU8810_HPF_SFT         4
 158 #define NAU8810_HPFEN_SFT               8
 159
 160 /* NAU8810_REG_ADCGAIN (0xF) */
 161 #define NAU8810_ADCGAIN_SFT             0
 162
 163 /* NAU8810_REG_EQ1 (0x12) */
 164 #define NAU8810_EQ1GC_SFT               0
 165 #define NAU8810_EQ1CF_SFT               5
 166 #define NAU8810_EQM_SFT         8
 167
 168 /* NAU8810_REG_EQ2 (0x13) */
 169 #define NAU8810_EQ2GC_SFT               0
 170 #define NAU8810_EQ2CF_SFT               5
 171 #define NAU8810_EQ2BW_SFT               8
 172
 173 /* NAU8810_REG_EQ3 (0x14) */
 174 #define NAU8810_EQ3GC_SFT               0
 175 #define NAU8810_EQ3CF_SFT               5
 176 #define NAU8810_EQ3BW_SFT               8
 177
 178 /* NAU8810_REG_EQ4 (0x15) */
 179 #define NAU8810_EQ4GC_SFT               0
 180 #define NAU8810_EQ4CF_SFT               5
 181 #define NAU8810_EQ4BW_SFT               8
 182
 183 /* NAU8810_REG_EQ5 (0x16) */
 184 #define NAU8810_EQ5GC_SFT               0
 185 #define NAU8810_EQ5CF_SFT               5
 186
 187 /* NAU8810_REG_DACLIM1 (0x18) */
 188 #define NAU8810_DACLIMATK_SFT           0
 189 #define NAU8810_DACLIMDCY_SFT           4
 190 #define NAU8810_DACLIMEN_SFT            8
 191
 192 /* NAU8810_REG_DACLIM2 (0x19) */
 193 #define NAU8810_DACLIMBST_SFT           0
 194 #define NAU8810_DACLIMTHL_SFT           4
 195
 196 /* NAU8810_REG_ALC1 (0x20) */
 197 #define NAU8810_ALCMINGAIN_SFT  0
 198 #define NAU8810_ALCMXGAIN_SFT           3
 199 #define NAU8810_ALCEN_SFT               8
 200
 201 /* NAU8810_REG_ALC2 (0x21) */
 202 #define NAU8810_ALCSL_SFT               0
 203 #define NAU8810_ALCHT_SFT               4
 204 #define NAU8810_ALCZC_SFT               8
 205
 206 /* NAU8810_REG_ALC3 (0x22) */
 207 #define NAU8810_ALCATK_SFT              0
 208 #define NAU8810_ALCDCY_SFT              4
 209 #define NAU8810_ALCM_SFT                8
 210
 211 /* NAU8810_REG_NOISEGATE (0x23) */
 212 #define NAU8810_ALCNTH_SFT              0
 213 #define NAU8810_ALCNEN_SFT              3
 214
 215 /* NAU8810_REG_PLLN (0x24) */
 216 #define NAU8810_PLLN_MASK               0xF
 217 #define NAU8810_PLLMCLK_DIV2            (0x1 << 4)
 218
 219 /* NAU8810_REG_PLLK1 (0x25) */
 220 #define NAU8810_PLLK1_SFT               18
 221 #define NAU8810_PLLK1_MASK              0x3F
 222
 223 /* NAU8810_REG_PLLK2 (0x26) */
 224 #define NAU8810_PLLK2_SFT               9
 225 #define NAU8810_PLLK2_MASK              0x1FF
 226
 227 /* NAU8810_REG_PLLK3 (0x27) */
 228 #define NAU8810_PLLK3_MASK              0x1FF
 229
 230 /* NAU8810_REG_INPUT_SIGNAL (0x2C) */
 231 #define NAU8810_PMICPGA_SFT             0
 232 #define NAU8810_PMICPGA_EN              (0x1 << NAU8810_PMICPGA_SFT)
 233 #define NAU8810_NMICPGA_SFT             1
 234 #define NAU8810_NMICPGA_EN              (0x1 << NAU8810_NMICPGA_SFT)
 235 #define NAU8810_AUXPGA_SFT              2
 236
 237 /* NAU8810_REG_PGAGAIN (0x2D) */
 238 #define NAU8810_PGAGAIN_SFT             0
 239 #define NAU8810_PGAMT_SFT               6
 240 #define NAU8810_PGAZC_SFT               7
 241
 242 /* NAU8810_REG_ADCBOOST (0x2F) */
 243 #define NAU8810_AUXBSTGAIN_SFT  0
 244 #define NAU8810_PMICBSTGAIN_SFT 4
 245 #define NAU8810_PMICBSTGAIN_MASK        (0x7 << NAU8810_PMICBSTGAIN_SFT)
 246 #define NAU8810_PGABST_SFT              8
 247
 248 /* NAU8810_REG_SPKMIX (0x32) */
 249 #define NAU8810_DACSPK_SFT              0
 250 #define NAU8810_BYPSPK_SFT              1
 251 #define NAU8810_AUXSPK_SFT              5
 252
 253 /* NAU8810_REG_SPKGAIN (0x36) */
 254 #define NAU8810_SPKGAIN_SFT             0
 255 #define NAU8810_SPKMT_SFT               6
 256 #define NAU8810_SPKZC_SFT               7
 257
 258 /* NAU8810_REG_MONOMIX (0x38) */
 259 #define NAU8810_DACMOUT_SFT             0
 260 #define NAU8810_BYPMOUT_SFT             1
 261 #define NAU8810_AUXMOUT_SFT             2
 262 #define NAU8810_MOUTMXMT_SFT            6
 263
 264
 265 /* System Clock Source */
 266 enum {
 267         NAU8810_SCLK_MCLK,
 268         NAU8810_SCLK_PLL,
 269 };
 270
 271 struct nau8810_pll {
 272         int pre_factor;
 273         int mclk_scaler;
 274         int pll_frac;
 275         int pll_int;
 276 };
 277
 278 struct nau8810 {
 279         struct device *dev;
 280         struct regmap *regmap;
 281         struct nau8810_pll pll;
 282         int sysclk;
 283         int clk_id;
 284 };
 285
 286 #endif