sound/soc/codecs/rt1015.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // rt1015.c  --  RT1015 ALSA SoC audio amplifier driver
   4 //
   5 // Copyright 2019 Realtek Semiconductor Corp.
   6 //
   7 // Author: Jack Yu <jack.yu@realtek.com>
   8 //
   9 //
  10
  11 #include <linux/acpi.h>
  12 #include <linux/delay.h>
  13 #include <linux/firmware.h>
  14 #include <linux/fs.h>
  15 #include <linux/gpio.h>
  16 #include <linux/i2c.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm.h>
  22 #include <linux/regmap.h>
  23 #include <sound/core.h>
  24 #include <sound/initval.h>
  25 #include <sound/pcm.h>
  26 #include <sound/pcm_params.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/soc.h>
  29 #include <sound/tlv.h>
  30 #include <sound/rt1015.h>
  31
  32 #include "rl6231.h"
  33 #include "rt1015.h"
  34
  35 static const struct rt1015_platform_data i2s_default_platform_data = {
  36         .power_up_delay_ms = 50,
  37 };
  38
  39 static const struct reg_default rt1015_reg[] = {
  40         { 0x0000, 0x0000 },
  41         { 0x0004, 0xa000 },
  42         { 0x0006, 0x0003 },
  43         { 0x000a, 0x081e },
  44         { 0x000c, 0x0006 },
  45         { 0x000e, 0x0000 },
  46         { 0x0010, 0x0000 },
  47         { 0x0012, 0x0000 },
  48         { 0x0014, 0x0000 },
  49         { 0x0016, 0x0000 },
  50         { 0x0018, 0x0000 },
  51         { 0x0020, 0x8000 },
  52         { 0x0022, 0x8043 },
  53         { 0x0076, 0x0000 },
  54         { 0x0078, 0x0000 },
  55         { 0x007a, 0x0002 },
  56         { 0x007c, 0x10ec },
  57         { 0x007d, 0x1015 },
  58         { 0x00f0, 0x5000 },
  59         { 0x00f2, 0x004c },
  60         { 0x00f3, 0xecfe },
  61         { 0x00f4, 0x0000 },
  62         { 0x00f6, 0x0400 },
  63         { 0x0100, 0x0028 },
  64         { 0x0102, 0xff02 },
  65         { 0x0104, 0xa213 },
  66         { 0x0106, 0x200c },
  67         { 0x010c, 0x0000 },
  68         { 0x010e, 0x0058 },
  69         { 0x0111, 0x0200 },
  70         { 0x0112, 0x0400 },
  71         { 0x0114, 0x0022 },
  72         { 0x0116, 0x0000 },
  73         { 0x0118, 0x0000 },
  74         { 0x011a, 0x0123 },
  75         { 0x011c, 0x4567 },
  76         { 0x0300, 0x203d },
  77         { 0x0302, 0x001e },
  78         { 0x0311, 0x0000 },
  79         { 0x0313, 0x6014 },
  80         { 0x0314, 0x00a2 },
  81         { 0x031a, 0x00a0 },
  82         { 0x031c, 0x001f },
  83         { 0x031d, 0xffff },
  84         { 0x031e, 0x0000 },
  85         { 0x031f, 0x0000 },
  86         { 0x0320, 0x0000 },
  87         { 0x0321, 0x0000 },
  88         { 0x0322, 0xd7df },
  89         { 0x0328, 0x10b2 },
  90         { 0x0329, 0x0175 },
  91         { 0x032a, 0x36ad },
  92         { 0x032b, 0x7e55 },
  93         { 0x032c, 0x0520 },
  94         { 0x032d, 0xaa00 },
  95         { 0x032e, 0x570e },
  96         { 0x0330, 0xe180 },
  97         { 0x0332, 0x0034 },
  98         { 0x0334, 0x0001 },
  99         { 0x0336, 0x0010 },
 100         { 0x0338, 0x0000 },
 101         { 0x04fa, 0x0030 },
 102         { 0x04fc, 0x35c8 },
 103         { 0x04fe, 0x0800 },
 104         { 0x0500, 0x0400 },
 105         { 0x0502, 0x1000 },
 106         { 0x0504, 0x0000 },
 107         { 0x0506, 0x04ff },
 108         { 0x0508, 0x0010 },
 109         { 0x050a, 0x001a },
 110         { 0x0519, 0x1c68 },
 111         { 0x051a, 0x0ccc },
 112         { 0x051b, 0x0666 },
 113         { 0x051d, 0x0000 },
 114         { 0x051f, 0x0000 },
 115         { 0x0536, 0x061c },
 116         { 0x0538, 0x0000 },
 117         { 0x053a, 0x0000 },
 118         { 0x053c, 0x0000 },
 119         { 0x053d, 0x0000 },
 120         { 0x053e, 0x0000 },
 121         { 0x053f, 0x0000 },
 122         { 0x0540, 0x0000 },
 123         { 0x0541, 0x0000 },
 124         { 0x0542, 0x0000 },
 125         { 0x0543, 0x0000 },
 126         { 0x0544, 0x0000 },
 127         { 0x0568, 0x0000 },
 128         { 0x056a, 0x0000 },
 129         { 0x1000, 0x0040 },
 130         { 0x1002, 0x5405 },
 131         { 0x1006, 0x5515 },
 132         { 0x1007, 0x05f7 },
 133         { 0x1009, 0x0b0a },
 134         { 0x100a, 0x00ef },
 135         { 0x100d, 0x0003 },
 136         { 0x1010, 0xa433 },
 137         { 0x1020, 0x0000 },
 138         { 0x1200, 0x5a01 },
 139         { 0x1202, 0x6524 },
 140         { 0x1204, 0x1f00 },
 141         { 0x1206, 0x0000 },
 142         { 0x1208, 0x0000 },
 143         { 0x120a, 0x0000 },
 144         { 0x120c, 0x0000 },
 145         { 0x120e, 0x0000 },
 146         { 0x1210, 0x0000 },
 147         { 0x1212, 0x0000 },
 148         { 0x1300, 0x10a1 },
 149         { 0x1302, 0x12ff },
 150         { 0x1304, 0x0400 },
 151         { 0x1305, 0x0844 },
 152         { 0x1306, 0x4611 },
 153         { 0x1308, 0x555e },
 154         { 0x130a, 0x0000 },
 155         { 0x130c, 0x2000 },
 156         { 0x130e, 0x0100 },
 157         { 0x130f, 0x0001 },
 158         { 0x1310, 0x0000 },
 159         { 0x1312, 0x0000 },
 160         { 0x1314, 0x0000 },
 161         { 0x1316, 0x0000 },
 162         { 0x1318, 0x0000 },
 163         { 0x131a, 0x0000 },
 164         { 0x1322, 0x0029 },
 165         { 0x1323, 0x4a52 },
 166         { 0x1324, 0x002c },
 167         { 0x1325, 0x0b02 },
 168         { 0x1326, 0x002d },
 169         { 0x1327, 0x6b5a },
 170         { 0x1328, 0x002e },
 171         { 0x1329, 0xcbb2 },
 172         { 0x132a, 0x0030 },
 173         { 0x132b, 0x2c0b },
 174         { 0x1330, 0x0031 },
 175         { 0x1331, 0x8c63 },
 176         { 0x1332, 0x0032 },
 177         { 0x1333, 0xecbb },
 178         { 0x1334, 0x0034 },
 179         { 0x1335, 0x4d13 },
 180         { 0x1336, 0x0037 },
 181         { 0x1337, 0x0dc3 },
 182         { 0x1338, 0x003d },
 183         { 0x1339, 0xef7b },
 184         { 0x133a, 0x0044 },
 185         { 0x133b, 0xd134 },
 186         { 0x133c, 0x0047 },
 187         { 0x133d, 0x91e4 },
 188         { 0x133e, 0x004d },
 189         { 0x133f, 0xc370 },
 190         { 0x1340, 0x0053 },
 191         { 0x1341, 0xf4fd },
 192         { 0x1342, 0x0060 },
 193         { 0x1343, 0x5816 },
 194         { 0x1344, 0x006c },
 195         { 0x1345, 0xbb2e },
 196         { 0x1346, 0x0072 },
 197         { 0x1347, 0xecbb },
 198         { 0x1348, 0x0076 },
 199         { 0x1349, 0x5d97 },
 200 };
 201
 202 static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
 203 {
 204         switch (reg) {
 205         case RT1015_RESET:
 206         case RT1015_CLK_DET:
 207         case RT1015_SIL_DET:
 208         case RT1015_VER_ID:
 209         case RT1015_VENDOR_ID:
 210         case RT1015_DEVICE_ID:
 211         case RT1015_PRO_ALT:
 212         case RT1015_DAC3:
 213         case RT1015_VBAT_TEST_OUT1:
 214         case RT1015_VBAT_TEST_OUT2:
 215         case RT1015_VBAT_PROT_ATT:
 216         case RT1015_VBAT_DET_CODE:
 217         case RT1015_SMART_BST_CTRL1:
 218         case RT1015_SPK_DC_DETECT1:
 219         case RT1015_SPK_DC_DETECT4:
 220         case RT1015_SPK_DC_DETECT5:
 221         case RT1015_DC_CALIB_CLSD1:
 222         case RT1015_DC_CALIB_CLSD5:
 223         case RT1015_DC_CALIB_CLSD6:
 224         case RT1015_DC_CALIB_CLSD7:
 225         case RT1015_DC_CALIB_CLSD8:
 226         case RT1015_S_BST_TIMING_INTER1:
 227         case RT1015_OSCK_STA:
 228         case RT1015_MONO_DYNA_CTRL1:
 229         case RT1015_MONO_DYNA_CTRL5:
 230                 return true;
 231
 232         default:
 233                 return false;
 234         }
 235 }
 236
 237 static bool rt1015_readable_register(struct device *dev, unsigned int reg)
 238 {
 239         switch (reg) {
 240         case RT1015_RESET:
 241         case RT1015_CLK2:
 242         case RT1015_CLK3:
 243         case RT1015_PLL1:
 244         case RT1015_PLL2:
 245         case RT1015_DUM_RW1:
 246         case RT1015_DUM_RW2:
 247         case RT1015_DUM_RW3:
 248         case RT1015_DUM_RW4:
 249         case RT1015_DUM_RW5:
 250         case RT1015_DUM_RW6:
 251         case RT1015_CLK_DET:
 252         case RT1015_SIL_DET:
 253         case RT1015_CUSTOMER_ID:
 254         case RT1015_PCODE_FWVER:
 255         case RT1015_VER_ID:
 256         case RT1015_VENDOR_ID:
 257         case RT1015_DEVICE_ID:
 258         case RT1015_PAD_DRV1:
 259         case RT1015_PAD_DRV2:
 260         case RT1015_GAT_BOOST:
 261         case RT1015_PRO_ALT:
 262         case RT1015_OSCK_STA:
 263         case RT1015_MAN_I2C:
 264         case RT1015_DAC1:
 265         case RT1015_DAC2:
 266         case RT1015_DAC3:
 267         case RT1015_ADC1:
 268         case RT1015_ADC2:
 269         case RT1015_TDM_MASTER:
 270         case RT1015_TDM_TCON:
 271         case RT1015_TDM1_1:
 272         case RT1015_TDM1_2:
 273         case RT1015_TDM1_3:
 274         case RT1015_TDM1_4:
 275         case RT1015_TDM1_5:
 276         case RT1015_MIXER1:
 277         case RT1015_MIXER2:
 278         case RT1015_ANA_PROTECT1:
 279         case RT1015_ANA_CTRL_SEQ1:
 280         case RT1015_ANA_CTRL_SEQ2:
 281         case RT1015_VBAT_DET_DEB:
 282         case RT1015_VBAT_VOLT_DET1:
 283         case RT1015_VBAT_VOLT_DET2:
 284         case RT1015_VBAT_TEST_OUT1:
 285         case RT1015_VBAT_TEST_OUT2:
 286         case RT1015_VBAT_PROT_ATT:
 287         case RT1015_VBAT_DET_CODE:
 288         case RT1015_PWR1:
 289         case RT1015_PWR4:
 290         case RT1015_PWR5:
 291         case RT1015_PWR6:
 292         case RT1015_PWR7:
 293         case RT1015_PWR8:
 294         case RT1015_PWR9:
 295         case RT1015_CLASSD_SEQ:
 296         case RT1015_SMART_BST_CTRL1:
 297         case RT1015_SMART_BST_CTRL2:
 298         case RT1015_ANA_CTRL1:
 299         case RT1015_ANA_CTRL2:
 300         case RT1015_PWR_STATE_CTRL:
 301         case RT1015_MONO_DYNA_CTRL:
 302         case RT1015_MONO_DYNA_CTRL1:
 303         case RT1015_MONO_DYNA_CTRL2:
 304         case RT1015_MONO_DYNA_CTRL3:
 305         case RT1015_MONO_DYNA_CTRL4:
 306         case RT1015_MONO_DYNA_CTRL5:
 307         case RT1015_SPK_VOL:
 308         case RT1015_SHORT_DETTOP1:
 309         case RT1015_SHORT_DETTOP2:
 310         case RT1015_SPK_DC_DETECT1:
 311         case RT1015_SPK_DC_DETECT2:
 312         case RT1015_SPK_DC_DETECT3:
 313         case RT1015_SPK_DC_DETECT4:
 314         case RT1015_SPK_DC_DETECT5:
 315         case RT1015_BAT_RPO_STEP1:
 316         case RT1015_BAT_RPO_STEP2:
 317         case RT1015_BAT_RPO_STEP3:
 318         case RT1015_BAT_RPO_STEP4:
 319         case RT1015_BAT_RPO_STEP5:
 320         case RT1015_BAT_RPO_STEP6:
 321         case RT1015_BAT_RPO_STEP7:
 322         case RT1015_BAT_RPO_STEP8:
 323         case RT1015_BAT_RPO_STEP9:
 324         case RT1015_BAT_RPO_STEP10:
 325         case RT1015_BAT_RPO_STEP11:
 326         case RT1015_BAT_RPO_STEP12:
 327         case RT1015_SPREAD_SPEC1:
 328         case RT1015_SPREAD_SPEC2:
 329         case RT1015_PAD_STATUS:
 330         case RT1015_PADS_PULLING_CTRL1:
 331         case RT1015_PADS_DRIVING:
 332         case RT1015_SYS_RST1:
 333         case RT1015_SYS_RST2:
 334         case RT1015_SYS_GATING1:
 335         case RT1015_TEST_MODE1:
 336         case RT1015_TEST_MODE2:
 337         case RT1015_TIMING_CTRL1:
 338         case RT1015_PLL_INT:
 339         case RT1015_TEST_OUT1:
 340         case RT1015_DC_CALIB_CLSD1:
 341         case RT1015_DC_CALIB_CLSD2:
 342         case RT1015_DC_CALIB_CLSD3:
 343         case RT1015_DC_CALIB_CLSD4:
 344         case RT1015_DC_CALIB_CLSD5:
 345         case RT1015_DC_CALIB_CLSD6:
 346         case RT1015_DC_CALIB_CLSD7:
 347         case RT1015_DC_CALIB_CLSD8:
 348         case RT1015_DC_CALIB_CLSD9:
 349         case RT1015_DC_CALIB_CLSD10:
 350         case RT1015_CLSD_INTERNAL1:
 351         case RT1015_CLSD_INTERNAL2:
 352         case RT1015_CLSD_INTERNAL3:
 353         case RT1015_CLSD_INTERNAL4:
 354         case RT1015_CLSD_INTERNAL5:
 355         case RT1015_CLSD_INTERNAL6:
 356         case RT1015_CLSD_INTERNAL7:
 357         case RT1015_CLSD_INTERNAL8:
 358         case RT1015_CLSD_INTERNAL9:
 359         case RT1015_CLSD_OCP_CTRL:
 360         case RT1015_VREF_LV:
 361         case RT1015_MBIAS1:
 362         case RT1015_MBIAS2:
 363         case RT1015_MBIAS3:
 364         case RT1015_MBIAS4:
 365         case RT1015_VREF_LV1:
 366         case RT1015_S_BST_TIMING_INTER1:
 367         case RT1015_S_BST_TIMING_INTER2:
 368         case RT1015_S_BST_TIMING_INTER3:
 369         case RT1015_S_BST_TIMING_INTER4:
 370         case RT1015_S_BST_TIMING_INTER5:
 371         case RT1015_S_BST_TIMING_INTER6:
 372         case RT1015_S_BST_TIMING_INTER7:
 373         case RT1015_S_BST_TIMING_INTER8:
 374         case RT1015_S_BST_TIMING_INTER9:
 375         case RT1015_S_BST_TIMING_INTER10:
 376         case RT1015_S_BST_TIMING_INTER11:
 377         case RT1015_S_BST_TIMING_INTER12:
 378         case RT1015_S_BST_TIMING_INTER13:
 379         case RT1015_S_BST_TIMING_INTER14:
 380         case RT1015_S_BST_TIMING_INTER15:
 381         case RT1015_S_BST_TIMING_INTER16:
 382         case RT1015_S_BST_TIMING_INTER17:
 383         case RT1015_S_BST_TIMING_INTER18:
 384         case RT1015_S_BST_TIMING_INTER19:
 385         case RT1015_S_BST_TIMING_INTER20:
 386         case RT1015_S_BST_TIMING_INTER21:
 387         case RT1015_S_BST_TIMING_INTER22:
 388         case RT1015_S_BST_TIMING_INTER23:
 389         case RT1015_S_BST_TIMING_INTER24:
 390         case RT1015_S_BST_TIMING_INTER25:
 391         case RT1015_S_BST_TIMING_INTER26:
 392         case RT1015_S_BST_TIMING_INTER27:
 393         case RT1015_S_BST_TIMING_INTER28:
 394         case RT1015_S_BST_TIMING_INTER29:
 395         case RT1015_S_BST_TIMING_INTER30:
 396         case RT1015_S_BST_TIMING_INTER31:
 397         case RT1015_S_BST_TIMING_INTER32:
 398         case RT1015_S_BST_TIMING_INTER33:
 399         case RT1015_S_BST_TIMING_INTER34:
 400         case RT1015_S_BST_TIMING_INTER35:
 401         case RT1015_S_BST_TIMING_INTER36:
 402                 return true;
 403
 404         default:
 405                 return false;
 406         }
 407 }
 408
 409 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
 410
 411 static const char * const rt1015_din_source_select[] = {
 412         "Left",
 413         "Right",
 414         "Left + Right average",
 415 };
 416
 417 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
 418         rt1015_din_source_select);
 419
 420 static const char * const rt1015_boost_mode[] = {
 421         "Bypass", "Adaptive", "Fixed Adaptive"
 422 };
 423
 424 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
 425         rt1015_boost_mode);
 426
 427 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
 428                 struct snd_ctl_elem_value *ucontrol)
 429 {
 430         struct snd_soc_component *component =
 431                 snd_soc_kcontrol_component(kcontrol);
 432         struct rt1015_priv *rt1015 =
 433                 snd_soc_component_get_drvdata(component);
 434
 435         ucontrol->value.integer.value[0] = rt1015->boost_mode;
 436
 437         return 0;
 438 }
 439
 440 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
 441                 struct snd_ctl_elem_value *ucontrol)
 442 {
 443         struct snd_soc_component *component =
 444                 snd_soc_kcontrol_component(kcontrol);
 445         struct rt1015_priv *rt1015 =
 446                 snd_soc_component_get_drvdata(component);
 447
 448         rt1015->boost_mode = ucontrol->value.integer.value[0];
 449
 450         switch (rt1015->boost_mode) {
 451         case BYPASS:
 452                 snd_soc_component_update_bits(component,
 453                         RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
 454                         RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
 455                         RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
 456                         RT1015_BYPASS_SWRREG_BYPASS);
 457                 break;
 458         case ADAPTIVE:
 459                 snd_soc_component_update_bits(component,
 460                         RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
 461                         RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
 462                         RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
 463                         RT1015_BYPASS_SWRREG_PASS);
 464                 break;
 465         case FIXED_ADAPTIVE:
 466                 snd_soc_component_update_bits(component,
 467                         RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
 468                         RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
 469                         RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
 470                         RT1015_BYPASS_SWRREG_PASS);
 471                 break;
 472         default:
 473                 dev_err(component->dev, "Unknown boost control.\n");
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
 480                 struct snd_ctl_elem_value *ucontrol)
 481 {
 482         struct snd_soc_component *component =
 483                 snd_soc_kcontrol_component(kcontrol);
 484         struct rt1015_priv *rt1015 =
 485                 snd_soc_component_get_drvdata(component);
 486
 487         ucontrol->value.integer.value[0] = rt1015->bypass_boost;
 488
 489         return 0;
 490 }
 491
 492 static void rt1015_calibrate(struct rt1015_priv *rt1015)
 493 {
 494         struct snd_soc_component *component = rt1015->component;
 495         struct regmap *regmap = rt1015->regmap;
 496
 497         snd_soc_dapm_mutex_lock(&component->dapm);
 498         regcache_cache_bypass(regmap, true);
 499
 500         regmap_write(regmap, RT1015_PWR9, 0xAA60);
 501         regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0089);
 502         regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x008A);
 503         regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x008C);
 504         regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x008D);
 505         regmap_write(regmap, RT1015_PWR4, 0x80B2);
 506         regmap_write(regmap, RT1015_CLASSD_SEQ, 0x5797);
 507         regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2100);
 508         regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0100);
 509         regmap_write(regmap, RT1015_PWR5, 0x2175);
 510         regmap_write(regmap, RT1015_MIXER1, 0x005D);
 511         regmap_write(regmap, RT1015_CLSD_INTERNAL1, 0x00A1);
 512         regmap_write(regmap, RT1015_CLSD_INTERNAL2, 0x12F7);
 513         regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x1205);
 514         msleep(200);
 515         regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2000);
 516         regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0180);
 517         regmap_write(regmap, RT1015_CLSD_INTERNAL1, 0x00A1);
 518         regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x0A05);
 519         msleep(200);
 520         regmap_write(regmap, RT1015_PWR4, 0x00B2);
 521         regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2028);
 522         regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
 523         regmap_write(regmap, RT1015_PWR5, 0x0175);
 524         regmap_write(regmap, RT1015_CLSD_INTERNAL1, 0x1721);
 525         regmap_write(regmap, RT1015_CLASSD_SEQ, 0x570E);
 526         regmap_write(regmap, RT1015_MIXER1, 0x203D);
 527         regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5A01);
 528         regmap_write(regmap, RT1015_CLSD_INTERNAL2, 0x12FF);
 529         regmap_write(regmap, RT1015_GAT_BOOST, 0x0eFE);
 530         regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x008E);
 531         regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0088);
 532         regmap_write(regmap, RT1015_SYS_RST1, 0x05F5);
 533         regmap_write(regmap, RT1015_SYS_RST2, 0x0b9a);
 534
 535         regcache_cache_bypass(regmap, false);
 536         regcache_mark_dirty(regmap);
 537         regcache_sync(regmap);
 538         snd_soc_dapm_mutex_unlock(&component->dapm);
 539 }
 540
 541 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
 542                 struct snd_ctl_elem_value *ucontrol)
 543 {
 544         struct snd_soc_component *component =
 545                 snd_soc_kcontrol_component(kcontrol);
 546         struct rt1015_priv *rt1015 =
 547                 snd_soc_component_get_drvdata(component);
 548
 549         if (!rt1015->dac_is_used) {
 550                 rt1015->bypass_boost = ucontrol->value.integer.value[0];
 551                 if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
 552                         !rt1015->cali_done) {
 553                         rt1015_calibrate(rt1015);
 554                         rt1015->cali_done = 1;
 555
 556                         regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010);
 557                 }
 558         } else
 559                 dev_err(component->dev, "DAC is being used!\n");
 560
 561         return 0;
 562 }
 563
 564 static void rt1015_flush_work(struct work_struct *work)
 565 {
 566         struct rt1015_priv *rt1015 = container_of(work, struct rt1015_priv,
 567                                                 flush_work.work);
 568         struct snd_soc_component *component = rt1015->component;
 569         unsigned int val, i = 0, count = 200;
 570
 571         while (i < count) {
 572                 usleep_range(1000, 1500);
 573                 dev_dbg(component->dev, "Flush DAC (retry:%u)\n", i);
 574                 regmap_read(rt1015->regmap, RT1015_CLK_DET, &val);
 575                 if (val & 0x800)
 576                         break;
 577                 i++;
 578         }
 579
 580         regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597);
 581         regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7);
 582         regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028);
 583
 584         if (val & 0x800)
 585                 dev_dbg(component->dev, "Flush DAC completed.\n");
 586         else
 587                 dev_warn(component->dev, "Fail to flush DAC data.\n");
 588 }
 589
 590 static const struct snd_kcontrol_new rt1015_snd_controls[] = {
 591         SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
 592                 127, 0, dac_vol_tlv),
 593         SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
 594                 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
 595         SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
 596                 rt1015_boost_mode_get, rt1015_boost_mode_put),
 597         SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
 598         SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
 599                 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
 600 };
 601
 602 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
 603                          struct snd_soc_dapm_widget *sink)
 604 {
 605         struct snd_soc_component *component =
 606                 snd_soc_dapm_to_component(source->dapm);
 607         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
 608
 609         if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
 610                 return 1;
 611         else
 612                 return 0;
 613 }
 614
 615 static int r1015_dac_event(struct snd_soc_dapm_widget *w,
 616         struct snd_kcontrol *kcontrol, int event)
 617 {
 618         struct snd_soc_component *component =
 619                 snd_soc_dapm_to_component(w->dapm);
 620         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
 621
 622         switch (event) {
 623         case SND_SOC_DAPM_PRE_PMU:
 624                 rt1015->dac_is_used = 1;
 625                 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
 626                         snd_soc_component_write(component,
 627                                 RT1015_SYS_RST1, 0x05f7);
 628                         snd_soc_component_write(component,
 629                                 RT1015_SYS_RST2, 0x0b0a);
 630                         snd_soc_component_write(component,
 631                                 RT1015_GAT_BOOST, 0xacfe);
 632                         snd_soc_component_write(component,
 633                                 RT1015_PWR9, 0xaa00);
 634                         snd_soc_component_write(component,
 635                                 RT1015_GAT_BOOST, 0xecfe);
 636                 } else {
 637                         snd_soc_component_write(component,
 638                                 0x032d, 0xaa60);
 639                         snd_soc_component_write(component,
 640                                 RT1015_SYS_RST1, 0x05f7);
 641                         snd_soc_component_write(component,
 642                                 RT1015_SYS_RST2, 0x0b0a);
 643                         snd_soc_component_write(component,
 644                                 RT1015_PWR_STATE_CTRL, 0x008e);
 645                 }
 646                 break;
 647
 648         case SND_SOC_DAPM_POST_PMU:
 649                 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8);
 650                 break;
 651
 652         case SND_SOC_DAPM_POST_PMD:
 653                 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
 654                         snd_soc_component_write(component,
 655                                 RT1015_PWR9, 0xa800);
 656                         snd_soc_component_write(component,
 657                                 RT1015_SYS_RST1, 0x05f5);
 658                         snd_soc_component_write(component,
 659                                 RT1015_SYS_RST2, 0x0b9a);
 660                 } else {
 661                         snd_soc_component_write(component,
 662                                 0x032d, 0xaa60);
 663                         snd_soc_component_write(component,
 664                                 RT1015_PWR_STATE_CTRL, 0x0088);
 665                         snd_soc_component_write(component,
 666                                 RT1015_SYS_RST1, 0x05f5);
 667                         snd_soc_component_write(component,
 668                                 RT1015_SYS_RST2, 0x0b9a);
 669                 }
 670                 rt1015->dac_is_used = 0;
 671
 672                 cancel_delayed_work_sync(&rt1015->flush_work);
 673                 break;
 674
 675         default:
 676                 break;
 677         }
 678         return 0;
 679 }
 680
 681 static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
 682         struct snd_kcontrol *kcontrol, int event)
 683 {
 684         struct snd_soc_component *component =
 685                 snd_soc_dapm_to_component(w->dapm);
 686         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
 687
 688         switch (event) {
 689         case SND_SOC_DAPM_POST_PMU:
 690                 if (rt1015->hw_config == RT1015_HW_28)
 691                         schedule_delayed_work(&rt1015->flush_work, msecs_to_jiffies(10));
 692                 msleep(rt1015->pdata.power_up_delay_ms);
 693                 break;
 694         default:
 695                 break;
 696         }
 697         return 0;
 698 }
 699
 700 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
 701         SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
 702                 NULL, 0),
 703         SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
 704         SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
 705                 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 706                 SND_SOC_DAPM_POST_PMD),
 707         SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
 708                         rt1015_amp_drv_event, SND_SOC_DAPM_POST_PMU),
 709         SND_SOC_DAPM_OUTPUT("SPO"),
 710 };
 711
 712 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
 713         { "DAC", NULL, "AIFRX" },
 714         { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
 715         { "Amp Drv", NULL, "DAC" },
 716         { "SPO", NULL, "Amp Drv" },
 717 };
 718
 719 static int rt1015_hw_params(struct snd_pcm_substream *substream,
 720         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 721 {
 722         struct snd_soc_component *component = dai->component;
 723         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
 724         int pre_div, bclk_ms, frame_size;
 725         unsigned int val_len = 0;
 726
 727         rt1015->lrck = params_rate(params);
 728         pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck);
 729         if (pre_div < 0) {
 730                 dev_err(component->dev, "Unsupported clock rate\n");
 731                 return -EINVAL;
 732         }
 733
 734         frame_size = snd_soc_params_to_frame_size(params);
 735         if (frame_size < 0) {
 736                 dev_err(component->dev, "Unsupported frame size: %d\n",
 737                         frame_size);
 738                 return -EINVAL;
 739         }
 740
 741         bclk_ms = frame_size > 32;
 742         rt1015->bclk = rt1015->lrck * (32 << bclk_ms);
 743
 744         dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
 745                                 bclk_ms, pre_div, dai->id);
 746
 747         dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
 748                                 rt1015->lrck, pre_div, dai->id);
 749
 750         switch (params_width(params)) {
 751         case 16:
 752                 break;
 753         case 20:
 754                 val_len = RT1015_I2S_DL_20;
 755                 break;
 756         case 24:
 757                 val_len = RT1015_I2S_DL_24;
 758                 break;
 759         case 8:
 760                 val_len = RT1015_I2S_DL_8;
 761                 break;
 762         default:
 763                 return -EINVAL;
 764         }
 765
 766         snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
 767                 RT1015_I2S_DL_MASK, val_len);
 768         snd_soc_component_update_bits(component, RT1015_CLK2,
 769                 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
 770
 771         return 0;
 772 }
 773
 774 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 775 {
 776         struct snd_soc_component *component = dai->component;
 777         unsigned int reg_val = 0, reg_val2 = 0;
 778
 779         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 780         case SND_SOC_DAIFMT_CBM_CFM:
 781                 reg_val |= RT1015_TCON_TDM_MS_M;
 782                 break;
 783         case SND_SOC_DAIFMT_CBS_CFS:
 784                 reg_val |= RT1015_TCON_TDM_MS_S;
 785                 break;
 786         default:
 787                 return -EINVAL;
 788         }
 789
 790         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 791         case SND_SOC_DAIFMT_NB_NF:
 792                 break;
 793         case SND_SOC_DAIFMT_IB_NF:
 794                 reg_val2 |= RT1015_TDM_INV_BCLK;
 795                 break;
 796         default:
 797                 return -EINVAL;
 798         }
 799
 800         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 801         case SND_SOC_DAIFMT_I2S:
 802                 break;
 803
 804         case SND_SOC_DAIFMT_LEFT_J:
 805                 reg_val |= RT1015_I2S_M_DF_LEFT;
 806                 break;
 807
 808         case SND_SOC_DAIFMT_DSP_A:
 809                 reg_val |= RT1015_I2S_M_DF_PCM_A;
 810                 break;
 811
 812         case SND_SOC_DAIFMT_DSP_B:
 813                 reg_val |= RT1015_I2S_M_DF_PCM_B;
 814                 break;
 815
 816         default:
 817                 return -EINVAL;
 818         }
 819
 820         snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
 821                         RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
 822                         reg_val);
 823         snd_soc_component_update_bits(component, RT1015_TDM1_1,
 824                         RT1015_TDM_INV_BCLK_MASK, reg_val2);
 825
 826         return 0;
 827 }
 828
 829 static int rt1015_set_component_sysclk(struct snd_soc_component *component,
 830                 int clk_id, int source, unsigned int freq, int dir)
 831 {
 832         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
 833         unsigned int reg_val = 0;
 834
 835         if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
 836                 return 0;
 837
 838         switch (clk_id) {
 839         case RT1015_SCLK_S_MCLK:
 840                 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
 841                 break;
 842
 843         case RT1015_SCLK_S_PLL:
 844                 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
 845                 break;
 846
 847         default:
 848                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
 849                 return -EINVAL;
 850         }
 851
 852         rt1015->sysclk = freq;
 853         rt1015->sysclk_src = clk_id;
 854
 855         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
 856                 freq, clk_id);
 857
 858         snd_soc_component_update_bits(component, RT1015_CLK2,
 859                         RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
 860
 861         return 0;
 862 }
 863
 864 static int rt1015_set_component_pll(struct snd_soc_component *component,
 865                 int pll_id, int source, unsigned int freq_in,
 866                 unsigned int freq_out)
 867 {
 868         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
 869         struct rl6231_pll_code pll_code;
 870         int ret;
 871
 872         if (!freq_in || !freq_out) {
 873                 dev_dbg(component->dev, "PLL disabled\n");
 874
 875                 rt1015->pll_in = 0;
 876                 rt1015->pll_out = 0;
 877
 878                 return 0;
 879         }
 880
 881         if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
 882                 freq_out == rt1015->pll_out)
 883                 return 0;
 884
 885         if (source == RT1015_PLL_S_BCLK) {
 886                 if (rt1015->bclk_ratio == 0) {
 887                         dev_err(component->dev,
 888                                 "Can not support bclk ratio as 0.\n");
 889                         return -EINVAL;
 890                 }
 891         }
 892
 893         switch (source) {
 894         case RT1015_PLL_S_MCLK:
 895                 snd_soc_component_update_bits(component, RT1015_CLK2,
 896                         RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
 897                 break;
 898
 899         case RT1015_PLL_S_BCLK:
 900                 snd_soc_component_update_bits(component, RT1015_CLK2,
 901                         RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
 902                 break;
 903
 904         default:
 905                 dev_err(component->dev, "Unknown PLL Source %d\n", source);
 906                 return -EINVAL;
 907         }
 908
 909         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
 910         if (ret < 0) {
 911                 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
 912                 return ret;
 913         }
 914
 915         dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
 916                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
 917                 pll_code.n_code, pll_code.k_code);
 918
 919         snd_soc_component_write(component, RT1015_PLL1,
 920                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT |
 921                 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code);
 922         snd_soc_component_write(component, RT1015_PLL2,
 923                 pll_code.k_code);
 924
 925         rt1015->pll_in = freq_in;
 926         rt1015->pll_out = freq_out;
 927         rt1015->pll_src = source;
 928
 929         return 0;
 930 }
 931
 932 static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
 933 {
 934         struct snd_soc_component *component = dai->component;
 935         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
 936
 937         dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
 938
 939         rt1015->bclk_ratio = ratio;
 940
 941         if (ratio == 50) {
 942                 dev_dbg(component->dev, "Unsupport bclk ratio\n");
 943                 return -EINVAL;
 944         }
 945
 946         return 0;
 947 }
 948
 949 static int rt1015_set_tdm_slot(struct snd_soc_dai *dai,
 950         unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
 951 {
 952         struct snd_soc_component *component = dai->component;
 953         unsigned int val = 0, rx_slotnum, tx_slotnum;
 954         int ret = 0, first_bit;
 955
 956         switch (slots) {
 957         case 2:
 958                 val |= RT1015_I2S_TX_2CH;
 959                 break;
 960         case 4:
 961                 val |= RT1015_I2S_TX_4CH;
 962                 break;
 963         case 6:
 964                 val |= RT1015_I2S_TX_6CH;
 965                 break;
 966         case 8:
 967                 val |= RT1015_I2S_TX_8CH;
 968                 break;
 969         default:
 970                 ret = -EINVAL;
 971                 goto _set_tdm_err_;
 972         }
 973
 974         switch (slot_width) {
 975         case 16:
 976                 val |= RT1015_I2S_CH_TX_LEN_16B;
 977                 break;
 978         case 20:
 979                 val |= RT1015_I2S_CH_TX_LEN_20B;
 980                 break;
 981         case 24:
 982                 val |= RT1015_I2S_CH_TX_LEN_24B;
 983                 break;
 984         case 32:
 985                 val |= RT1015_I2S_CH_TX_LEN_32B;
 986                 break;
 987         default:
 988                 ret = -EINVAL;
 989                 goto _set_tdm_err_;
 990         }
 991
 992         /* Rx slot configuration */
 993         rx_slotnum = hweight_long(rx_mask);
 994         if (rx_slotnum != 1) {
 995                 ret = -EINVAL;
 996                 dev_err(component->dev, "too many rx slots or zero slot\n");
 997                 goto _set_tdm_err_;
 998         }
 999
1000         /* This is an assumption that the system sends stereo audio to the amplifier typically.
1001          * And the stereo audio is placed in slot 0/2/4/6 as the starting slot.
1002          * The users could select the channel from L/R/L+R by "Mono LR Select" control.
1003          */
1004         first_bit = __ffs(rx_mask);
1005         switch (first_bit) {
1006         case 0:
1007         case 2:
1008         case 4:
1009         case 6:
1010                 snd_soc_component_update_bits(component,
1011                         RT1015_TDM1_4,
1012                         RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
1013                         RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
1014                         (first_bit << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
1015                         ((first_bit+1) << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
1016                 break;
1017         case 1:
1018         case 3:
1019         case 5:
1020         case 7:
1021                 snd_soc_component_update_bits(component,
1022                         RT1015_TDM1_4,
1023                         RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
1024                         RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
1025                         ((first_bit-1) << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
1026                         (first_bit << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
1027                 break;
1028         default:
1029                 ret = -EINVAL;
1030                 goto _set_tdm_err_;
1031         }
1032
1033         /* Tx slot configuration */
1034         tx_slotnum = hweight_long(tx_mask);
1035         if (tx_slotnum) {
1036                 ret = -EINVAL;
1037                 dev_err(component->dev, "doesn't need to support tx slots\n");
1038                 goto _set_tdm_err_;
1039         }
1040
1041         snd_soc_component_update_bits(component, RT1015_TDM1_1,
1042                 RT1015_I2S_CH_TX_MASK | RT1015_I2S_CH_RX_MASK |
1043                 RT1015_I2S_CH_TX_LEN_MASK | RT1015_I2S_CH_RX_LEN_MASK, val);
1044
1045 _set_tdm_err_:
1046         return ret;
1047 }
1048
1049 static int rt1015_probe(struct snd_soc_component *component)
1050 {
1051         struct rt1015_priv *rt1015 =
1052                 snd_soc_component_get_drvdata(component);
1053
1054         rt1015->component = component;
1055         rt1015->bclk_ratio = 0;
1056         rt1015->cali_done = 0;
1057
1058         INIT_DELAYED_WORK(&rt1015->flush_work, rt1015_flush_work);
1059
1060         return 0;
1061 }
1062
1063 static void rt1015_remove(struct snd_soc_component *component)
1064 {
1065         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1066
1067         cancel_delayed_work_sync(&rt1015->flush_work);
1068         regmap_write(rt1015->regmap, RT1015_RESET, 0);
1069 }
1070
1071 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1072 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1073                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1074
1075 static struct snd_soc_dai_ops rt1015_aif_dai_ops = {
1076         .hw_params = rt1015_hw_params,
1077         .set_fmt = rt1015_set_dai_fmt,
1078         .set_bclk_ratio = rt1015_set_bclk_ratio,
1079         .set_tdm_slot = rt1015_set_tdm_slot,
1080 };
1081
1082 static struct snd_soc_dai_driver rt1015_dai[] = {
1083         {
1084                 .name = "rt1015-aif",
1085                 .id = 0,
1086                 .playback = {
1087                         .stream_name = "AIF Playback",
1088                         .channels_min = 1,
1089                         .channels_max = 4,
1090                         .rates = RT1015_STEREO_RATES,
1091                         .formats = RT1015_FORMATS,
1092                 },
1093                 .ops = &rt1015_aif_dai_ops,
1094         }
1095 };
1096
1097 #ifdef CONFIG_PM
1098 static int rt1015_suspend(struct snd_soc_component *component)
1099 {
1100         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1101
1102         regcache_cache_only(rt1015->regmap, true);
1103         regcache_mark_dirty(rt1015->regmap);
1104
1105         return 0;
1106 }
1107
1108 static int rt1015_resume(struct snd_soc_component *component)
1109 {
1110         struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1111
1112         regcache_cache_only(rt1015->regmap, false);
1113         regcache_sync(rt1015->regmap);
1114         return 0;
1115 }
1116 #else
1117 #define rt1015_suspend NULL
1118 #define rt1015_resume NULL
1119 #endif
1120
1121 static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
1122         .probe = rt1015_probe,
1123         .remove = rt1015_remove,
1124         .suspend = rt1015_suspend,
1125         .resume = rt1015_resume,
1126         .controls = rt1015_snd_controls,
1127         .num_controls = ARRAY_SIZE(rt1015_snd_controls),
1128         .dapm_widgets = rt1015_dapm_widgets,
1129         .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
1130         .dapm_routes = rt1015_dapm_routes,
1131         .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
1132         .set_sysclk = rt1015_set_component_sysclk,
1133         .set_pll = rt1015_set_component_pll,
1134         .use_pmdown_time        = 1,
1135         .endianness             = 1,
1136         .non_legacy_dai_naming  = 1,
1137 };
1138
1139 static const struct regmap_config rt1015_regmap = {
1140         .reg_bits = 16,
1141         .val_bits = 16,
1142         .max_register = RT1015_S_BST_TIMING_INTER36,
1143         .volatile_reg = rt1015_volatile_register,
1144         .readable_reg = rt1015_readable_register,
1145         .cache_type = REGCACHE_RBTREE,
1146         .reg_defaults = rt1015_reg,
1147         .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
1148 };
1149
1150 static const struct i2c_device_id rt1015_i2c_id[] = {
1151         { "rt1015", 0 },
1152         { }
1153 };
1154 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
1155
1156 #if defined(CONFIG_OF)
1157 static const struct of_device_id rt1015_of_match[] = {
1158         { .compatible = "realtek,rt1015", },
1159         {},
1160 };
1161 MODULE_DEVICE_TABLE(of, rt1015_of_match);
1162 #endif
1163
1164 #ifdef CONFIG_ACPI
1165 static struct acpi_device_id rt1015_acpi_match[] = {
1166         {"10EC1015", 0,},
1167         {},
1168 };
1169 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1170 #endif
1171
1172 static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
1173 {
1174         device_property_read_u32(dev, "realtek,power-up-delay-ms",
1175                 &rt1015->pdata.power_up_delay_ms);
1176 }
1177
1178 static int rt1015_i2c_probe(struct i2c_client *i2c,
1179         const struct i2c_device_id *id)
1180 {
1181         struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev);
1182         struct rt1015_priv *rt1015;
1183         int ret;
1184         unsigned int val;
1185
1186         rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv),
1187                                 GFP_KERNEL);
1188         if (rt1015 == NULL)
1189                 return -ENOMEM;
1190
1191         i2c_set_clientdata(i2c, rt1015);
1192
1193         rt1015->pdata = i2s_default_platform_data;
1194
1195         if (pdata)
1196                 rt1015->pdata = *pdata;
1197         else
1198                 rt1015_parse_dt(rt1015, &i2c->dev);
1199
1200         rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1201         if (IS_ERR(rt1015->regmap)) {
1202                 ret = PTR_ERR(rt1015->regmap);
1203                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1204                         ret);
1205                 return ret;
1206         }
1207
1208         rt1015->hw_config = (i2c->addr == 0x29) ? RT1015_HW_29 : RT1015_HW_28;
1209
1210         ret = regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
1211         if (ret) {
1212                 dev_err(&i2c->dev,
1213                         "Failed to read device register: %d\n", ret);
1214                 return ret;
1215         } else if ((val != RT1015_DEVICE_ID_VAL) &&
1216                         (val != RT1015_DEVICE_ID_VAL2)) {
1217                 dev_err(&i2c->dev,
1218                         "Device with ID register %x is not rt1015\n", val);
1219                 return -ENODEV;
1220         }
1221
1222         return devm_snd_soc_register_component(&i2c->dev,
1223                 &soc_component_dev_rt1015,
1224                 rt1015_dai, ARRAY_SIZE(rt1015_dai));
1225 }
1226
1227 static void rt1015_i2c_shutdown(struct i2c_client *client)
1228 {
1229         struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1230
1231         regmap_write(rt1015->regmap, RT1015_RESET, 0);
1232 }
1233
1234 static struct i2c_driver rt1015_i2c_driver = {
1235         .driver = {
1236                 .name = "rt1015",
1237                 .of_match_table = of_match_ptr(rt1015_of_match),
1238                 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1239         },
1240         .probe = rt1015_i2c_probe,
1241         .shutdown = rt1015_i2c_shutdown,
1242         .id_table = rt1015_i2c_id,
1243 };
1244 module_i2c_driver(rt1015_i2c_driver);
1245
1246 MODULE_DESCRIPTION("ASoC RT1015 driver");
1247 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1248 MODULE_LICENSE("GPL v2");