1 // SPDX-License-Identifier: GPL-2.0
2 // TLV320ADCX140 Sound driver
3 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 #include <linux/module.h>
6 #include <linux/moduleparam.h>
7 #include <linux/init.h>
8 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/acpi.h>
15 #include <linux/of_gpio.h>
16 #include <linux/slab.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/initval.h>
22 #include <sound/tlv.h>
24 #include "tlv320adcx140.h"
27 struct snd_soc_component
*component
;
28 struct regulator
*supply_areg
;
29 struct gpio_desc
*gpio_reset
;
30 struct regmap
*regmap
;
36 unsigned int tdm_delay
;
37 unsigned int slot_width
;
40 static const char * const gpo_config_names
[] = {
47 static const struct reg_default adcx140_reg_defaults
[] = {
48 { ADCX140_PAGE_SELECT
, 0x00 },
49 { ADCX140_SW_RESET
, 0x00 },
50 { ADCX140_SLEEP_CFG
, 0x00 },
51 { ADCX140_SHDN_CFG
, 0x05 },
52 { ADCX140_ASI_CFG0
, 0x30 },
53 { ADCX140_ASI_CFG1
, 0x00 },
54 { ADCX140_ASI_CFG2
, 0x00 },
55 { ADCX140_ASI_CH1
, 0x00 },
56 { ADCX140_ASI_CH2
, 0x01 },
57 { ADCX140_ASI_CH3
, 0x02 },
58 { ADCX140_ASI_CH4
, 0x03 },
59 { ADCX140_ASI_CH5
, 0x04 },
60 { ADCX140_ASI_CH6
, 0x05 },
61 { ADCX140_ASI_CH7
, 0x06 },
62 { ADCX140_ASI_CH8
, 0x07 },
63 { ADCX140_MST_CFG0
, 0x02 },
64 { ADCX140_MST_CFG1
, 0x48 },
65 { ADCX140_ASI_STS
, 0xff },
66 { ADCX140_CLK_SRC
, 0x10 },
67 { ADCX140_PDMCLK_CFG
, 0x40 },
68 { ADCX140_PDM_CFG
, 0x00 },
69 { ADCX140_GPIO_CFG0
, 0x22 },
70 { ADCX140_GPO_CFG0
, 0x00 },
71 { ADCX140_GPO_CFG1
, 0x00 },
72 { ADCX140_GPO_CFG2
, 0x00 },
73 { ADCX140_GPO_CFG3
, 0x00 },
74 { ADCX140_GPO_VAL
, 0x00 },
75 { ADCX140_GPIO_MON
, 0x00 },
76 { ADCX140_GPI_CFG0
, 0x00 },
77 { ADCX140_GPI_CFG1
, 0x00 },
78 { ADCX140_GPI_MON
, 0x00 },
79 { ADCX140_INT_CFG
, 0x00 },
80 { ADCX140_INT_MASK0
, 0xff },
81 { ADCX140_INT_LTCH0
, 0x00 },
82 { ADCX140_BIAS_CFG
, 0x00 },
83 { ADCX140_CH1_CFG0
, 0x00 },
84 { ADCX140_CH1_CFG1
, 0x00 },
85 { ADCX140_CH1_CFG2
, 0xc9 },
86 { ADCX140_CH1_CFG3
, 0x80 },
87 { ADCX140_CH1_CFG4
, 0x00 },
88 { ADCX140_CH2_CFG0
, 0x00 },
89 { ADCX140_CH2_CFG1
, 0x00 },
90 { ADCX140_CH2_CFG2
, 0xc9 },
91 { ADCX140_CH2_CFG3
, 0x80 },
92 { ADCX140_CH2_CFG4
, 0x00 },
93 { ADCX140_CH3_CFG0
, 0x00 },
94 { ADCX140_CH3_CFG1
, 0x00 },
95 { ADCX140_CH3_CFG2
, 0xc9 },
96 { ADCX140_CH3_CFG3
, 0x80 },
97 { ADCX140_CH3_CFG4
, 0x00 },
98 { ADCX140_CH4_CFG0
, 0x00 },
99 { ADCX140_CH4_CFG1
, 0x00 },
100 { ADCX140_CH4_CFG2
, 0xc9 },
101 { ADCX140_CH4_CFG3
, 0x80 },
102 { ADCX140_CH4_CFG4
, 0x00 },
103 { ADCX140_CH5_CFG2
, 0xc9 },
104 { ADCX140_CH5_CFG3
, 0x80 },
105 { ADCX140_CH5_CFG4
, 0x00 },
106 { ADCX140_CH6_CFG2
, 0xc9 },
107 { ADCX140_CH6_CFG3
, 0x80 },
108 { ADCX140_CH6_CFG4
, 0x00 },
109 { ADCX140_CH7_CFG2
, 0xc9 },
110 { ADCX140_CH7_CFG3
, 0x80 },
111 { ADCX140_CH7_CFG4
, 0x00 },
112 { ADCX140_CH8_CFG2
, 0xc9 },
113 { ADCX140_CH8_CFG3
, 0x80 },
114 { ADCX140_CH8_CFG4
, 0x00 },
115 { ADCX140_DSP_CFG0
, 0x01 },
116 { ADCX140_DSP_CFG1
, 0x40 },
117 { ADCX140_DRE_CFG0
, 0x7b },
118 { ADCX140_AGC_CFG0
, 0xe7 },
119 { ADCX140_IN_CH_EN
, 0xf0 },
120 { ADCX140_ASI_OUT_CH_EN
, 0x00 },
121 { ADCX140_PWR_CFG
, 0x00 },
122 { ADCX140_DEV_STS0
, 0x00 },
123 { ADCX140_DEV_STS1
, 0x80 },
126 static const struct regmap_range_cfg adcx140_ranges
[] = {
129 .range_max
= 12 * 128,
130 .selector_reg
= ADCX140_PAGE_SELECT
,
131 .selector_mask
= 0xff,
138 static bool adcx140_volatile(struct device
*dev
, unsigned int reg
)
141 case ADCX140_SW_RESET
:
142 case ADCX140_DEV_STS0
:
143 case ADCX140_DEV_STS1
:
144 case ADCX140_ASI_STS
:
151 static const struct regmap_config adcx140_i2c_regmap
= {
154 .reg_defaults
= adcx140_reg_defaults
,
155 .num_reg_defaults
= ARRAY_SIZE(adcx140_reg_defaults
),
156 .cache_type
= REGCACHE_FLAT
,
157 .ranges
= adcx140_ranges
,
158 .num_ranges
= ARRAY_SIZE(adcx140_ranges
),
159 .max_register
= 12 * 128,
160 .volatile_reg
= adcx140_volatile
,
163 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
164 static DECLARE_TLV_DB_SCALE(dig_vol_tlv
, -10050, 50, 0);
166 /* ADC gain. From 0 to 42 dB in 1 dB steps */
167 static DECLARE_TLV_DB_SCALE(adc_tlv
, 0, 100, 0);
169 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
170 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv
, -6600, 100, 0);
171 /* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */
172 static DECLARE_TLV_DB_SCALE(dre_gain_tlv
, 200, 200, 0);
174 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
175 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv
, -3600, 200, 0);
176 /* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */
177 static DECLARE_TLV_DB_SCALE(agc_gain_tlv
, 300, 300, 0);
179 static const char * const decimation_filter_text
[] = {
180 "Linear Phase", "Low Latency", "Ultra-low Latency"
183 static SOC_ENUM_SINGLE_DECL(decimation_filter_enum
, ADCX140_DSP_CFG0
, 4,
184 decimation_filter_text
);
186 static const struct snd_kcontrol_new decimation_filter_controls
[] = {
187 SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum
),
190 static const char * const pdmclk_text
[] = {
191 "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
194 static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum
, ADCX140_PDMCLK_CFG
, 0,
197 static const struct snd_kcontrol_new pdmclk_div_controls
[] = {
198 SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum
),
201 static const char * const resistor_text
[] = {
202 "2.5 kOhm", "10 kOhm", "20 kOhm"
205 static SOC_ENUM_SINGLE_DECL(in1_resistor_enum
, ADCX140_CH1_CFG0
, 2,
207 static SOC_ENUM_SINGLE_DECL(in2_resistor_enum
, ADCX140_CH2_CFG0
, 2,
209 static SOC_ENUM_SINGLE_DECL(in3_resistor_enum
, ADCX140_CH3_CFG0
, 2,
211 static SOC_ENUM_SINGLE_DECL(in4_resistor_enum
, ADCX140_CH4_CFG0
, 2,
214 static const struct snd_kcontrol_new in1_resistor_controls
[] = {
215 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum
),
217 static const struct snd_kcontrol_new in2_resistor_controls
[] = {
218 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum
),
220 static const struct snd_kcontrol_new in3_resistor_controls
[] = {
221 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum
),
223 static const struct snd_kcontrol_new in4_resistor_controls
[] = {
224 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum
),
227 /* Analog/Digital Selection */
228 static const char * const adcx140_mic_sel_text
[] = {"Analog", "Line In", "Digital"};
229 static const char * const adcx140_analog_sel_text
[] = {"Analog", "Line In"};
231 static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum
,
233 adcx140_mic_sel_text
);
235 static const struct snd_kcontrol_new adcx140_dapm_mic1p_control
=
236 SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum
);
238 static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum
,
240 adcx140_analog_sel_text
);
242 static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control
=
243 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum
);
245 static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum
,
247 adcx140_mic_sel_text
);
249 static const struct snd_kcontrol_new adcx140_dapm_mic1m_control
=
250 SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum
);
252 static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum
,
254 adcx140_mic_sel_text
);
256 static const struct snd_kcontrol_new adcx140_dapm_mic2p_control
=
257 SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum
);
259 static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum
,
261 adcx140_analog_sel_text
);
263 static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control
=
264 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum
);
266 static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum
,
268 adcx140_mic_sel_text
);
270 static const struct snd_kcontrol_new adcx140_dapm_mic2m_control
=
271 SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum
);
273 static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum
,
275 adcx140_mic_sel_text
);
277 static const struct snd_kcontrol_new adcx140_dapm_mic3p_control
=
278 SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum
);
280 static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum
,
282 adcx140_analog_sel_text
);
284 static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control
=
285 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum
);
287 static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum
,
289 adcx140_mic_sel_text
);
291 static const struct snd_kcontrol_new adcx140_dapm_mic3m_control
=
292 SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum
);
294 static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum
,
296 adcx140_mic_sel_text
);
298 static const struct snd_kcontrol_new adcx140_dapm_mic4p_control
=
299 SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum
);
301 static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum
,
303 adcx140_analog_sel_text
);
305 static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control
=
306 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum
);
308 static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum
,
310 adcx140_mic_sel_text
);
312 static const struct snd_kcontrol_new adcx140_dapm_mic4m_control
=
313 SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum
);
315 static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch
=
316 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN
, 7, 1, 0);
317 static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch
=
318 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN
, 6, 1, 0);
319 static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch
=
320 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN
, 5, 1, 0);
321 static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch
=
322 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN
, 4, 1, 0);
323 static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch
=
324 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN
, 3, 1, 0);
325 static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch
=
326 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN
, 2, 1, 0);
327 static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch
=
328 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN
, 1, 1, 0);
329 static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch
=
330 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN
, 0, 1, 0);
332 static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch
=
333 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0
, 0, 1, 0);
334 static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch
=
335 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0
, 0, 1, 0);
336 static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch
=
337 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0
, 0, 1, 0);
338 static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch
=
339 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0
, 0, 1, 0);
341 static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch
=
342 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1
, 3, 1, 0);
345 static const struct snd_kcontrol_new adcx140_output_mixer_controls
[] = {
346 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
347 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
348 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
349 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
352 static const struct snd_soc_dapm_widget adcx140_dapm_widgets
[] = {
353 /* Analog Differential Inputs */
354 SND_SOC_DAPM_INPUT("MIC1P"),
355 SND_SOC_DAPM_INPUT("MIC1M"),
356 SND_SOC_DAPM_INPUT("MIC2P"),
357 SND_SOC_DAPM_INPUT("MIC2M"),
358 SND_SOC_DAPM_INPUT("MIC3P"),
359 SND_SOC_DAPM_INPUT("MIC3M"),
360 SND_SOC_DAPM_INPUT("MIC4P"),
361 SND_SOC_DAPM_INPUT("MIC4M"),
363 SND_SOC_DAPM_OUTPUT("CH1_OUT"),
364 SND_SOC_DAPM_OUTPUT("CH2_OUT"),
365 SND_SOC_DAPM_OUTPUT("CH3_OUT"),
366 SND_SOC_DAPM_OUTPUT("CH4_OUT"),
367 SND_SOC_DAPM_OUTPUT("CH5_OUT"),
368 SND_SOC_DAPM_OUTPUT("CH6_OUT"),
369 SND_SOC_DAPM_OUTPUT("CH7_OUT"),
370 SND_SOC_DAPM_OUTPUT("CH8_OUT"),
372 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM
, 0, 0,
373 &adcx140_output_mixer_controls
[0],
374 ARRAY_SIZE(adcx140_output_mixer_controls
)),
376 /* Input Selection to MIC_PGA */
377 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM
, 0, 0,
378 &adcx140_dapm_mic1p_control
),
379 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM
, 0, 0,
380 &adcx140_dapm_mic2p_control
),
381 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM
, 0, 0,
382 &adcx140_dapm_mic3p_control
),
383 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM
, 0, 0,
384 &adcx140_dapm_mic4p_control
),
386 /* Input Selection to MIC_PGA */
387 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM
, 0, 0,
388 &adcx140_dapm_mic1_analog_control
),
389 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM
, 0, 0,
390 &adcx140_dapm_mic2_analog_control
),
391 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM
, 0, 0,
392 &adcx140_dapm_mic3_analog_control
),
393 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM
, 0, 0,
394 &adcx140_dapm_mic4_analog_control
),
396 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM
, 0, 0,
397 &adcx140_dapm_mic1m_control
),
398 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM
, 0, 0,
399 &adcx140_dapm_mic2m_control
),
400 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM
, 0, 0,
401 &adcx140_dapm_mic3m_control
),
402 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM
, 0, 0,
403 &adcx140_dapm_mic4m_control
),
405 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM
, 0, 0, NULL
, 0),
406 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM
, 0, 0, NULL
, 0),
407 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM
, 0, 0, NULL
, 0),
408 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM
, 0, 0, NULL
, 0),
410 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN
, 7, 0),
411 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN
, 6, 0),
412 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN
, 5, 0),
413 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN
, 4, 0),
415 SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN
, 7, 0),
416 SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN
, 6, 0),
417 SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN
, 5, 0),
418 SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN
, 4, 0),
419 SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN
, 3, 0),
420 SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN
, 2, 0),
421 SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN
, 1, 0),
422 SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN
, 0, 0),
425 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM
, 0, 0,
426 &adcx140_dapm_ch1_en_switch
),
427 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM
, 0, 0,
428 &adcx140_dapm_ch2_en_switch
),
429 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM
, 0, 0,
430 &adcx140_dapm_ch3_en_switch
),
431 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM
, 0, 0,
432 &adcx140_dapm_ch4_en_switch
),
434 SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM
, 0, 0,
435 &adcx140_dapm_ch5_en_switch
),
436 SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM
, 0, 0,
437 &adcx140_dapm_ch6_en_switch
),
438 SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM
, 0, 0,
439 &adcx140_dapm_ch7_en_switch
),
440 SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM
, 0, 0,
441 &adcx140_dapm_ch8_en_switch
),
443 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM
, 0, 0,
444 &adcx140_dapm_dre_en_switch
),
446 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM
, 0, 0,
447 &adcx140_dapm_ch1_dre_en_switch
),
448 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM
, 0, 0,
449 &adcx140_dapm_ch2_dre_en_switch
),
450 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM
, 0, 0,
451 &adcx140_dapm_ch3_dre_en_switch
),
452 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM
, 0, 0,
453 &adcx140_dapm_ch4_dre_en_switch
),
455 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM
, 0, 0,
456 in1_resistor_controls
),
457 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM
, 0, 0,
458 in2_resistor_controls
),
459 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM
, 0, 0,
460 in3_resistor_controls
),
461 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM
, 0, 0,
462 in4_resistor_controls
),
464 SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM
, 0, 0,
465 pdmclk_div_controls
),
467 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM
, 0, 0,
468 decimation_filter_controls
),
471 static const struct snd_soc_dapm_route adcx140_audio_map
[] = {
473 {"CH1_OUT", NULL
, "Output Mixer"},
474 {"CH2_OUT", NULL
, "Output Mixer"},
475 {"CH3_OUT", NULL
, "Output Mixer"},
476 {"CH4_OUT", NULL
, "Output Mixer"},
478 {"CH1_ASI_EN", "Switch", "CH1_ADC"},
479 {"CH2_ASI_EN", "Switch", "CH2_ADC"},
480 {"CH3_ASI_EN", "Switch", "CH3_ADC"},
481 {"CH4_ASI_EN", "Switch", "CH4_ADC"},
483 {"CH1_ASI_EN", "Switch", "CH1_DIG"},
484 {"CH2_ASI_EN", "Switch", "CH2_DIG"},
485 {"CH3_ASI_EN", "Switch", "CH3_DIG"},
486 {"CH4_ASI_EN", "Switch", "CH4_DIG"},
487 {"CH5_ASI_EN", "Switch", "CH5_DIG"},
488 {"CH6_ASI_EN", "Switch", "CH6_DIG"},
489 {"CH7_ASI_EN", "Switch", "CH7_DIG"},
490 {"CH8_ASI_EN", "Switch", "CH8_DIG"},
492 {"CH5_ASI_EN", "Switch", "CH5_OUT"},
493 {"CH6_ASI_EN", "Switch", "CH6_OUT"},
494 {"CH7_ASI_EN", "Switch", "CH7_OUT"},
495 {"CH8_ASI_EN", "Switch", "CH8_OUT"},
497 {"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
498 {"Decimation Filter", "Low Latency", "DRE_ENABLE"},
499 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
501 {"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
502 {"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
503 {"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
504 {"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
506 {"CH1_DRE_EN", "Switch", "CH1_ADC"},
507 {"CH2_DRE_EN", "Switch", "CH2_ADC"},
508 {"CH3_DRE_EN", "Switch", "CH3_ADC"},
509 {"CH4_DRE_EN", "Switch", "CH4_ADC"},
512 {"CH1_ADC", NULL
, "MIC_GAIN_CTL_CH1"},
513 {"CH2_ADC", NULL
, "MIC_GAIN_CTL_CH2"},
514 {"CH3_ADC", NULL
, "MIC_GAIN_CTL_CH3"},
515 {"CH4_ADC", NULL
, "MIC_GAIN_CTL_CH4"},
517 {"MIC_GAIN_CTL_CH1", NULL
, "IN1 Analog Mic Resistor"},
518 {"MIC_GAIN_CTL_CH1", NULL
, "IN1 Analog Mic Resistor"},
519 {"MIC_GAIN_CTL_CH2", NULL
, "IN2 Analog Mic Resistor"},
520 {"MIC_GAIN_CTL_CH2", NULL
, "IN2 Analog Mic Resistor"},
521 {"MIC_GAIN_CTL_CH3", NULL
, "IN3 Analog Mic Resistor"},
522 {"MIC_GAIN_CTL_CH3", NULL
, "IN3 Analog Mic Resistor"},
523 {"MIC_GAIN_CTL_CH4", NULL
, "IN4 Analog Mic Resistor"},
524 {"MIC_GAIN_CTL_CH4", NULL
, "IN4 Analog Mic Resistor"},
526 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
527 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
528 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
530 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
531 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
532 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
534 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
535 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
536 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
538 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
539 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
540 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
542 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
543 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
544 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
546 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
547 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
548 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
550 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
551 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
552 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
554 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
555 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
556 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
558 {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
559 {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
560 {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
561 {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
563 {"MIC1P Input Mux", NULL
, "CH1_DIG"},
564 {"MIC1M Input Mux", NULL
, "CH2_DIG"},
565 {"MIC2P Input Mux", NULL
, "CH3_DIG"},
566 {"MIC2M Input Mux", NULL
, "CH4_DIG"},
567 {"MIC3P Input Mux", NULL
, "CH5_DIG"},
568 {"MIC3M Input Mux", NULL
, "CH6_DIG"},
569 {"MIC4P Input Mux", NULL
, "CH7_DIG"},
570 {"MIC4M Input Mux", NULL
, "CH8_DIG"},
572 {"MIC1 Analog Mux", "Line In", "MIC1P"},
573 {"MIC2 Analog Mux", "Line In", "MIC2P"},
574 {"MIC3 Analog Mux", "Line In", "MIC3P"},
575 {"MIC4 Analog Mux", "Line In", "MIC4P"},
577 {"MIC1P Input Mux", "Analog", "MIC1P"},
578 {"MIC1M Input Mux", "Analog", "MIC1M"},
579 {"MIC2P Input Mux", "Analog", "MIC2P"},
580 {"MIC2M Input Mux", "Analog", "MIC2M"},
581 {"MIC3P Input Mux", "Analog", "MIC3P"},
582 {"MIC3M Input Mux", "Analog", "MIC3M"},
583 {"MIC4P Input Mux", "Analog", "MIC4P"},
584 {"MIC4M Input Mux", "Analog", "MIC4M"},
586 {"MIC1P Input Mux", "Digital", "MIC1P"},
587 {"MIC1M Input Mux", "Digital", "MIC1M"},
588 {"MIC2P Input Mux", "Digital", "MIC2P"},
589 {"MIC2M Input Mux", "Digital", "MIC2M"},
590 {"MIC3P Input Mux", "Digital", "MIC3P"},
591 {"MIC3M Input Mux", "Digital", "MIC3M"},
592 {"MIC4P Input Mux", "Digital", "MIC4P"},
593 {"MIC4M Input Mux", "Digital", "MIC4M"},
596 static const struct snd_kcontrol_new adcx140_snd_controls
[] = {
597 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1
, 2, 42, 0,
599 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1
, 2, 42, 0,
601 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1
, 2, 42, 0,
603 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1
, 2, 42, 0,
606 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0
, 4, 9, 0,
608 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0
, 0, 12, 0,
611 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0
, 4, 15, 0,
613 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0
, 0, 13, 0,
616 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2
,
617 0, 0xff, 0, dig_vol_tlv
),
618 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2
,
619 0, 0xff, 0, dig_vol_tlv
),
620 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2
,
621 0, 0xff, 0, dig_vol_tlv
),
622 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2
,
623 0, 0xff, 0, dig_vol_tlv
),
624 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2
,
625 0, 0xff, 0, dig_vol_tlv
),
626 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2
,
627 0, 0xff, 0, dig_vol_tlv
),
628 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2
,
629 0, 0xff, 0, dig_vol_tlv
),
630 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2
,
631 0, 0xff, 0, dig_vol_tlv
),
634 static int adcx140_reset(struct adcx140_priv
*adcx140
)
638 if (adcx140
->gpio_reset
) {
639 gpiod_direction_output(adcx140
->gpio_reset
, 0);
640 /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */
641 usleep_range(30000, 100000);
642 gpiod_direction_output(adcx140
->gpio_reset
, 1);
644 ret
= regmap_write(adcx140
->regmap
, ADCX140_SW_RESET
,
648 /* 8.4.2: wait >= 10 ms after entering sleep mode. */
649 usleep_range(10000, 100000);
654 static void adcx140_pwr_ctrl(struct adcx140_priv
*adcx140
, bool power_state
)
659 pwr_ctrl
= ADCX140_PWR_CFG_ADC_PDZ
| ADCX140_PWR_CFG_PLL_PDZ
;
661 if (adcx140
->micbias_vg
&& power_state
)
662 pwr_ctrl
|= ADCX140_PWR_CFG_BIAS_PDZ
;
664 regmap_update_bits(adcx140
->regmap
, ADCX140_PWR_CFG
,
665 ADCX140_PWR_CTRL_MSK
, pwr_ctrl
);
668 static int adcx140_hw_params(struct snd_pcm_substream
*substream
,
669 struct snd_pcm_hw_params
*params
,
670 struct snd_soc_dai
*dai
)
672 struct snd_soc_component
*component
= dai
->component
;
673 struct adcx140_priv
*adcx140
= snd_soc_component_get_drvdata(component
);
676 switch (params_width(params
)) {
678 data
= ADCX140_16_BIT_WORD
;
681 data
= ADCX140_20_BIT_WORD
;
684 data
= ADCX140_24_BIT_WORD
;
687 data
= ADCX140_32_BIT_WORD
;
690 dev_err(component
->dev
, "%s: Unsupported width %d\n",
691 __func__
, params_width(params
));
695 adcx140_pwr_ctrl(adcx140
, false);
697 snd_soc_component_update_bits(component
, ADCX140_ASI_CFG0
,
698 ADCX140_WORD_LEN_MSK
, data
);
700 adcx140_pwr_ctrl(adcx140
, true);
705 static int adcx140_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
708 struct snd_soc_component
*component
= codec_dai
->component
;
709 struct adcx140_priv
*adcx140
= snd_soc_component_get_drvdata(component
);
713 bool inverted_bclk
= false;
715 /* set master/slave audio interface */
716 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
717 case SND_SOC_DAIFMT_CBM_CFM
:
718 iface_reg2
|= ADCX140_BCLK_FSYNC_MASTER
;
720 case SND_SOC_DAIFMT_CBS_CFS
:
722 case SND_SOC_DAIFMT_CBS_CFM
:
723 case SND_SOC_DAIFMT_CBM_CFS
:
725 dev_err(component
->dev
, "Invalid DAI master/slave interface\n");
729 /* interface format */
730 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
731 case SND_SOC_DAIFMT_I2S
:
732 iface_reg1
|= ADCX140_I2S_MODE_BIT
;
734 case SND_SOC_DAIFMT_LEFT_J
:
735 iface_reg1
|= ADCX140_LEFT_JUST_BIT
;
737 case SND_SOC_DAIFMT_DSP_A
:
739 inverted_bclk
= true;
741 case SND_SOC_DAIFMT_DSP_B
:
742 inverted_bclk
= true;
745 dev_err(component
->dev
, "Invalid DAI interface format\n");
749 /* signal polarity */
750 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
751 case SND_SOC_DAIFMT_IB_NF
:
752 case SND_SOC_DAIFMT_IB_IF
:
753 inverted_bclk
= !inverted_bclk
;
755 case SND_SOC_DAIFMT_NB_IF
:
756 iface_reg1
|= ADCX140_FSYNCINV_BIT
;
758 case SND_SOC_DAIFMT_NB_NF
:
761 dev_err(component
->dev
, "Invalid DAI clock signal polarity\n");
766 iface_reg1
|= ADCX140_BCLKINV_BIT
;
768 adcx140
->dai_fmt
= fmt
& SND_SOC_DAIFMT_FORMAT_MASK
;
770 adcx140_pwr_ctrl(adcx140
, false);
772 snd_soc_component_update_bits(component
, ADCX140_ASI_CFG0
,
773 ADCX140_FSYNCINV_BIT
|
774 ADCX140_BCLKINV_BIT
|
775 ADCX140_ASI_FORMAT_MSK
,
777 snd_soc_component_update_bits(component
, ADCX140_MST_CFG0
,
778 ADCX140_BCLK_FSYNC_MASTER
, iface_reg2
);
780 /* Configure data offset */
781 snd_soc_component_update_bits(component
, ADCX140_ASI_CFG1
,
782 ADCX140_TX_OFFSET_MASK
, offset
);
784 adcx140_pwr_ctrl(adcx140
, true);
789 static int adcx140_set_dai_tdm_slot(struct snd_soc_dai
*codec_dai
,
790 unsigned int tx_mask
, unsigned int rx_mask
,
791 int slots
, int slot_width
)
793 struct snd_soc_component
*component
= codec_dai
->component
;
794 struct adcx140_priv
*adcx140
= snd_soc_component_get_drvdata(component
);
797 /* TDM based on DSP mode requires slots to be adjacent */
798 lsb
= __ffs(tx_mask
);
799 if ((lsb
+ 1) != __fls(tx_mask
)) {
800 dev_err(component
->dev
, "Invalid mask, slots must be adjacent\n");
804 switch (slot_width
) {
811 dev_err(component
->dev
, "Unsupported slot width %d\n", slot_width
);
815 adcx140
->tdm_delay
= lsb
;
816 adcx140
->slot_width
= slot_width
;
821 static const struct snd_soc_dai_ops adcx140_dai_ops
= {
822 .hw_params
= adcx140_hw_params
,
823 .set_fmt
= adcx140_set_dai_fmt
,
824 .set_tdm_slot
= adcx140_set_dai_tdm_slot
,
827 static int adcx140_configure_gpo(struct adcx140_priv
*adcx140
)
829 u32 gpo_outputs
[ADCX140_NUM_GPOS
];
830 u32 gpo_output_val
= 0;
834 for (i
= 0; i
< ADCX140_NUM_GPOS
; i
++) {
835 ret
= device_property_read_u32_array(adcx140
->dev
,
838 ADCX140_NUM_GPO_CFGS
);
842 if (gpo_outputs
[0] > ADCX140_GPO_CFG_MAX
) {
843 dev_err(adcx140
->dev
, "GPO%d config out of range\n", i
+ 1);
847 if (gpo_outputs
[1] > ADCX140_GPO_DRV_MAX
) {
848 dev_err(adcx140
->dev
, "GPO%d drive out of range\n", i
+ 1);
852 gpo_output_val
= gpo_outputs
[0] << ADCX140_GPO_SHIFT
|
854 ret
= regmap_write(adcx140
->regmap
, ADCX140_GPO_CFG0
+ i
,
864 static int adcx140_configure_gpio(struct adcx140_priv
*adcx140
)
867 u32 gpio_outputs
[ADCX140_NUM_GPIO_CFGS
];
868 u32 gpio_output_val
= 0;
871 gpio_count
= device_property_count_u32(adcx140
->dev
,
876 if (gpio_count
!= ADCX140_NUM_GPIO_CFGS
)
879 ret
= device_property_read_u32_array(adcx140
->dev
, "ti,gpio-config",
880 gpio_outputs
, gpio_count
);
884 if (gpio_outputs
[0] > ADCX140_GPIO_CFG_MAX
) {
885 dev_err(adcx140
->dev
, "GPIO config out of range\n");
889 if (gpio_outputs
[1] > ADCX140_GPIO_DRV_MAX
) {
890 dev_err(adcx140
->dev
, "GPIO drive out of range\n");
894 gpio_output_val
= gpio_outputs
[0] << ADCX140_GPIO_SHIFT
897 return regmap_write(adcx140
->regmap
, ADCX140_GPIO_CFG0
, gpio_output_val
);
900 static int adcx140_codec_probe(struct snd_soc_component
*component
)
902 struct adcx140_priv
*adcx140
= snd_soc_component_get_drvdata(component
);
903 int sleep_cfg_val
= ADCX140_WAKE_DEV
;
908 u32 pdm_edges
[ADCX140_NUM_PDM_EDGES
];
909 u32 pdm_edge_val
= 0;
911 u32 gpi_inputs
[ADCX140_NUM_GPI_PINS
];
912 u32 gpi_input_val
= 0;
917 ret
= device_property_read_u32(adcx140
->dev
, "ti,mic-bias-source",
919 if (ret
|| bias_source
> ADCX140_MIC_BIAS_VAL_AVDD
) {
920 bias_source
= ADCX140_MIC_BIAS_VAL_VREF
;
921 adcx140
->micbias_vg
= false;
923 adcx140
->micbias_vg
= true;
926 ret
= device_property_read_u32(adcx140
->dev
, "ti,vref-source",
929 vref_source
= ADCX140_MIC_BIAS_VREF_275V
;
931 if (vref_source
> ADCX140_MIC_BIAS_VREF_1375V
) {
932 dev_err(adcx140
->dev
, "Mic Bias source value is invalid\n");
936 bias_cfg
= bias_source
<< ADCX140_MIC_BIAS_SHIFT
| vref_source
;
938 ret
= adcx140_reset(adcx140
);
942 if (adcx140
->supply_areg
== NULL
)
943 sleep_cfg_val
|= ADCX140_AREG_INTERNAL
;
945 ret
= regmap_write(adcx140
->regmap
, ADCX140_SLEEP_CFG
, sleep_cfg_val
);
947 dev_err(adcx140
->dev
, "setting sleep config failed %d\n", ret
);
951 /* 8.4.3: Wait >= 1ms after entering active mode. */
952 usleep_range(1000, 100000);
954 pdm_count
= device_property_count_u32(adcx140
->dev
,
955 "ti,pdm-edge-select");
956 if (pdm_count
<= ADCX140_NUM_PDM_EDGES
&& pdm_count
> 0) {
957 ret
= device_property_read_u32_array(adcx140
->dev
,
958 "ti,pdm-edge-select",
959 pdm_edges
, pdm_count
);
963 for (i
= 0; i
< pdm_count
; i
++)
964 pdm_edge_val
|= pdm_edges
[i
] << (ADCX140_PDM_EDGE_SHIFT
- i
);
966 ret
= regmap_write(adcx140
->regmap
, ADCX140_PDM_CFG
,
972 gpi_count
= device_property_count_u32(adcx140
->dev
, "ti,gpi-config");
973 if (gpi_count
<= ADCX140_NUM_GPI_PINS
&& gpi_count
> 0) {
974 ret
= device_property_read_u32_array(adcx140
->dev
,
976 gpi_inputs
, gpi_count
);
980 gpi_input_val
= gpi_inputs
[ADCX140_GPI1_INDEX
] << ADCX140_GPI_SHIFT
|
981 gpi_inputs
[ADCX140_GPI2_INDEX
];
983 ret
= regmap_write(adcx140
->regmap
, ADCX140_GPI_CFG0
,
988 gpi_input_val
= gpi_inputs
[ADCX140_GPI3_INDEX
] << ADCX140_GPI_SHIFT
|
989 gpi_inputs
[ADCX140_GPI4_INDEX
];
991 ret
= regmap_write(adcx140
->regmap
, ADCX140_GPI_CFG1
,
997 ret
= adcx140_configure_gpio(adcx140
);
1001 ret
= adcx140_configure_gpo(adcx140
);
1005 ret
= regmap_update_bits(adcx140
->regmap
, ADCX140_BIAS_CFG
,
1006 ADCX140_MIC_BIAS_VAL_MSK
|
1007 ADCX140_MIC_BIAS_VREF_MSK
, bias_cfg
);
1009 dev_err(adcx140
->dev
, "setting MIC bias failed %d\n", ret
);
1011 tx_high_z
= device_property_read_bool(adcx140
->dev
, "ti,asi-tx-drive");
1013 ret
= regmap_update_bits(adcx140
->regmap
, ADCX140_ASI_CFG0
,
1014 ADCX140_TX_FILL
, ADCX140_TX_FILL
);
1016 dev_err(adcx140
->dev
, "Setting Tx drive failed %d\n", ret
);
1021 adcx140_pwr_ctrl(adcx140
, true);
1026 static int adcx140_set_bias_level(struct snd_soc_component
*component
,
1027 enum snd_soc_bias_level level
)
1029 struct adcx140_priv
*adcx140
= snd_soc_component_get_drvdata(component
);
1032 case SND_SOC_BIAS_ON
:
1033 case SND_SOC_BIAS_PREPARE
:
1034 case SND_SOC_BIAS_STANDBY
:
1035 adcx140_pwr_ctrl(adcx140
, true);
1037 case SND_SOC_BIAS_OFF
:
1038 adcx140_pwr_ctrl(adcx140
, false);
1045 static const struct snd_soc_component_driver soc_codec_driver_adcx140
= {
1046 .probe
= adcx140_codec_probe
,
1047 .set_bias_level
= adcx140_set_bias_level
,
1048 .controls
= adcx140_snd_controls
,
1049 .num_controls
= ARRAY_SIZE(adcx140_snd_controls
),
1050 .dapm_widgets
= adcx140_dapm_widgets
,
1051 .num_dapm_widgets
= ARRAY_SIZE(adcx140_dapm_widgets
),
1052 .dapm_routes
= adcx140_audio_map
,
1053 .num_dapm_routes
= ARRAY_SIZE(adcx140_audio_map
),
1054 .suspend_bias_off
= 1,
1056 .use_pmdown_time
= 1,
1058 .non_legacy_dai_naming
= 1,
1061 static struct snd_soc_dai_driver adcx140_dai_driver
[] = {
1063 .name
= "tlv320adcx140-codec",
1065 .stream_name
= "Capture",
1067 .channels_max
= ADCX140_MAX_CHANNELS
,
1068 .rates
= ADCX140_RATES
,
1069 .formats
= ADCX140_FORMATS
,
1071 .ops
= &adcx140_dai_ops
,
1072 .symmetric_rates
= 1,
1077 static const struct of_device_id tlv320adcx140_of_match
[] = {
1078 { .compatible
= "ti,tlv320adc3140" },
1079 { .compatible
= "ti,tlv320adc5140" },
1080 { .compatible
= "ti,tlv320adc6140" },
1083 MODULE_DEVICE_TABLE(of
, tlv320adcx140_of_match
);
1086 static int adcx140_i2c_probe(struct i2c_client
*i2c
,
1087 const struct i2c_device_id
*id
)
1089 struct adcx140_priv
*adcx140
;
1092 adcx140
= devm_kzalloc(&i2c
->dev
, sizeof(*adcx140
), GFP_KERNEL
);
1096 adcx140
->dev
= &i2c
->dev
;
1098 adcx140
->gpio_reset
= devm_gpiod_get_optional(adcx140
->dev
,
1099 "reset", GPIOD_OUT_LOW
);
1100 if (IS_ERR(adcx140
->gpio_reset
))
1101 dev_info(&i2c
->dev
, "Reset GPIO not defined\n");
1103 adcx140
->supply_areg
= devm_regulator_get_optional(adcx140
->dev
,
1105 if (IS_ERR(adcx140
->supply_areg
)) {
1106 if (PTR_ERR(adcx140
->supply_areg
) == -EPROBE_DEFER
)
1107 return -EPROBE_DEFER
;
1109 adcx140
->supply_areg
= NULL
;
1111 ret
= regulator_enable(adcx140
->supply_areg
);
1113 dev_err(adcx140
->dev
, "Failed to enable areg\n");
1118 adcx140
->regmap
= devm_regmap_init_i2c(i2c
, &adcx140_i2c_regmap
);
1119 if (IS_ERR(adcx140
->regmap
)) {
1120 ret
= PTR_ERR(adcx140
->regmap
);
1121 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
1126 i2c_set_clientdata(i2c
, adcx140
);
1128 return devm_snd_soc_register_component(&i2c
->dev
,
1129 &soc_codec_driver_adcx140
,
1130 adcx140_dai_driver
, 1);
1133 static const struct i2c_device_id adcx140_i2c_id
[] = {
1134 { "tlv320adc3140", 0 },
1135 { "tlv320adc5140", 1 },
1136 { "tlv320adc6140", 2 },
1139 MODULE_DEVICE_TABLE(i2c
, adcx140_i2c_id
);
1141 static struct i2c_driver adcx140_i2c_driver
= {
1143 .name
= "tlv320adcx140-codec",
1144 .of_match_table
= of_match_ptr(tlv320adcx140_of_match
),
1146 .probe
= adcx140_i2c_probe
,
1147 .id_table
= adcx140_i2c_id
,
1149 module_i2c_driver(adcx140_i2c_driver
);
1151 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1152 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
1153 MODULE_LICENSE("GPL v2");