sound/soc/mediatek/mt8183/mt8183-dai-adda.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // MediaTek ALSA SoC Audio DAI ADDA Control
   4 //
   5 // Copyright (c) 2018 MediaTek Inc.
   6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
   7
   8 #include <linux/regmap.h>
   9 #include <linux/delay.h>
  10 #include "mt8183-afe-common.h"
  11 #include "mt8183-interconnection.h"
  12 #include "mt8183-reg.h"
  13
  14 enum {
  15         AUDIO_SDM_LEVEL_MUTE = 0,
  16         AUDIO_SDM_LEVEL_NORMAL = 0x1d,
  17         /* if you change level normal */
  18         /* you need to change formula of hp impedance and dc trim too */
  19 };
  20
  21 enum {
  22         DELAY_DATA_MISO1 = 0,
  23         DELAY_DATA_MISO2,
  24 };
  25
  26 enum {
  27         MTK_AFE_ADDA_DL_RATE_8K = 0,
  28         MTK_AFE_ADDA_DL_RATE_11K = 1,
  29         MTK_AFE_ADDA_DL_RATE_12K = 2,
  30         MTK_AFE_ADDA_DL_RATE_16K = 3,
  31         MTK_AFE_ADDA_DL_RATE_22K = 4,
  32         MTK_AFE_ADDA_DL_RATE_24K = 5,
  33         MTK_AFE_ADDA_DL_RATE_32K = 6,
  34         MTK_AFE_ADDA_DL_RATE_44K = 7,
  35         MTK_AFE_ADDA_DL_RATE_48K = 8,
  36         MTK_AFE_ADDA_DL_RATE_96K = 9,
  37         MTK_AFE_ADDA_DL_RATE_192K = 10,
  38 };
  39
  40 enum {
  41         MTK_AFE_ADDA_UL_RATE_8K = 0,
  42         MTK_AFE_ADDA_UL_RATE_16K = 1,
  43         MTK_AFE_ADDA_UL_RATE_32K = 2,
  44         MTK_AFE_ADDA_UL_RATE_48K = 3,
  45         MTK_AFE_ADDA_UL_RATE_96K = 4,
  46         MTK_AFE_ADDA_UL_RATE_192K = 5,
  47         MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
  48 };
  49
  50 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
  51                                            unsigned int rate)
  52 {
  53         switch (rate) {
  54         case 8000:
  55                 return MTK_AFE_ADDA_DL_RATE_8K;
  56         case 11025:
  57                 return MTK_AFE_ADDA_DL_RATE_11K;
  58         case 12000:
  59                 return MTK_AFE_ADDA_DL_RATE_12K;
  60         case 16000:
  61                 return MTK_AFE_ADDA_DL_RATE_16K;
  62         case 22050:
  63                 return MTK_AFE_ADDA_DL_RATE_22K;
  64         case 24000:
  65                 return MTK_AFE_ADDA_DL_RATE_24K;
  66         case 32000:
  67                 return MTK_AFE_ADDA_DL_RATE_32K;
  68         case 44100:
  69                 return MTK_AFE_ADDA_DL_RATE_44K;
  70         case 48000:
  71                 return MTK_AFE_ADDA_DL_RATE_48K;
  72         case 96000:
  73                 return MTK_AFE_ADDA_DL_RATE_96K;
  74         case 192000:
  75                 return MTK_AFE_ADDA_DL_RATE_192K;
  76         default:
  77                 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
  78                          __func__, rate);
  79                 return MTK_AFE_ADDA_DL_RATE_48K;
  80         }
  81 }
  82
  83 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
  84                                            unsigned int rate)
  85 {
  86         switch (rate) {
  87         case 8000:
  88                 return MTK_AFE_ADDA_UL_RATE_8K;
  89         case 16000:
  90                 return MTK_AFE_ADDA_UL_RATE_16K;
  91         case 32000:
  92                 return MTK_AFE_ADDA_UL_RATE_32K;
  93         case 48000:
  94                 return MTK_AFE_ADDA_UL_RATE_48K;
  95         case 96000:
  96                 return MTK_AFE_ADDA_UL_RATE_96K;
  97         case 192000:
  98                 return MTK_AFE_ADDA_UL_RATE_192K;
  99         default:
 100                 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
 101                          __func__, rate);
 102                 return MTK_AFE_ADDA_UL_RATE_48K;
 103         }
 104 }
 105
 106 /* dai component */
 107 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
 108         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
 109         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
 110         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
 111         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
 112                                     I_ADDA_UL_CH2, 1, 0),
 113         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
 114                                     I_ADDA_UL_CH1, 1, 0),
 115         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
 116                                     I_PCM_1_CAP_CH1, 1, 0),
 117         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
 118                                     I_PCM_2_CAP_CH1, 1, 0),
 119 };
 120
 121 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
 122         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
 123         SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
 124         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
 125         SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
 126         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
 127         SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
 128         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
 129                                     I_ADDA_UL_CH2, 1, 0),
 130         SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
 131                                     I_ADDA_UL_CH1, 1, 0),
 132         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
 133                                     I_PCM_1_CAP_CH1, 1, 0),
 134         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
 135                                     I_PCM_2_CAP_CH1, 1, 0),
 136         SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
 137                                     I_PCM_1_CAP_CH2, 1, 0),
 138         SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
 139                                     I_PCM_2_CAP_CH2, 1, 0),
 140 };
 141
 142 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
 143                              struct snd_kcontrol *kcontrol,
 144                              int event)
 145 {
 146         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 147         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 148         struct mt8183_afe_private *afe_priv = afe->platform_priv;
 149
 150         dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
 151                 __func__, w->name, event);
 152
 153         switch (event) {
 154         case SND_SOC_DAPM_PRE_PMU:
 155                 /* update setting to dmic */
 156                 if (afe_priv->mtkaif_dmic) {
 157                         /* mtkaif_rxif_data_mode = 1, dmic */
 158                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
 159                                            0x1, 0x1);
 160
 161                         /* dmic mode, 3.25M*/
 162                         regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
 163                                            0x0, 0xf << 20);
 164                         regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
 165                                            0x0, 0x1 << 5);
 166                         regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
 167                                            0x0, 0x3 << 14);
 168
 169                         /* turn on dmic, ch1, ch2 */
 170                         regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
 171                                            0x1 << 1, 0x1 << 1);
 172                         regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
 173                                            0x3 << 21, 0x3 << 21);
 174                 }
 175                 break;
 176         case SND_SOC_DAPM_POST_PMD:
 177                 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
 178                 usleep_range(125, 135);
 179                 break;
 180         default:
 181                 break;
 182         }
 183
 184         return 0;
 185 }
 186
 187 /* mtkaif dmic */
 188 static const char * const mt8183_adda_off_on_str[] = {
 189         "Off", "On"
 190 };
 191
 192 static const struct soc_enum mt8183_adda_enum[] = {
 193         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_adda_off_on_str),
 194                             mt8183_adda_off_on_str),
 195 };
 196
 197 static int mt8183_adda_dmic_get(struct snd_kcontrol *kcontrol,
 198                                 struct snd_ctl_elem_value *ucontrol)
 199 {
 200         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 201         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 202         struct mt8183_afe_private *afe_priv = afe->platform_priv;
 203
 204         ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
 205
 206         return 0;
 207 }
 208
 209 static int mt8183_adda_dmic_set(struct snd_kcontrol *kcontrol,
 210                                 struct snd_ctl_elem_value *ucontrol)
 211 {
 212         struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
 213         struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
 214         struct mt8183_afe_private *afe_priv = afe->platform_priv;
 215         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 216
 217         if (ucontrol->value.enumerated.item[0] >= e->items)
 218                 return -EINVAL;
 219
 220         afe_priv->mtkaif_dmic = ucontrol->value.integer.value[0];
 221
 222         dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_dmic %d\n",
 223                  __func__, kcontrol->id.name, afe_priv->mtkaif_dmic);
 224
 225         return 0;
 226 }
 227
 228 static const struct snd_kcontrol_new mtk_adda_controls[] = {
 229         SOC_ENUM_EXT("MTKAIF_DMIC", mt8183_adda_enum[0],
 230                      mt8183_adda_dmic_get, mt8183_adda_dmic_set),
 231 };
 232
 233 enum {
 234         SUPPLY_SEQ_ADDA_AFE_ON,
 235         SUPPLY_SEQ_ADDA_DL_ON,
 236         SUPPLY_SEQ_ADDA_UL_ON,
 237 };
 238
 239 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
 240         /* adda */
 241         SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
 242                            mtk_adda_dl_ch1_mix,
 243                            ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
 244         SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
 245                            mtk_adda_dl_ch2_mix,
 246                            ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
 247
 248         SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
 249                               AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
 250                               NULL, 0),
 251
 252         SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
 253                               AFE_ADDA_DL_SRC2_CON0,
 254                               DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
 255                               NULL, 0),
 256
 257         SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
 258                               AFE_ADDA_UL_SRC_CON0,
 259                               UL_SRC_ON_TMP_CTL_SFT, 0,
 260                               mtk_adda_ul_event,
 261                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 262
 263         SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
 264         SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
 265         SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
 266         SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
 267 };
 268
 269 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
 270         /* playback */
 271         {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
 272         {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
 273         {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
 274
 275         {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
 276         {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
 277         {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
 278
 279         {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
 280         {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
 281         {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
 282
 283         {"ADDA Playback", NULL, "ADDA_DL_CH1"},
 284         {"ADDA Playback", NULL, "ADDA_DL_CH2"},
 285
 286         /* adda enable */
 287         {"ADDA Playback", NULL, "ADDA Enable"},
 288         {"ADDA Playback", NULL, "ADDA Playback Enable"},
 289         {"ADDA Capture", NULL, "ADDA Enable"},
 290         {"ADDA Capture", NULL, "ADDA Capture Enable"},
 291
 292         /* clk */
 293         {"ADDA Playback", NULL, "mtkaif_26m_clk"},
 294         {"ADDA Playback", NULL, "aud_dac_clk"},
 295         {"ADDA Playback", NULL, "aud_dac_predis_clk"},
 296
 297         {"ADDA Capture", NULL, "mtkaif_26m_clk"},
 298         {"ADDA Capture", NULL, "aud_adc_clk"},
 299 };
 300
 301 static int set_mtkaif_rx(struct mtk_base_afe *afe)
 302 {
 303         struct mt8183_afe_private *afe_priv = afe->platform_priv;
 304         int delay_data;
 305         int delay_cycle;
 306
 307         switch (afe_priv->mtkaif_protocol) {
 308         case MT8183_MTKAIF_PROTOCOL_2_CLK_P2:
 309                 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
 310                 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
 311                 /* mtkaif_rxif_clkinv_adc inverse for calibration */
 312                 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
 313                              0x80010000);
 314
 315                 if (afe_priv->mtkaif_phase_cycle[0] >=
 316                     afe_priv->mtkaif_phase_cycle[1]) {
 317                         delay_data = DELAY_DATA_MISO1;
 318                         delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
 319                                       afe_priv->mtkaif_phase_cycle[1];
 320                 } else {
 321                         delay_data = DELAY_DATA_MISO2;
 322                         delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
 323                                       afe_priv->mtkaif_phase_cycle[0];
 324                 }
 325
 326                 regmap_update_bits(afe->regmap,
 327                                    AFE_ADDA_MTKAIF_RX_CFG2,
 328                                    MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
 329                                    delay_data << MTKAIF_RXIF_DELAY_DATA_SFT);
 330
 331                 regmap_update_bits(afe->regmap,
 332                                    AFE_ADDA_MTKAIF_RX_CFG2,
 333                                    MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
 334                                    delay_cycle << MTKAIF_RXIF_DELAY_CYCLE_SFT);
 335                 break;
 336         case MT8183_MTKAIF_PROTOCOL_2:
 337                 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
 338                 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
 339                              0x00010000);
 340                 break;
 341         case MT8183_MTKAIF_PROTOCOL_1:
 342                 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
 343                 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
 344         default:
 345                 break;
 346         }
 347
 348         return 0;
 349 }
 350
 351 /* dai ops */
 352 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
 353                                   struct snd_pcm_hw_params *params,
 354                                   struct snd_soc_dai *dai)
 355 {
 356         struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 357         unsigned int rate = params_rate(params);
 358
 359         dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
 360                 __func__, dai->id, substream->stream, rate);
 361
 362         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 363                 unsigned int dl_src2_con0 = 0;
 364                 unsigned int dl_src2_con1 = 0;
 365
 366                 /* clean predistortion */
 367                 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
 368                 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
 369
 370                 /* set sampling rate */
 371                 dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
 372
 373                 /* set output mode */
 374                 switch (rate) {
 375                 case 192000:
 376                         dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
 377                         dl_src2_con0 |= 1 << 14;
 378                         break;
 379                 case 96000:
 380                         dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
 381                         dl_src2_con0 |= 1 << 14;
 382                         break;
 383                 default:
 384                         dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
 385                         break;
 386                 }
 387
 388                 /* turn off mute function */
 389                 dl_src2_con0 |= (0x03 << 11);
 390
 391                 /* set voice input data if input sample rate is 8k or 16k */
 392                 if (rate == 8000 || rate == 16000)
 393                         dl_src2_con0 |= 0x01 << 5;
 394
 395                 /* SA suggest apply -0.3db to audio/speech path */
 396                 dl_src2_con1 = 0xf74f0000;
 397
 398                 /* turn on down-link gain */
 399                 dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
 400
 401                 regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
 402                 regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
 403
 404                 /* set sdm gain */
 405                 regmap_update_bits(afe->regmap,
 406                                    AFE_ADDA_DL_SDM_DCCOMP_CON,
 407                                    ATTGAIN_CTL_MASK_SFT,
 408                                    AUDIO_SDM_LEVEL_NORMAL << ATTGAIN_CTL_SFT);
 409         } else {
 410                 unsigned int voice_mode = 0;
 411                 unsigned int ul_src_con0 = 0;   /* default value */
 412
 413                 /* set mtkaif protocol */
 414                 set_mtkaif_rx(afe);
 415
 416                 /* Using Internal ADC */
 417                 regmap_update_bits(afe->regmap,
 418                                    AFE_ADDA_TOP_CON0,
 419                                    0x1 << 0,
 420                                    0x0 << 0);
 421
 422                 voice_mode = adda_ul_rate_transform(afe, rate);
 423
 424                 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
 425
 426                 /* enable iir */
 427                 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
 428                                UL_IIR_ON_TMP_CTL_MASK_SFT;
 429
 430                 /* 35Hz @ 48k */
 431                 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_02_01, 0x00000000);
 432                 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
 433                 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
 434                 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
 435                 regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
 436
 437                 regmap_write(afe->regmap, AFE_ADDA_UL_SRC_CON0, ul_src_con0);
 438
 439                 /* mtkaif_rxif_data_mode = 0, amic */
 440                 regmap_update_bits(afe->regmap,
 441                                    AFE_ADDA_MTKAIF_RX_CFG0,
 442                                    0x1 << 0,
 443                                    0x0 << 0);
 444         }
 445
 446         return 0;
 447 }
 448
 449 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
 450         .hw_params = mtk_dai_adda_hw_params,
 451 };
 452
 453 /* dai driver */
 454 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
 455                                  SNDRV_PCM_RATE_96000 |\
 456                                  SNDRV_PCM_RATE_192000)
 457
 458 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
 459                                 SNDRV_PCM_RATE_16000 |\
 460                                 SNDRV_PCM_RATE_32000 |\
 461                                 SNDRV_PCM_RATE_48000)
 462
 463 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 464                           SNDRV_PCM_FMTBIT_S24_LE |\
 465                           SNDRV_PCM_FMTBIT_S32_LE)
 466
 467 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
 468         {
 469                 .name = "ADDA",
 470                 .id = MT8183_DAI_ADDA,
 471                 .playback = {
 472                         .stream_name = "ADDA Playback",
 473                         .channels_min = 1,
 474                         .channels_max = 2,
 475                         .rates = MTK_ADDA_PLAYBACK_RATES,
 476                         .formats = MTK_ADDA_FORMATS,
 477                 },
 478                 .capture = {
 479                         .stream_name = "ADDA Capture",
 480                         .channels_min = 1,
 481                         .channels_max = 2,
 482                         .rates = MTK_ADDA_CAPTURE_RATES,
 483                         .formats = MTK_ADDA_FORMATS,
 484                 },
 485                 .ops = &mtk_dai_adda_ops,
 486         },
 487 };
 488
 489 int mt8183_dai_adda_register(struct mtk_base_afe *afe)
 490 {
 491         struct mtk_base_afe_dai *dai;
 492
 493         dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
 494         if (!dai)
 495                 return -ENOMEM;
 496
 497         list_add(&dai->list, &afe->sub_dais);
 498
 499         dai->dai_drivers = mtk_dai_adda_driver;
 500         dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
 501
 502         dai->controls = mtk_adda_controls;
 503         dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
 504         dai->dapm_widgets = mtk_dai_adda_widgets;
 505         dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
 506         dai->dapm_routes = mtk_dai_adda_routes;
 507         dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
 508         return 0;
 509 }