?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
WIP FPC-III support
[linux/fpc-iii.git] / sound / soc / mediatek / mt8192 / mt8192-dai-adda.c
blobf040dce85da537b41faf1b503debfd3a17f86064
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // MediaTek ALSA SoC Audio DAI ADDA Control
4 //
5 // Copyright (c) 2020 MediaTek Inc.
6 // Author: Shane Chien <shane.chien@mediatek.com>
7 //
8
9 #include <linux/delay.h>
10 #include <linux/regmap.h>
11
12 #include "mt8192-afe-clk.h"
13 #include "mt8192-afe-common.h"
14 #include "mt8192-afe-gpio.h"
15 #include "mt8192-interconnection.h"
16
17 enum {
18 UL_IIR_SW = 0,
19 UL_IIR_5HZ,
20 UL_IIR_10HZ,
21 UL_IIR_25HZ,
22 UL_IIR_50HZ,
23 UL_IIR_75HZ,
24 };
25
26 enum {
27 AUDIO_SDM_LEVEL_MUTE = 0,
28 AUDIO_SDM_LEVEL_NORMAL = 0x1d,
29 /* if you change level normal */
30 /* you need to change formula of hp impedance and dc trim too */
31 };
32
33 enum {
34 AUDIO_SDM_2ND = 0,
35 AUDIO_SDM_3RD,
36 };
37
38 enum {
39 DELAY_DATA_MISO1 = 0,
40 DELAY_DATA_MISO2,
41 };
42
43 enum {
44 MTK_AFE_ADDA_DL_RATE_8K = 0,
45 MTK_AFE_ADDA_DL_RATE_11K = 1,
46 MTK_AFE_ADDA_DL_RATE_12K = 2,
47 MTK_AFE_ADDA_DL_RATE_16K = 3,
48 MTK_AFE_ADDA_DL_RATE_22K = 4,
49 MTK_AFE_ADDA_DL_RATE_24K = 5,
50 MTK_AFE_ADDA_DL_RATE_32K = 6,
51 MTK_AFE_ADDA_DL_RATE_44K = 7,
52 MTK_AFE_ADDA_DL_RATE_48K = 8,
53 MTK_AFE_ADDA_DL_RATE_96K = 9,
54 MTK_AFE_ADDA_DL_RATE_192K = 10,
55 };
56
57 enum {
58 MTK_AFE_ADDA_UL_RATE_8K = 0,
59 MTK_AFE_ADDA_UL_RATE_16K = 1,
60 MTK_AFE_ADDA_UL_RATE_32K = 2,
61 MTK_AFE_ADDA_UL_RATE_48K = 3,
62 MTK_AFE_ADDA_UL_RATE_96K = 4,
63 MTK_AFE_ADDA_UL_RATE_192K = 5,
64 MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
65 };
66
67 #define SDM_AUTO_RESET_THRESHOLD 0x190000
68
69 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
70 unsigned int rate)
71 {
72 switch (rate) {
73 case 8000:
74 return MTK_AFE_ADDA_DL_RATE_8K;
75 case 11025:
76 return MTK_AFE_ADDA_DL_RATE_11K;
77 case 12000:
78 return MTK_AFE_ADDA_DL_RATE_12K;
79 case 16000:
80 return MTK_AFE_ADDA_DL_RATE_16K;
81 case 22050:
82 return MTK_AFE_ADDA_DL_RATE_22K;
83 case 24000:
84 return MTK_AFE_ADDA_DL_RATE_24K;
85 case 32000:
86 return MTK_AFE_ADDA_DL_RATE_32K;
87 case 44100:
88 return MTK_AFE_ADDA_DL_RATE_44K;
89 case 48000:
90 return MTK_AFE_ADDA_DL_RATE_48K;
91 case 96000:
92 return MTK_AFE_ADDA_DL_RATE_96K;
93 case 192000:
94 return MTK_AFE_ADDA_DL_RATE_192K;
95 default:
96 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
97 __func__, rate);
98 return MTK_AFE_ADDA_DL_RATE_48K;
99 }
100 }
101
102 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
103 unsigned int rate)
104 {
105 switch (rate) {
106 case 8000:
107 return MTK_AFE_ADDA_UL_RATE_8K;
108 case 16000:
109 return MTK_AFE_ADDA_UL_RATE_16K;
110 case 32000:
111 return MTK_AFE_ADDA_UL_RATE_32K;
112 case 48000:
113 return MTK_AFE_ADDA_UL_RATE_48K;
114 case 96000:
115 return MTK_AFE_ADDA_UL_RATE_96K;
116 case 192000:
117 return MTK_AFE_ADDA_UL_RATE_192K;
118 default:
119 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
120 __func__, rate);
121 return MTK_AFE_ADDA_UL_RATE_48K;
122 }
123 }
124
125 /* dai component */
126 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
127 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
128 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN3, I_DL12_CH1, 1, 0),
129 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
130 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
131 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN3_1, I_DL4_CH1, 1, 0),
132 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN3_1, I_DL5_CH1, 1, 0),
133 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN3_1, I_DL6_CH1, 1, 0),
134 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN3_1, I_DL8_CH1, 1, 0),
135 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN3,
136 I_ADDA_UL_CH3, 1, 0),
137 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
138 I_ADDA_UL_CH2, 1, 0),
139 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
140 I_ADDA_UL_CH1, 1, 0),
141 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN3,
142 I_GAIN1_OUT_CH1, 1, 0),
143 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
144 I_PCM_1_CAP_CH1, 1, 0),
145 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
146 I_PCM_2_CAP_CH1, 1, 0),
147 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN3_1,
148 I_SRC_1_OUT_CH1, 1, 0),
149 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1", AFE_CONN3_1,
150 I_SRC_2_OUT_CH1, 1, 0),
151 };
152
153 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
154 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
155 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
156 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN4, I_DL12_CH2, 1, 0),
157 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
158 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
159 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
160 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
161 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN4_1, I_DL4_CH2, 1, 0),
162 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN4_1, I_DL5_CH2, 1, 0),
163 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN4_1, I_DL6_CH2, 1, 0),
164 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN4_1, I_DL8_CH2, 1, 0),
165 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN4,
166 I_ADDA_UL_CH3, 1, 0),
167 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
168 I_ADDA_UL_CH2, 1, 0),
169 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
170 I_ADDA_UL_CH1, 1, 0),
171 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN4,
172 I_GAIN1_OUT_CH2, 1, 0),
173 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
174 I_PCM_1_CAP_CH1, 1, 0),
175 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
176 I_PCM_2_CAP_CH1, 1, 0),
177 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
178 I_PCM_1_CAP_CH2, 1, 0),
179 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
180 I_PCM_2_CAP_CH2, 1, 0),
181 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN4_1,
182 I_SRC_1_OUT_CH2, 1, 0),
183 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2", AFE_CONN4_1,
184 I_SRC_2_OUT_CH2, 1, 0),
185 };
186
187 static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = {
188 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN52, I_DL1_CH1, 1, 0),
189 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN52, I_DL12_CH1, 1, 0),
190 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN52, I_DL2_CH1, 1, 0),
191 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN52, I_DL3_CH1, 1, 0),
192 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN52_1, I_DL4_CH1, 1, 0),
193 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN52_1, I_DL5_CH1, 1, 0),
194 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN52_1, I_DL6_CH1, 1, 0),
195 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN52,
196 I_ADDA_UL_CH3, 1, 0),
197 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN52,
198 I_ADDA_UL_CH2, 1, 0),
199 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN52,
200 I_ADDA_UL_CH1, 1, 0),
201 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN52,
202 I_GAIN1_OUT_CH1, 1, 0),
203 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN52,
204 I_PCM_1_CAP_CH1, 1, 0),
205 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN52,
206 I_PCM_2_CAP_CH1, 1, 0),
207 };
208
209 static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = {
210 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN53, I_DL1_CH1, 1, 0),
211 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN53, I_DL1_CH2, 1, 0),
212 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN53, I_DL12_CH2, 1, 0),
213 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN53, I_DL2_CH1, 1, 0),
214 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN53, I_DL2_CH2, 1, 0),
215 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN53, I_DL3_CH1, 1, 0),
216 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN53, I_DL3_CH2, 1, 0),
217 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN53_1, I_DL4_CH2, 1, 0),
218 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN53_1, I_DL5_CH2, 1, 0),
219 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN53_1, I_DL6_CH1, 1, 0),
220 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN53,
221 I_ADDA_UL_CH3, 1, 0),
222 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN53,
223 I_ADDA_UL_CH2, 1, 0),
224 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN53,
225 I_ADDA_UL_CH1, 1, 0),
226 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN53,
227 I_GAIN1_OUT_CH2, 1, 0),
228 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN53,
229 I_PCM_1_CAP_CH1, 1, 0),
230 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN53,
231 I_PCM_2_CAP_CH1, 1, 0),
232 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN53,
233 I_PCM_1_CAP_CH2, 1, 0),
234 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN53,
235 I_PCM_2_CAP_CH2, 1, 0),
236 };
237
238 static const struct snd_kcontrol_new mtk_stf_ch1_mix[] = {
239 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN19,
240 I_ADDA_UL_CH1, 1, 0),
241 };
242
243 static const struct snd_kcontrol_new mtk_stf_ch2_mix[] = {
244 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN20,
245 I_ADDA_UL_CH2, 1, 0),
246 };
247
248 enum {
249 SUPPLY_SEQ_ADDA_AFE_ON,
250 SUPPLY_SEQ_ADDA_DL_ON,
251 SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
252 SUPPLY_SEQ_ADDA_MTKAIF_CFG,
253 SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
254 SUPPLY_SEQ_ADDA_FIFO,
255 SUPPLY_SEQ_ADDA_AP_DMIC,
256 SUPPLY_SEQ_ADDA_UL_ON,
257 };
258
259 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)
260 {
261 unsigned int reg;
262
263 switch (id) {
264 case MT8192_DAI_ADDA:
265 case MT8192_DAI_AP_DMIC:
266 reg = AFE_ADDA_UL_SRC_CON0;
267 break;
268 case MT8192_DAI_ADDA_CH34:
269 case MT8192_DAI_AP_DMIC_CH34:
270 reg = AFE_ADDA6_UL_SRC_CON0;
271 break;
272 default:
273 return -EINVAL;
274 }
275
276 /* dmic mode, 3.25M*/
277 regmap_update_bits(afe->regmap, reg,
278 DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT,
279 0x0);
280 regmap_update_bits(afe->regmap, reg,
281 DMIC_LOW_POWER_MODE_CTL_MASK_SFT,
282 0x0);
283
284 /* turn on dmic, ch1, ch2 */
285 regmap_update_bits(afe->regmap, reg,
286 UL_SDM_3_LEVEL_CTL_MASK_SFT,
287 0x1 << UL_SDM_3_LEVEL_CTL_SFT);
288 regmap_update_bits(afe->regmap, reg,
289 UL_MODE_3P25M_CH1_CTL_MASK_SFT,
290 0x1 << UL_MODE_3P25M_CH1_CTL_SFT);
291 regmap_update_bits(afe->regmap, reg,
292 UL_MODE_3P25M_CH2_CTL_MASK_SFT,
293 0x1 << UL_MODE_3P25M_CH2_CTL_SFT);
294 return 0;
295 }
296
297 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
298 struct snd_kcontrol *kcontrol,
299 int event)
300 {
301 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
302 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
303 struct mt8192_afe_private *afe_priv = afe->platform_priv;
304 int mtkaif_dmic = afe_priv->mtkaif_dmic;
305
306 dev_info(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",
307 __func__, w->name, event, mtkaif_dmic);
308
309 switch (event) {
310 case SND_SOC_DAPM_PRE_PMU:
311 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1);
312
313 /* update setting to dmic */
314 if (mtkaif_dmic) {
315 /* mtkaif_rxif_data_mode = 1, dmic */
316 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
317 0x1, 0x1);
318
319 /* dmic mode, 3.25M*/
320 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
321 MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
322 0x0);
323 mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA);
324 }
325 break;
326 case SND_SOC_DAPM_POST_PMD:
327 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
328 usleep_range(125, 135);
329 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1);
330 break;
331 default:
332 break;
333 }
334
335 return 0;
336 }
337
338 static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w,
339 struct snd_kcontrol *kcontrol,
340 int event)
341 {
342 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
343 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
344 struct mt8192_afe_private *afe_priv = afe->platform_priv;
345 int mtkaif_dmic = afe_priv->mtkaif_dmic_ch34;
346 int mtkaif_adda6_only = afe_priv->mtkaif_adda6_only;
347
348 dev_info(afe->dev,
349 "%s(), name %s, event 0x%x, mtkaif_dmic %d, mtkaif_adda6_only %d\n",
350 __func__, w->name, event, mtkaif_dmic, mtkaif_adda6_only);
351
352 switch (event) {
353 case SND_SOC_DAPM_PRE_PMU:
354 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34,
355 1);
356
357 /* update setting to dmic */
358 if (mtkaif_dmic) {
359 /* mtkaif_rxif_data_mode = 1, dmic */
360 regmap_update_bits(afe->regmap,
361 AFE_ADDA6_MTKAIF_RX_CFG0,
362 0x1, 0x1);
363
364 /* dmic mode, 3.25M*/
365 regmap_update_bits(afe->regmap,
366 AFE_ADDA6_MTKAIF_RX_CFG0,
367 MTKAIF_RXIF_VOICE_MODE_MASK_SFT,
368 0x0);
369 mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA_CH34);
370 }
371
372 /* when using adda6 without adda enabled,
373 * RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT need to be set or
374 * data cannot be received.
375 */
376 if (mtkaif_adda6_only) {
377 regmap_update_bits(afe->regmap,
378 AFE_ADDA_MTKAIF_SYNCWORD_CFG,
379 0x1 << 23, 0x1 << 23);
380 }
381 break;
382 case SND_SOC_DAPM_POST_PMD:
383 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
384 usleep_range(125, 135);
385 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34,
386 1);
387
388 /* reset dmic */
389 afe_priv->mtkaif_dmic_ch34 = 0;
390
391 if (mtkaif_adda6_only) {
392 regmap_update_bits(afe->regmap,
393 AFE_ADDA_MTKAIF_SYNCWORD_CFG,
394 0x1 << 23, 0x0 << 23);
395 }
396 break;
397 default:
398 break;
399 }
400
401 return 0;
402 }
403
404 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,
405 struct snd_kcontrol *kcontrol,
406 int event)
407 {
408 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
409 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
410 struct mt8192_afe_private *afe_priv = afe->platform_priv;
411
412 switch (event) {
413 case SND_SOC_DAPM_PRE_PMU:
414 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)
415 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
416 else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2)
417 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x30);
418 else
419 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x30);
420 break;
421 default:
422 break;
423 }
424
425 return 0;
426 }
427
428 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,
429 struct snd_kcontrol *kcontrol,
430 int event)
431 {
432 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
433 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
434 struct mt8192_afe_private *afe_priv = afe->platform_priv;
435 int delay_data;
436 int delay_cycle;
437
438 switch (event) {
439 case SND_SOC_DAPM_PRE_PMU:
440 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {
441 /* set protocol 2 */
442 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
443 0x00010000);
444 regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
445 0x00010000);
446
447 if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0 &&
448 (afe_priv->mtkaif_chosen_phase[0] < 0 ||
449 afe_priv->mtkaif_chosen_phase[1] < 0)) {
450 dev_warn(afe->dev,
451 "%s(), mtkaif_chosen_phase[0/1]:%d/%d\n",
452 __func__,
453 afe_priv->mtkaif_chosen_phase[0],
454 afe_priv->mtkaif_chosen_phase[1]);
455 break;
456 } else if (strcmp(w->name, "ADDA6_MTKAIF_CFG") == 0 &&
457 afe_priv->mtkaif_chosen_phase[2] < 0) {
458 dev_warn(afe->dev,
459 "%s(), mtkaif_chosen_phase[2]:%d\n",
460 __func__,
461 afe_priv->mtkaif_chosen_phase[2]);
462 break;
463 }
464
465 /* mtkaif_rxif_clkinv_adc inverse for calibration */
466 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
467 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
468 0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
469 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
470 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,
471 0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT);
472
473 /* set delay for ch12 */
474 if (afe_priv->mtkaif_phase_cycle[0] >=
475 afe_priv->mtkaif_phase_cycle[1]) {
476 delay_data = DELAY_DATA_MISO1;
477 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
478 afe_priv->mtkaif_phase_cycle[1];
479 } else {
480 delay_data = DELAY_DATA_MISO2;
481 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
482 afe_priv->mtkaif_phase_cycle[0];
483 }
484
485 regmap_update_bits(afe->regmap,
486 AFE_ADDA_MTKAIF_RX_CFG2,
487 MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
488 delay_data <<
489 MTKAIF_RXIF_DELAY_DATA_SFT);
490
491 regmap_update_bits(afe->regmap,
492 AFE_ADDA_MTKAIF_RX_CFG2,
493 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
494 delay_cycle <<
495 MTKAIF_RXIF_DELAY_CYCLE_SFT);
496
497 /* set delay between ch3 and ch2 */
498 if (afe_priv->mtkaif_phase_cycle[2] >=
499 afe_priv->mtkaif_phase_cycle[1]) {
500 delay_data = DELAY_DATA_MISO1; /* ch3 */
501 delay_cycle = afe_priv->mtkaif_phase_cycle[2] -
502 afe_priv->mtkaif_phase_cycle[1];
503 } else {
504 delay_data = DELAY_DATA_MISO2; /* ch2 */
505 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
506 afe_priv->mtkaif_phase_cycle[2];
507 }
508
509 regmap_update_bits(afe->regmap,
510 AFE_ADDA6_MTKAIF_RX_CFG2,
511 MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
512 delay_data <<
513 MTKAIF_RXIF_DELAY_DATA_SFT);
514 regmap_update_bits(afe->regmap,
515 AFE_ADDA6_MTKAIF_RX_CFG2,
516 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
517 delay_cycle <<
518 MTKAIF_RXIF_DELAY_CYCLE_SFT);
519 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {
520 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
521 0x00010000);
522 regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0,
523 0x00010000);
524 } else {
525 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
526 regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 0x0);
527 }
528 break;
529 default:
530 break;
531 }
532
533 return 0;
534 }
535
536 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,
537 struct snd_kcontrol *kcontrol,
538 int event)
539 {
540 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
541 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
542
543 dev_info(afe->dev, "%s(), name %s, event 0x%x\n",
544 __func__, w->name, event);
545
546 switch (event) {
547 case SND_SOC_DAPM_PRE_PMU:
548 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0);
549 break;
550 case SND_SOC_DAPM_POST_PMD:
551 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
552 usleep_range(125, 135);
553 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0);
554 break;
555 default:
556 break;
557 }
558
559 return 0;
560 }
561
562 static int mtk_adda_ch34_dl_event(struct snd_soc_dapm_widget *w,
563 struct snd_kcontrol *kcontrol,
564 int event)
565 {
566 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
567 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
568
569 dev_info(afe->dev, "%s(), name %s, event 0x%x\n",
570 __func__, w->name, event);
571
572 switch (event) {
573 case SND_SOC_DAPM_PRE_PMU:
574 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34,
575 0);
576 break;
577 case SND_SOC_DAPM_POST_PMD:
578 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
579 usleep_range(125, 135);
580 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34,
581 0);
582 break;
583 default:
584 break;
585 }
586
587 return 0;
588 }
589
590 /* stf */
591 static int stf_positive_gain_get(struct snd_kcontrol *kcontrol,
592 struct snd_ctl_elem_value *ucontrol)
593 {
594 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
595 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
596 struct mt8192_afe_private *afe_priv = afe->platform_priv;
597
598 ucontrol->value.integer.value[0] = afe_priv->stf_positive_gain_db;
599 return 0;
600 }
601
602 static int stf_positive_gain_set(struct snd_kcontrol *kcontrol,
603 struct snd_ctl_elem_value *ucontrol)
604 {
605 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
606 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
607 struct mt8192_afe_private *afe_priv = afe->platform_priv;
608 int gain_db = ucontrol->value.integer.value[0];
609
610 afe_priv->stf_positive_gain_db = gain_db;
611
612 if (gain_db >= 0 && gain_db <= 24) {
613 regmap_update_bits(afe->regmap,
614 AFE_SIDETONE_GAIN,
615 POSITIVE_GAIN_MASK_SFT,
616 (gain_db / 6) << POSITIVE_GAIN_SFT);
617 } else {
618 dev_warn(afe->dev, "%s(), gain_db %d invalid\n",
619 __func__, gain_db);
620 }
621 return 0;
622 }
623
624 static int mt8192_adda_dmic_get(struct snd_kcontrol *kcontrol,
625 struct snd_ctl_elem_value *ucontrol)
626 {
627 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
628 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
629 struct mt8192_afe_private *afe_priv = afe->platform_priv;
630
631 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
632 return 0;
633 }
634
635 static int mt8192_adda_dmic_set(struct snd_kcontrol *kcontrol,
636 struct snd_ctl_elem_value *ucontrol)
637 {
638 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
639 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
640 struct mt8192_afe_private *afe_priv = afe->platform_priv;
641 int dmic_on;
642
643 dmic_on = ucontrol->value.integer.value[0];
644
645 dev_info(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",
646 __func__, kcontrol->id.name, dmic_on);
647
648 afe_priv->mtkaif_dmic = dmic_on;
649 afe_priv->mtkaif_dmic_ch34 = dmic_on;
650 return 0;
651 }
652
653 static int mt8192_adda6_only_get(struct snd_kcontrol *kcontrol,
654 struct snd_ctl_elem_value *ucontrol)
655 {
656 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
657 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
658 struct mt8192_afe_private *afe_priv = afe->platform_priv;
659
660 ucontrol->value.integer.value[0] = afe_priv->mtkaif_adda6_only;
661 return 0;
662 }
663
664 static int mt8192_adda6_only_set(struct snd_kcontrol *kcontrol,
665 struct snd_ctl_elem_value *ucontrol)
666 {
667 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
668 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
669 struct mt8192_afe_private *afe_priv = afe->platform_priv;
670 int mtkaif_adda6_only;
671
672 mtkaif_adda6_only = ucontrol->value.integer.value[0];
673
674 dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_adda6_only %d\n",
675 __func__, kcontrol->id.name, mtkaif_adda6_only);
676
677 afe_priv->mtkaif_adda6_only = mtkaif_adda6_only;
678 return 0;
679 }
680
681 static const struct snd_kcontrol_new mtk_adda_controls[] = {
682 SOC_SINGLE("Sidetone_Gain", AFE_SIDETONE_GAIN,
683 SIDE_TONE_GAIN_SFT, SIDE_TONE_GAIN_MASK, 0),
684 SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 100, 0,
685 stf_positive_gain_get, stf_positive_gain_set),
686 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,
687 DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),
688 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,
689 mt8192_adda_dmic_get, mt8192_adda_dmic_set),
690 SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY Switch", 0,
691 mt8192_adda6_only_get, mt8192_adda6_only_set),
692 };
693
694 static const struct snd_kcontrol_new stf_ctl =
695 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0);
696
697 static const u16 stf_coeff_table_16k[] = {
698 0x049C, 0x09E8, 0x09E0, 0x089C,
699 0xFF54, 0xF488, 0xEAFC, 0xEBAC,
700 0xfA40, 0x17AC, 0x3D1C, 0x6028,
701 0x7538
702 };
703
704 static const u16 stf_coeff_table_32k[] = {
705 0xFE52, 0x0042, 0x00C5, 0x0194,
706 0x029A, 0x03B7, 0x04BF, 0x057D,
707 0x05BE, 0x0555, 0x0426, 0x0230,
708 0xFF92, 0xFC89, 0xF973, 0xF6C6,
709 0xF500, 0xF49D, 0xF603, 0xF970,
710 0xFEF3, 0x065F, 0x0F4F, 0x1928,
711 0x2329, 0x2C80, 0x345E, 0x3A0D,
712 0x3D08
713 };
714
715 static const u16 stf_coeff_table_48k[] = {
716 0x0401, 0xFFB0, 0xFF5A, 0xFECE,
717 0xFE10, 0xFD28, 0xFC21, 0xFB08,
718 0xF9EF, 0xF8E8, 0xF80A, 0xF76C,
719 0xF724, 0xF746, 0xF7E6, 0xF90F,
720 0xFACC, 0xFD1E, 0xFFFF, 0x0364,
721 0x0737, 0x0B62, 0x0FC1, 0x1431,
722 0x188A, 0x1CA4, 0x2056, 0x237D,
723 0x25F9, 0x27B0, 0x2890
724 };
725
726 static int mtk_stf_event(struct snd_soc_dapm_widget *w,
727 struct snd_kcontrol *kcontrol,
728 int event)
729 {
730 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
731 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
732
733 size_t half_tap_num;
734 const u16 *stf_coeff_table;
735 unsigned int ul_rate, reg_value;
736 size_t coef_addr;
737
738 regmap_read(afe->regmap, AFE_ADDA_UL_SRC_CON0, &ul_rate);
739 ul_rate = ul_rate >> UL_VOICE_MODE_CH1_CH2_CTL_SFT;
740 ul_rate = ul_rate & UL_VOICE_MODE_CH1_CH2_CTL_MASK;
741
742 if (ul_rate == MTK_AFE_ADDA_UL_RATE_48K) {
743 half_tap_num = ARRAY_SIZE(stf_coeff_table_48k);
744 stf_coeff_table = stf_coeff_table_48k;
745 } else if (ul_rate == MTK_AFE_ADDA_UL_RATE_32K) {
746 half_tap_num = ARRAY_SIZE(stf_coeff_table_32k);
747 stf_coeff_table = stf_coeff_table_32k;
748 } else {
749 half_tap_num = ARRAY_SIZE(stf_coeff_table_16k);
750 stf_coeff_table = stf_coeff_table_16k;
751 }
752
753 regmap_read(afe->regmap, AFE_SIDETONE_CON1, &reg_value);
754
755 dev_info(afe->dev, "%s(), name %s, event 0x%x, ul_rate 0x%x, AFE_SIDETONE_CON1 0x%x\n",
756 __func__, w->name, event, ul_rate, reg_value);
757
758 switch (event) {
759 case SND_SOC_DAPM_PRE_PMU:
760 /* set side tone gain = 0 */
761 regmap_update_bits(afe->regmap,
762 AFE_SIDETONE_GAIN,
763 SIDE_TONE_GAIN_MASK_SFT,
764 0);
765 regmap_update_bits(afe->regmap,
766 AFE_SIDETONE_GAIN,
767 POSITIVE_GAIN_MASK_SFT,
768 0);
769 /* don't bypass stf */
770 regmap_update_bits(afe->regmap,
771 AFE_SIDETONE_CON1,
772 0x1f << 27,
773 0x0);
774 /* set stf half tap num */
775 regmap_update_bits(afe->regmap,
776 AFE_SIDETONE_CON1,
777 SIDE_TONE_HALF_TAP_NUM_MASK_SFT,
778 half_tap_num << SIDE_TONE_HALF_TAP_NUM_SFT);
779
780 /* set side tone coefficient */
781 regmap_read(afe->regmap, AFE_SIDETONE_CON0, &reg_value);
782 for (coef_addr = 0; coef_addr < half_tap_num; coef_addr++) {
783 bool old_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
784 bool new_w_ready = 0;
785 int try_cnt = 0;
786
787 regmap_update_bits(afe->regmap,
788 AFE_SIDETONE_CON0,
789 0x39FFFFF,
790 (1 << R_W_EN_SFT) |
791 (1 << R_W_SEL_SFT) |
792 (0 << SEL_CH2_SFT) |
793 (coef_addr <<
794 SIDE_TONE_COEFFICIENT_ADDR_SFT) |
795 stf_coeff_table[coef_addr]);
796
797 /* wait until flag write_ready changed */
798 for (try_cnt = 0; try_cnt < 10; try_cnt++) {
799 regmap_read(afe->regmap,
800 AFE_SIDETONE_CON0, &reg_value);
801 new_w_ready = (reg_value >> W_RDY_SFT) & 0x1;
802
803 /* flip => ok */
804 if (new_w_ready == old_w_ready) {
805 udelay(3);
806 if (try_cnt == 9) {
807 dev_warn(afe->dev,
808 "%s(), write coeff not ready",
809 __func__);
810 }
811 } else {
812 break;
813 }
814 }
815 /* need write -> read -> write to write next coeff */
816 regmap_update_bits(afe->regmap,
817 AFE_SIDETONE_CON0,
818 R_W_SEL_MASK_SFT,
819 0x0);
820 }
821 break;
822 case SND_SOC_DAPM_POST_PMD:
823 /* bypass stf */
824 regmap_update_bits(afe->regmap,
825 AFE_SIDETONE_CON1,
826 0x1f << 27,
827 0x1f << 27);
828
829 /* set side tone gain = 0 */
830 regmap_update_bits(afe->regmap,
831 AFE_SIDETONE_GAIN,
832 SIDE_TONE_GAIN_MASK_SFT,
833 0);
834 regmap_update_bits(afe->regmap,
835 AFE_SIDETONE_GAIN,
836 POSITIVE_GAIN_MASK_SFT,
837 0);
838 break;
839 default:
840 break;
841 }
842
843 return 0;
844 }
845
846 /* stf mux */
847 enum {
848 STF_SRC_ADDA_ADDA6 = 0,
849 STF_SRC_O19O20,
850 };
851
852 static const char *const stf_o19o20_mux_map[] = {
853 "ADDA_ADDA6",
854 "O19O20",
855 };
856
857 static int stf_o19o20_mux_map_value[] = {
858 STF_SRC_ADDA_ADDA6,
859 STF_SRC_O19O20,
860 };
861
862 static SOC_VALUE_ENUM_SINGLE_DECL(stf_o19o20_mux_map_enum,
863 AFE_SIDETONE_CON1,
864 STF_SOURCE_FROM_O19O20_SFT,
865 STF_SOURCE_FROM_O19O20_MASK,
866 stf_o19o20_mux_map,
867 stf_o19o20_mux_map_value);
868
869 static const struct snd_kcontrol_new stf_o19O20_mux_control =
870 SOC_DAPM_ENUM("STF_O19O20_MUX", stf_o19o20_mux_map_enum);
871
872 enum {
873 STF_SRC_ADDA = 0,
874 STF_SRC_ADDA6,
875 };
876
877 static const char *const stf_adda_mux_map[] = {
878 "ADDA",
879 "ADDA6",
880 };
881
882 static int stf_adda_mux_map_value[] = {
883 STF_SRC_ADDA,
884 STF_SRC_ADDA6,
885 };
886
887 static SOC_VALUE_ENUM_SINGLE_DECL(stf_adda_mux_map_enum,
888 AFE_SIDETONE_CON1,
889 STF_O19O20_OUT_EN_SEL_SFT,
890 STF_O19O20_OUT_EN_SEL_MASK,
891 stf_adda_mux_map,
892 stf_adda_mux_map_value);
893
894 static const struct snd_kcontrol_new stf_adda_mux_control =
895 SOC_DAPM_ENUM("STF_ADDA_MUX", stf_adda_mux_map_enum);
896
897 /* ADDA UL MUX */
898 enum {
899 ADDA_UL_MUX_MTKAIF = 0,
900 ADDA_UL_MUX_AP_DMIC,
901 ADDA_UL_MUX_MASK = 0x1,
902 };
903
904 static const char * const adda_ul_mux_map[] = {
905 "MTKAIF", "AP_DMIC"
906 };
907
908 static int adda_ul_map_value[] = {
909 ADDA_UL_MUX_MTKAIF,
910 ADDA_UL_MUX_AP_DMIC,
911 };
912
913 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,
914 SND_SOC_NOPM,
915 0,
916 ADDA_UL_MUX_MASK,
917 adda_ul_mux_map,
918 adda_ul_map_value);
919
920 static const struct snd_kcontrol_new adda_ul_mux_control =
921 SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);
922
923 static const struct snd_kcontrol_new adda_ch34_ul_mux_control =
924 SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum);
925
926 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
927 /* inter-connections */
928 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
929 mtk_adda_dl_ch1_mix,
930 ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
931 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
932 mtk_adda_dl_ch2_mix,
933 ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
934
935 SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0,
936 mtk_adda_dl_ch3_mix,
937 ARRAY_SIZE(mtk_adda_dl_ch3_mix)),
938 SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0,
939 mtk_adda_dl_ch4_mix,
940 ARRAY_SIZE(mtk_adda_dl_ch4_mix)),
941
942 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
943 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
944 NULL, 0),
945
946 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
947 AFE_ADDA_DL_SRC2_CON0,
948 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
949 mtk_adda_dl_event,
950 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
951 SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Playback Enable",
952 SUPPLY_SEQ_ADDA_DL_ON,
953 AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
954 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
955 mtk_adda_ch34_dl_event,
956 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
957
958 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
959 AFE_ADDA_UL_SRC_CON0,
960 UL_SRC_ON_TMP_CTL_SFT, 0,
961 mtk_adda_ul_event,
962 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
963 SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
964 AFE_ADDA6_UL_SRC_CON0,
965 UL_SRC_ON_TMP_CTL_SFT, 0,
966 mtk_adda_ch34_ul_event,
967 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
968
969 SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,
970 AFE_AUD_PAD_TOP,
971 RG_RX_FIFO_ON_SFT, 0,
972 mtk_adda_pad_top_event,
973 SND_SOC_DAPM_PRE_PMU),
974 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,
975 SND_SOC_NOPM, 0, 0,
976 mtk_adda_mtkaif_cfg_event,
977 SND_SOC_DAPM_PRE_PMU),
978 SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG,
979 SND_SOC_NOPM, 0, 0,
980 mtk_adda_mtkaif_cfg_event,
981 SND_SOC_DAPM_PRE_PMU),
982
983 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
984 AFE_ADDA_UL_SRC_CON0,
985 UL_AP_DMIC_ON_SFT, 0,
986 NULL, 0),
987 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC,
988 AFE_ADDA6_UL_SRC_CON0,
989 UL_AP_DMIC_ON_SFT, 0,
990 NULL, 0),
991
992 SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,
993 AFE_ADDA_UL_DL_CON0,
994 AFE_ADDA_FIFO_AUTO_RST_SFT, 1,
995 NULL, 0),
996 SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO,
997 AFE_ADDA_UL_DL_CON0,
998 AFE_ADDA6_FIFO_AUTO_RST_SFT, 1,
999 NULL, 0),
1000
1001 SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,
1002 &adda_ul_mux_control),
1003 SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0,
1004 &adda_ch34_ul_mux_control),
1005
1006 SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),
1007 SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"),
1008
1009 /* stf */
1010 SND_SOC_DAPM_SWITCH_E("Sidetone Filter",
1011 AFE_SIDETONE_CON1, SIDE_TONE_ON_SFT, 0,
1012 &stf_ctl,
1013 mtk_stf_event,
1014 SND_SOC_DAPM_PRE_PMU |
1015 SND_SOC_DAPM_POST_PMD),
1016 SND_SOC_DAPM_MUX("STF_O19O20_MUX", SND_SOC_NOPM, 0, 0,
1017 &stf_o19O20_mux_control),
1018 SND_SOC_DAPM_MUX("STF_ADDA_MUX", SND_SOC_NOPM, 0, 0,
1019 &stf_adda_mux_control),
1020 SND_SOC_DAPM_MIXER("STF_CH1", SND_SOC_NOPM, 0, 0,
1021 mtk_stf_ch1_mix,
1022 ARRAY_SIZE(mtk_stf_ch1_mix)),
1023 SND_SOC_DAPM_MIXER("STF_CH2", SND_SOC_NOPM, 0, 0,
1024 mtk_stf_ch2_mix,
1025 ARRAY_SIZE(mtk_stf_ch2_mix)),
1026 SND_SOC_DAPM_OUTPUT("STF_OUTPUT"),
1027
1028 /* clock */
1029 SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),
1030
1031 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
1032 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
1033 SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_clk"),
1034 SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_predis_clk"),
1035
1036 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
1037 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_clk"),
1038 };
1039
1040 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
1041 /* playback */
1042 {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
1043 {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
1044 {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
1045
1046 {"ADDA_DL_CH1", "DL12_CH1", "DL12"},
1047 {"ADDA_DL_CH2", "DL12_CH2", "DL12"},
1048
1049 {"ADDA_DL_CH1", "DL6_CH1", "DL6"},
1050 {"ADDA_DL_CH2", "DL6_CH2", "DL6"},
1051
1052 {"ADDA_DL_CH1", "DL8_CH1", "DL8"},
1053 {"ADDA_DL_CH2", "DL8_CH2", "DL8"},
1054
1055 {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
1056 {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
1057 {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
1058
1059 {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
1060 {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
1061 {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
1062
1063 {"ADDA_DL_CH1", "DL4_CH1", "DL4"},
1064 {"ADDA_DL_CH2", "DL4_CH2", "DL4"},
1065
1066 {"ADDA_DL_CH1", "DL5_CH1", "DL5"},
1067 {"ADDA_DL_CH2", "DL5_CH2", "DL5"},
1068
1069 {"ADDA Playback", NULL, "ADDA_DL_CH1"},
1070 {"ADDA Playback", NULL, "ADDA_DL_CH2"},
1071
1072 {"ADDA Playback", NULL, "ADDA Enable"},
1073 {"ADDA Playback", NULL, "ADDA Playback Enable"},
1074
1075 {"ADDA_DL_CH3", "DL1_CH1", "DL1"},
1076 {"ADDA_DL_CH4", "DL1_CH1", "DL1"},
1077 {"ADDA_DL_CH4", "DL1_CH2", "DL1"},
1078
1079 {"ADDA_DL_CH3", "DL12_CH1", "DL12"},
1080 {"ADDA_DL_CH4", "DL12_CH2", "DL12"},
1081
1082 {"ADDA_DL_CH3", "DL6_CH1", "DL6"},
1083 {"ADDA_DL_CH4", "DL6_CH2", "DL6"},
1084
1085 {"ADDA_DL_CH3", "DL2_CH1", "DL2"},
1086 {"ADDA_DL_CH4", "DL2_CH1", "DL2"},
1087 {"ADDA_DL_CH4", "DL2_CH2", "DL2"},
1088
1089 {"ADDA_DL_CH3", "DL3_CH1", "DL3"},
1090 {"ADDA_DL_CH4", "DL3_CH1", "DL3"},
1091 {"ADDA_DL_CH4", "DL3_CH2", "DL3"},
1092
1093 {"ADDA_DL_CH3", "DL4_CH1", "DL4"},
1094 {"ADDA_DL_CH4", "DL4_CH2", "DL4"},
1095
1096 {"ADDA_DL_CH3", "DL5_CH1", "DL5"},
1097 {"ADDA_DL_CH4", "DL5_CH2", "DL5"},
1098
1099 {"ADDA CH34 Playback", NULL, "ADDA_DL_CH3"},
1100 {"ADDA CH34 Playback", NULL, "ADDA_DL_CH4"},
1101
1102 {"ADDA CH34 Playback", NULL, "ADDA Enable"},
1103 {"ADDA CH34 Playback", NULL, "ADDA CH34 Playback Enable"},
1104
1105 /* capture */
1106 {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},
1107 {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},
1108
1109 {"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"},
1110 {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"},
1111
1112 {"ADDA Capture", NULL, "ADDA Enable"},
1113 {"ADDA Capture", NULL, "ADDA Capture Enable"},
1114 {"ADDA Capture", NULL, "AUD_PAD_TOP"},
1115 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},
1116
1117 {"AP DMIC Capture", NULL, "ADDA Enable"},
1118 {"AP DMIC Capture", NULL, "ADDA Capture Enable"},
1119 {"AP DMIC Capture", NULL, "ADDA_FIFO"},
1120 {"AP DMIC Capture", NULL, "AP_DMIC_EN"},
1121
1122 {"ADDA CH34 Capture", NULL, "ADDA Enable"},
1123 {"ADDA CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
1124 {"ADDA CH34 Capture", NULL, "AUD_PAD_TOP"},
1125 {"ADDA CH34 Capture", NULL, "ADDA6_MTKAIF_CFG"},
1126
1127 {"AP DMIC CH34 Capture", NULL, "ADDA Enable"},
1128 {"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"},
1129 {"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"},
1130 {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"},
1131
1132 {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},
1133 {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"},
1134
1135 /* sidetone filter */
1136 {"STF_ADDA_MUX", "ADDA", "ADDA_UL_Mux"},
1137 {"STF_ADDA_MUX", "ADDA6", "ADDA_CH34_UL_Mux"},
1138
1139 {"STF_O19O20_MUX", "ADDA_ADDA6", "STF_ADDA_MUX"},
1140 {"STF_O19O20_MUX", "O19O20", "STF_CH1"},
1141 {"STF_O19O20_MUX", "O19O20", "STF_CH2"},
1142
1143 {"Sidetone Filter", "Switch", "STF_O19O20_MUX"},
1144 {"STF_OUTPUT", NULL, "Sidetone Filter"},
1145 {"ADDA Playback", NULL, "Sidetone Filter"},
1146 {"ADDA CH34 Playback", NULL, "Sidetone Filter"},
1147
1148 /* clk */
1149 {"ADDA Playback", NULL, "aud_dac_clk"},
1150 {"ADDA Playback", NULL, "aud_dac_predis_clk"},
1151
1152 {"ADDA CH34 Playback", NULL, "aud_3rd_dac_clk"},
1153 {"ADDA CH34 Playback", NULL, "aud_3rd_dac_predis_clk"},
1154
1155 {"ADDA Capture Enable", NULL, "aud_adc_clk"},
1156 {"ADDA CH34 Capture Enable", NULL, "aud_adda6_adc_clk"},
1157 };
1158
1159 /* dai ops */
1160 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
1161 struct snd_pcm_hw_params *params,
1162 struct snd_soc_dai *dai)
1163 {
1164 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1165 unsigned int rate = params_rate(params);
1166 int id = dai->id;
1167
1168 dev_info(afe->dev, "%s(), id %d, stream %d, rate %d\n",
1169 __func__,
1170 id,
1171 substream->stream,
1172 rate);
1173
1174 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1175 unsigned int dl_src2_con0 = 0;
1176 unsigned int dl_src2_con1 = 0;
1177
1178 /* set sampling rate */
1179 dl_src2_con0 = adda_dl_rate_transform(afe, rate) <<
1180 DL_2_INPUT_MODE_CTL_SFT;
1181
1182 /* set output mode, UP_SAMPLING_RATE_X8 */
1183 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);
1184
1185 /* turn off mute function */
1186 dl_src2_con0 |= (0x01 << DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);
1187 dl_src2_con0 |= (0x01 << DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);
1188
1189 /* set voice input data if input sample rate is 8k or 16k */
1190 if (rate == 8000 || rate == 16000)
1191 dl_src2_con0 |= 0x01 << DL_2_VOICE_MODE_CTL_PRE_SFT;
1192
1193 /* SA suggest apply -0.3db to audio/speech path */
1194 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<
1195 DL_2_GAIN_CTL_PRE_SFT;
1196
1197 /* turn on down-link gain */
1198 dl_src2_con0 |= (0x01 << DL_2_GAIN_ON_CTL_PRE_SFT);
1199
1200 if (id == MT8192_DAI_ADDA) {
1201 /* clean predistortion */
1202 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
1203 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
1204
1205 regmap_write(afe->regmap,
1206 AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
1207 regmap_write(afe->regmap,
1208 AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
1209
1210 /* set sdm gain */
1211 regmap_update_bits(afe->regmap,
1212 AFE_ADDA_DL_SDM_DCCOMP_CON,
1213 ATTGAIN_CTL_MASK_SFT,
1214 AUDIO_SDM_LEVEL_NORMAL <<
1215 ATTGAIN_CTL_SFT);
1216
1217 /* 2nd sdm */
1218 regmap_update_bits(afe->regmap,
1219 AFE_ADDA_DL_SDM_DCCOMP_CON,
1220 USE_3RD_SDM_MASK_SFT,
1221 AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
1222
1223 /* sdm auto reset */
1224 regmap_write(afe->regmap,
1225 AFE_ADDA_DL_SDM_AUTO_RESET_CON,
1226 SDM_AUTO_RESET_THRESHOLD);
1227 regmap_update_bits(afe->regmap,
1228 AFE_ADDA_DL_SDM_AUTO_RESET_CON,
1229 ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT,
1230 0x1 << ADDA_SDM_AUTO_RESET_ONOFF_SFT);
1231 } else {
1232 /* clean predistortion */
1233 regmap_write(afe->regmap,
1234 AFE_ADDA_3RD_DAC_PREDIS_CON0, 0);
1235 regmap_write(afe->regmap,
1236 AFE_ADDA_3RD_DAC_PREDIS_CON1, 0);
1237
1238 regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON0,
1239 dl_src2_con0);
1240 regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON1,
1241 dl_src2_con1);
1242
1243 /* set sdm gain */
1244 regmap_update_bits(afe->regmap,
1245 AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
1246 ATTGAIN_CTL_MASK_SFT,
1247 AUDIO_SDM_LEVEL_NORMAL <<
1248 ATTGAIN_CTL_SFT);
1249
1250 /* 2nd sdm */
1251 regmap_update_bits(afe->regmap,
1252 AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON,
1253 USE_3RD_SDM_MASK_SFT,
1254 AUDIO_SDM_2ND << USE_3RD_SDM_SFT);
1255
1256 /* sdm auto reset */
1257 regmap_write(afe->regmap,
1258 AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
1259 SDM_AUTO_RESET_THRESHOLD);
1260 regmap_update_bits(afe->regmap,
1261 AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON,
1262 ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT,
1263 0x1 << ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT);
1264 }
1265 } else {
1266 unsigned int voice_mode = 0;
1267 unsigned int ul_src_con0 = 0; /* default value */
1268
1269 voice_mode = adda_ul_rate_transform(afe, rate);
1270
1271 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
1272
1273 /* enable iir */
1274 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
1275 UL_IIR_ON_TMP_CTL_MASK_SFT;
1276 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &
1277 UL_IIRMODE_CTL_MASK_SFT;
1278
1279 switch (id) {
1280 case MT8192_DAI_ADDA:
1281 case MT8192_DAI_AP_DMIC:
1282 /* 35Hz @ 48k */
1283 regmap_write(afe->regmap,
1284 AFE_ADDA_IIR_COEF_02_01, 0x00000000);
1285 regmap_write(afe->regmap,
1286 AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
1287 regmap_write(afe->regmap,
1288 AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
1289 regmap_write(afe->regmap,
1290 AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
1291 regmap_write(afe->regmap,
1292 AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
1293
1294 regmap_write(afe->regmap,
1295 AFE_ADDA_UL_SRC_CON0, ul_src_con0);
1296
1297 /* Using Internal ADC */
1298 regmap_update_bits(afe->regmap,
1299 AFE_ADDA_TOP_CON0,
1300 0x1 << 0,
1301 0x0 << 0);
1302
1303 /* mtkaif_rxif_data_mode = 0, amic */
1304 regmap_update_bits(afe->regmap,
1305 AFE_ADDA_MTKAIF_RX_CFG0,
1306 0x1 << 0,
1307 0x0 << 0);
1308 break;
1309 case MT8192_DAI_ADDA_CH34:
1310 case MT8192_DAI_AP_DMIC_CH34:
1311 /* 35Hz @ 48k */
1312 regmap_write(afe->regmap,
1313 AFE_ADDA6_IIR_COEF_02_01, 0x00000000);
1314 regmap_write(afe->regmap,
1315 AFE_ADDA6_IIR_COEF_04_03, 0x00003FB8);
1316 regmap_write(afe->regmap,
1317 AFE_ADDA6_IIR_COEF_06_05, 0x3FB80000);
1318 regmap_write(afe->regmap,
1319 AFE_ADDA6_IIR_COEF_08_07, 0x3FB80000);
1320 regmap_write(afe->regmap,
1321 AFE_ADDA6_IIR_COEF_10_09, 0x0000C048);
1322
1323 regmap_write(afe->regmap,
1324 AFE_ADDA6_UL_SRC_CON0, ul_src_con0);
1325
1326 /* Using Internal ADC */
1327 regmap_update_bits(afe->regmap,
1328 AFE_ADDA6_TOP_CON0,
1329 0x1 << 0,
1330 0x0 << 0);
1331
1332 /* mtkaif_rxif_data_mode = 0, amic */
1333 regmap_update_bits(afe->regmap,
1334 AFE_ADDA6_MTKAIF_RX_CFG0,
1335 0x1 << 0,
1336 0x0 << 0);
1337 break;
1338 default:
1339 break;
1340 }
1341
1342 /* ap dmic */
1343 switch (id) {
1344 case MT8192_DAI_AP_DMIC:
1345 case MT8192_DAI_AP_DMIC_CH34:
1346 mtk_adda_ul_src_dmic(afe, id);
1347 break;
1348 default:
1349 break;
1350 }
1351 }
1352
1353 return 0;
1354 }
1355
1356 static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
1357 .hw_params = mtk_dai_adda_hw_params,
1358 };
1359
1360 /* dai driver */
1361 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
1362 SNDRV_PCM_RATE_96000 |\
1363 SNDRV_PCM_RATE_192000)
1364
1365 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1366 SNDRV_PCM_RATE_16000 |\
1367 SNDRV_PCM_RATE_32000 |\
1368 SNDRV_PCM_RATE_48000 |\
1369 SNDRV_PCM_RATE_96000 |\
1370 SNDRV_PCM_RATE_192000)
1371
1372 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1373 SNDRV_PCM_FMTBIT_S24_LE |\
1374 SNDRV_PCM_FMTBIT_S32_LE)
1375
1376 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
1377 {
1378 .name = "ADDA",
1379 .id = MT8192_DAI_ADDA,
1380 .playback = {
1381 .stream_name = "ADDA Playback",
1382 .channels_min = 1,
1383 .channels_max = 2,
1384 .rates = MTK_ADDA_PLAYBACK_RATES,
1385 .formats = MTK_ADDA_FORMATS,
1386 },
1387 .capture = {
1388 .stream_name = "ADDA Capture",
1389 .channels_min = 1,
1390 .channels_max = 2,
1391 .rates = MTK_ADDA_CAPTURE_RATES,
1392 .formats = MTK_ADDA_FORMATS,
1393 },
1394 .ops = &mtk_dai_adda_ops,
1395 },
1396 {
1397 .name = "ADDA_CH34",
1398 .id = MT8192_DAI_ADDA_CH34,
1399 .playback = {
1400 .stream_name = "ADDA CH34 Playback",
1401 .channels_min = 1,
1402 .channels_max = 2,
1403 .rates = MTK_ADDA_PLAYBACK_RATES,
1404 .formats = MTK_ADDA_FORMATS,
1405 },
1406 .capture = {
1407 .stream_name = "ADDA CH34 Capture",
1408 .channels_min = 1,
1409 .channels_max = 2,
1410 .rates = MTK_ADDA_CAPTURE_RATES,
1411 .formats = MTK_ADDA_FORMATS,
1412 },
1413 .ops = &mtk_dai_adda_ops,
1414 },
1415 {
1416 .name = "AP_DMIC",
1417 .id = MT8192_DAI_AP_DMIC,
1418 .capture = {
1419 .stream_name = "AP DMIC Capture",
1420 .channels_min = 1,
1421 .channels_max = 2,
1422 .rates = MTK_ADDA_CAPTURE_RATES,
1423 .formats = MTK_ADDA_FORMATS,
1424 },
1425 .ops = &mtk_dai_adda_ops,
1426 },
1427 {
1428 .name = "AP_DMIC_CH34",
1429 .id = MT8192_DAI_AP_DMIC_CH34,
1430 .capture = {
1431 .stream_name = "AP DMIC CH34 Capture",
1432 .channels_min = 1,
1433 .channels_max = 2,
1434 .rates = MTK_ADDA_CAPTURE_RATES,
1435 .formats = MTK_ADDA_FORMATS,
1436 },
1437 .ops = &mtk_dai_adda_ops,
1438 },
1439 };
1440
1441 int mt8192_dai_adda_register(struct mtk_base_afe *afe)
1442 {
1443 struct mtk_base_afe_dai *dai;
1444 struct mt8192_afe_private *afe_priv = afe->platform_priv;
1445
1446 dev_info(afe->dev, "%s()\n", __func__);
1447
1448 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1449 if (!dai)
1450 return -ENOMEM;
1451
1452 list_add(&dai->list, &afe->sub_dais);
1453
1454 dai->dai_drivers = mtk_dai_adda_driver;
1455 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
1456
1457 dai->controls = mtk_adda_controls;
1458 dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
1459 dai->dapm_widgets = mtk_dai_adda_widgets;
1460 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
1461 dai->dapm_routes = mtk_dai_adda_routes;
1462 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
1463
1464 /* ap dmic priv share with adda */
1465 afe_priv->dai_priv[MT8192_DAI_AP_DMIC] =
1466 afe_priv->dai_priv[MT8192_DAI_ADDA];
1467 afe_priv->dai_priv[MT8192_DAI_AP_DMIC_CH34] =
1468 afe_priv->dai_priv[MT8192_DAI_ADDA_CH34];
1469
1470 return 0;
1471 }
Linux with added FPC-III support