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WIP FPC-III support
[linux/fpc-iii.git] / sound / soc / mediatek / mt8192 / mt8192-dai-i2s.c
blob5b29340f9516c9cbe04747fe665d82c8d80a760c
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // MediaTek ALSA SoC Audio DAI I2S Control
4 //
5 // Copyright (c) 2020 MediaTek Inc.
6 // Author: Shane Chien <shane.chien@mediatek.com>
7 //
8
9 #include <linux/bitops.h>
10 #include <linux/regmap.h>
11 #include <sound/pcm_params.h>
12
13 #include "mt8192-afe-clk.h"
14 #include "mt8192-afe-common.h"
15 #include "mt8192-afe-gpio.h"
16 #include "mt8192-interconnection.h"
17
18 enum {
19 I2S_FMT_EIAJ = 0,
20 I2S_FMT_I2S = 1,
21 };
22
23 enum {
24 I2S_WLEN_16_BIT = 0,
25 I2S_WLEN_32_BIT = 1,
26 };
27
28 enum {
29 I2S_HD_NORMAL = 0,
30 I2S_HD_LOW_JITTER = 1,
31 };
32
33 enum {
34 I2S1_SEL_O28_O29 = 0,
35 I2S1_SEL_O03_O04 = 1,
36 };
37
38 enum {
39 I2S_IN_PAD_CONNSYS = 0,
40 I2S_IN_PAD_IO_MUX = 1,
41 };
42
43 struct mtk_afe_i2s_priv {
44 int id;
45 int rate; /* for determine which apll to use */
46 int low_jitter_en;
47
48 const char *share_property_name;
49 int share_i2s_id;
50
51 int mclk_id;
52 int mclk_rate;
53 int mclk_apll;
54 };
55
56 static unsigned int get_i2s_wlen(snd_pcm_format_t format)
57 {
58 return snd_pcm_format_physical_width(format) <= 16 ?
59 I2S_WLEN_16_BIT : I2S_WLEN_32_BIT;
60 }
61
62 #define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux"
63 #define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux"
64 #define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux"
65 #define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux"
66 #define MTK_AFE_I2S5_KCONTROL_NAME "I2S5_HD_Mux"
67 #define MTK_AFE_I2S6_KCONTROL_NAME "I2S6_HD_Mux"
68 #define MTK_AFE_I2S7_KCONTROL_NAME "I2S7_HD_Mux"
69 #define MTK_AFE_I2S8_KCONTROL_NAME "I2S8_HD_Mux"
70 #define MTK_AFE_I2S9_KCONTROL_NAME "I2S9_HD_Mux"
71
72 #define I2S0_HD_EN_W_NAME "I2S0_HD_EN"
73 #define I2S1_HD_EN_W_NAME "I2S1_HD_EN"
74 #define I2S2_HD_EN_W_NAME "I2S2_HD_EN"
75 #define I2S3_HD_EN_W_NAME "I2S3_HD_EN"
76 #define I2S5_HD_EN_W_NAME "I2S5_HD_EN"
77 #define I2S6_HD_EN_W_NAME "I2S6_HD_EN"
78 #define I2S7_HD_EN_W_NAME "I2S7_HD_EN"
79 #define I2S8_HD_EN_W_NAME "I2S8_HD_EN"
80 #define I2S9_HD_EN_W_NAME "I2S9_HD_EN"
81
82 #define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN"
83 #define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN"
84 #define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN"
85 #define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN"
86 #define I2S5_MCLK_EN_W_NAME "I2S5_MCLK_EN"
87 #define I2S6_MCLK_EN_W_NAME "I2S6_MCLK_EN"
88 #define I2S7_MCLK_EN_W_NAME "I2S7_MCLK_EN"
89 #define I2S8_MCLK_EN_W_NAME "I2S8_MCLK_EN"
90 #define I2S9_MCLK_EN_W_NAME "I2S9_MCLK_EN"
91
92 static int get_i2s_id_by_name(struct mtk_base_afe *afe,
93 const char *name)
94 {
95 if (strncmp(name, "I2S0", 4) == 0)
96 return MT8192_DAI_I2S_0;
97 else if (strncmp(name, "I2S1", 4) == 0)
98 return MT8192_DAI_I2S_1;
99 else if (strncmp(name, "I2S2", 4) == 0)
100 return MT8192_DAI_I2S_2;
101 else if (strncmp(name, "I2S3", 4) == 0)
102 return MT8192_DAI_I2S_3;
103 else if (strncmp(name, "I2S5", 4) == 0)
104 return MT8192_DAI_I2S_5;
105 else if (strncmp(name, "I2S6", 4) == 0)
106 return MT8192_DAI_I2S_6;
107 else if (strncmp(name, "I2S7", 4) == 0)
108 return MT8192_DAI_I2S_7;
109 else if (strncmp(name, "I2S8", 4) == 0)
110 return MT8192_DAI_I2S_8;
111 else if (strncmp(name, "I2S9", 4) == 0)
112 return MT8192_DAI_I2S_9;
113 else
114 return -EINVAL;
115 }
116
117 static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe,
118 const char *name)
119 {
120 struct mt8192_afe_private *afe_priv = afe->platform_priv;
121 int dai_id = get_i2s_id_by_name(afe, name);
122
123 if (dai_id < 0)
124 return NULL;
125
126 return afe_priv->dai_priv[dai_id];
127 }
128
129 /* low jitter control */
130 static const char * const mt8192_i2s_hd_str[] = {
131 "Normal", "Low_Jitter"
132 };
133
134 static SOC_ENUM_SINGLE_EXT_DECL(mt8192_i2s_enum, mt8192_i2s_hd_str);
135
136 static int mt8192_i2s_hd_get(struct snd_kcontrol *kcontrol,
137 struct snd_ctl_elem_value *ucontrol)
138 {
139 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
140 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
141 struct mtk_afe_i2s_priv *i2s_priv;
142
143 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
144
145 if (!i2s_priv) {
146 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
147 return -EINVAL;
148 }
149
150 ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en;
151
152 return 0;
153 }
154
155 static int mt8192_i2s_hd_set(struct snd_kcontrol *kcontrol,
156 struct snd_ctl_elem_value *ucontrol)
157 {
158 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
159 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
160 struct mtk_afe_i2s_priv *i2s_priv;
161 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
162 int hd_en;
163
164 if (ucontrol->value.enumerated.item[0] >= e->items)
165 return -EINVAL;
166
167 hd_en = ucontrol->value.integer.value[0];
168
169 dev_dbg(afe->dev, "%s(), kcontrol name %s, hd_en %d\n",
170 __func__, kcontrol->id.name, hd_en);
171
172 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
173
174 if (!i2s_priv) {
175 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
176 return -EINVAL;
177 }
178
179 i2s_priv->low_jitter_en = hd_en;
180
181 return 0;
182 }
183
184 static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = {
185 SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8192_i2s_enum,
186 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
187 SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8192_i2s_enum,
188 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
189 SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8192_i2s_enum,
190 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
191 SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8192_i2s_enum,
192 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
193 SOC_ENUM_EXT(MTK_AFE_I2S5_KCONTROL_NAME, mt8192_i2s_enum,
194 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
195 SOC_ENUM_EXT(MTK_AFE_I2S6_KCONTROL_NAME, mt8192_i2s_enum,
196 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
197 SOC_ENUM_EXT(MTK_AFE_I2S7_KCONTROL_NAME, mt8192_i2s_enum,
198 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
199 SOC_ENUM_EXT(MTK_AFE_I2S8_KCONTROL_NAME, mt8192_i2s_enum,
200 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
201 SOC_ENUM_EXT(MTK_AFE_I2S9_KCONTROL_NAME, mt8192_i2s_enum,
202 mt8192_i2s_hd_get, mt8192_i2s_hd_set),
203 };
204
205 /* dai component */
206 /* i2s virtual mux to output widget */
207 static const char * const i2s_mux_map[] = {
208 "Normal", "Dummy_Widget",
209 };
210
211 static int i2s_mux_map_value[] = {
212 0, 1,
213 };
214
215 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s_mux_map_enum,
216 SND_SOC_NOPM,
217 0,
218 1,
219 i2s_mux_map,
220 i2s_mux_map_value);
221
222 static const struct snd_kcontrol_new i2s0_in_mux_control =
223 SOC_DAPM_ENUM("I2S0 In Select", i2s_mux_map_enum);
224
225 static const struct snd_kcontrol_new i2s8_in_mux_control =
226 SOC_DAPM_ENUM("I2S8 In Select", i2s_mux_map_enum);
227
228 static const struct snd_kcontrol_new i2s1_out_mux_control =
229 SOC_DAPM_ENUM("I2S1 Out Select", i2s_mux_map_enum);
230
231 static const struct snd_kcontrol_new i2s3_out_mux_control =
232 SOC_DAPM_ENUM("I2S3 Out Select", i2s_mux_map_enum);
233
234 static const struct snd_kcontrol_new i2s5_out_mux_control =
235 SOC_DAPM_ENUM("I2S5 Out Select", i2s_mux_map_enum);
236
237 static const struct snd_kcontrol_new i2s7_out_mux_control =
238 SOC_DAPM_ENUM("I2S7 Out Select", i2s_mux_map_enum);
239
240 static const struct snd_kcontrol_new i2s9_out_mux_control =
241 SOC_DAPM_ENUM("I2S9 Out Select", i2s_mux_map_enum);
242
243 /* Tinyconn Mux */
244 enum {
245 TINYCONN_CH1_MUX_DL1 = 0x0,
246 TINYCONN_CH2_MUX_DL1 = 0x1,
247 TINYCONN_CH1_MUX_DL12 = 0x2,
248 TINYCONN_CH2_MUX_DL12 = 0x3,
249 TINYCONN_CH1_MUX_DL2 = 0x4,
250 TINYCONN_CH2_MUX_DL2 = 0x5,
251 TINYCONN_CH1_MUX_DL3 = 0x6,
252 TINYCONN_CH2_MUX_DL3 = 0x7,
253 TINYCONN_MUX_NONE = 0x1f,
254 };
255
256 static const char * const tinyconn_mux_map[] = {
257 "NONE",
258 "DL1_CH1",
259 "DL1_CH2",
260 "DL12_CH1",
261 "DL12_CH2",
262 "DL2_CH1",
263 "DL2_CH2",
264 "DL3_CH1",
265 "DL3_CH2",
266 };
267
268 static int tinyconn_mux_map_value[] = {
269 TINYCONN_MUX_NONE,
270 TINYCONN_CH1_MUX_DL1,
271 TINYCONN_CH2_MUX_DL1,
272 TINYCONN_CH1_MUX_DL12,
273 TINYCONN_CH2_MUX_DL12,
274 TINYCONN_CH1_MUX_DL2,
275 TINYCONN_CH2_MUX_DL2,
276 TINYCONN_CH1_MUX_DL3,
277 TINYCONN_CH2_MUX_DL3,
278 };
279
280 static SOC_VALUE_ENUM_SINGLE_DECL(i2s1_tinyconn_ch1_mux_map_enum,
281 AFE_TINY_CONN5,
282 O_20_CFG_SFT,
283 O_20_CFG_MASK,
284 tinyconn_mux_map,
285 tinyconn_mux_map_value);
286 static const struct snd_kcontrol_new i2s1_tinyconn_ch1_mux_control =
287 SOC_DAPM_ENUM("i2s1 ch1 tinyconn Select",
288 i2s1_tinyconn_ch1_mux_map_enum);
289
290 static SOC_VALUE_ENUM_SINGLE_DECL(i2s1_tinyconn_ch2_mux_map_enum,
291 AFE_TINY_CONN5,
292 O_21_CFG_SFT,
293 O_21_CFG_MASK,
294 tinyconn_mux_map,
295 tinyconn_mux_map_value);
296 static const struct snd_kcontrol_new i2s1_tinyconn_ch2_mux_control =
297 SOC_DAPM_ENUM("i2s1 ch2 tinyconn Select",
298 i2s1_tinyconn_ch2_mux_map_enum);
299
300 static SOC_VALUE_ENUM_SINGLE_DECL(i2s3_tinyconn_ch1_mux_map_enum,
301 AFE_TINY_CONN5,
302 O_22_CFG_SFT,
303 O_22_CFG_MASK,
304 tinyconn_mux_map,
305 tinyconn_mux_map_value);
306 static const struct snd_kcontrol_new i2s3_tinyconn_ch1_mux_control =
307 SOC_DAPM_ENUM("i2s3 ch1 tinyconn Select",
308 i2s3_tinyconn_ch1_mux_map_enum);
309
310 static SOC_VALUE_ENUM_SINGLE_DECL(i2s3_tinyconn_ch2_mux_map_enum,
311 AFE_TINY_CONN5,
312 O_23_CFG_SFT,
313 O_23_CFG_MASK,
314 tinyconn_mux_map,
315 tinyconn_mux_map_value);
316 static const struct snd_kcontrol_new i2s3_tinyconn_ch2_mux_control =
317 SOC_DAPM_ENUM("i2s3 ch2 tinyconn Select",
318 i2s3_tinyconn_ch2_mux_map_enum);
319
320 /* i2s in lpbk */
321 static const char * const i2s_lpbk_mux_map[] = {
322 "Normal", "Lpbk",
323 };
324
325 static int i2s_lpbk_mux_map_value[] = {
326 0, 1,
327 };
328
329 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s0_lpbk_mux_map_enum,
330 AFE_I2S_CON,
331 I2S_LOOPBACK_SFT,
332 1,
333 i2s_lpbk_mux_map,
334 i2s_lpbk_mux_map_value);
335
336 static const struct snd_kcontrol_new i2s0_lpbk_mux_control =
337 SOC_DAPM_ENUM("I2S Lpbk Select", i2s0_lpbk_mux_map_enum);
338
339 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(i2s2_lpbk_mux_map_enum,
340 AFE_I2S_CON2,
341 I2S3_LOOPBACK_SFT,
342 1,
343 i2s_lpbk_mux_map,
344 i2s_lpbk_mux_map_value);
345
346 static const struct snd_kcontrol_new i2s2_lpbk_mux_control =
347 SOC_DAPM_ENUM("I2S Lpbk Select", i2s2_lpbk_mux_map_enum);
348
349 /* interconnection */
350 static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = {
351 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN0, I_DL1_CH1, 1, 0),
352 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN0, I_DL2_CH1, 1, 0),
353 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN0, I_DL3_CH1, 1, 0),
354 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN0, I_DL12_CH1, 1, 0),
355 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN0_1, I_DL6_CH1, 1, 0),
356 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN0_1, I_DL4_CH1, 1, 0),
357 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN0_1, I_DL5_CH1, 1, 0),
358 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN0_1, I_DL8_CH1, 1, 0),
359 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN0_1, I_DL9_CH1, 1, 0),
360 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN0,
361 I_GAIN1_OUT_CH1, 1, 0),
362 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN0,
363 I_ADDA_UL_CH1, 1, 0),
364 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN0,
365 I_ADDA_UL_CH2, 1, 0),
366 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN0,
367 I_ADDA_UL_CH3, 1, 0),
368 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN0,
369 I_PCM_1_CAP_CH1, 1, 0),
370 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN0,
371 I_PCM_2_CAP_CH1, 1, 0),
372 };
373
374 static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = {
375 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN1, I_DL1_CH2, 1, 0),
376 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN1, I_DL2_CH2, 1, 0),
377 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN1, I_DL3_CH2, 1, 0),
378 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN1, I_DL12_CH2, 1, 0),
379 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN1_1, I_DL6_CH2, 1, 0),
380 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN1_1, I_DL4_CH2, 1, 0),
381 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN1_1, I_DL5_CH2, 1, 0),
382 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN1_1, I_DL8_CH2, 1, 0),
383 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN1_1, I_DL9_CH2, 1, 0),
384 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN1,
385 I_GAIN1_OUT_CH2, 1, 0),
386 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN1,
387 I_ADDA_UL_CH1, 1, 0),
388 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN1,
389 I_ADDA_UL_CH2, 1, 0),
390 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN1,
391 I_ADDA_UL_CH3, 1, 0),
392 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN1,
393 I_PCM_1_CAP_CH1, 1, 0),
394 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN1,
395 I_PCM_2_CAP_CH1, 1, 0),
396 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN1,
397 I_PCM_1_CAP_CH2, 1, 0),
398 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN1,
399 I_PCM_2_CAP_CH2, 1, 0),
400 };
401
402 static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = {
403 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN28, I_DL1_CH1, 1, 0),
404 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN28, I_DL2_CH1, 1, 0),
405 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN28, I_DL3_CH1, 1, 0),
406 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN28, I_DL12_CH1, 1, 0),
407 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN28_1, I_DL6_CH1, 1, 0),
408 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN28_1, I_DL4_CH1, 1, 0),
409 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN28_1, I_DL5_CH1, 1, 0),
410 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN28_1, I_DL8_CH1, 1, 0),
411 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN28_1, I_DL9_CH1, 1, 0),
412 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN28,
413 I_GAIN1_OUT_CH1, 1, 0),
414 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN28,
415 I_ADDA_UL_CH1, 1, 0),
416 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN28,
417 I_PCM_1_CAP_CH1, 1, 0),
418 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN28,
419 I_PCM_2_CAP_CH1, 1, 0),
420 };
421
422 static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = {
423 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN29, I_DL1_CH2, 1, 0),
424 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN29, I_DL2_CH2, 1, 0),
425 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN29, I_DL3_CH2, 1, 0),
426 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN29, I_DL12_CH2, 1, 0),
427 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN29_1, I_DL6_CH2, 1, 0),
428 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN29_1, I_DL4_CH2, 1, 0),
429 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN29_1, I_DL5_CH2, 1, 0),
430 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN29_1, I_DL8_CH2, 1, 0),
431 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN29_1, I_DL9_CH2, 1, 0),
432 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN29,
433 I_GAIN1_OUT_CH2, 1, 0),
434 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN29,
435 I_ADDA_UL_CH2, 1, 0),
436 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN29,
437 I_PCM_1_CAP_CH1, 1, 0),
438 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN29,
439 I_PCM_2_CAP_CH1, 1, 0),
440 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN29,
441 I_PCM_1_CAP_CH2, 1, 0),
442 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN29,
443 I_PCM_2_CAP_CH2, 1, 0),
444 };
445
446 static const struct snd_kcontrol_new mtk_i2s5_ch1_mix[] = {
447 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN30, I_DL1_CH1, 1, 0),
448 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN30, I_DL2_CH1, 1, 0),
449 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN30, I_DL3_CH1, 1, 0),
450 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN30, I_DL12_CH1, 1, 0),
451 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN30_1, I_DL6_CH1, 1, 0),
452 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN30_1, I_DL4_CH1, 1, 0),
453 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN30_1, I_DL5_CH1, 1, 0),
454 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN30_1, I_DL8_CH1, 1, 0),
455 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN30_1, I_DL9_CH1, 1, 0),
456 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN30,
457 I_GAIN1_OUT_CH1, 1, 0),
458 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN30,
459 I_ADDA_UL_CH1, 1, 0),
460 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN30,
461 I_PCM_1_CAP_CH1, 1, 0),
462 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN30,
463 I_PCM_2_CAP_CH1, 1, 0),
464 };
465
466 static const struct snd_kcontrol_new mtk_i2s5_ch2_mix[] = {
467 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN31, I_DL1_CH2, 1, 0),
468 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN31, I_DL2_CH2, 1, 0),
469 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN31, I_DL3_CH2, 1, 0),
470 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN31, I_DL12_CH2, 1, 0),
471 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN31_1, I_DL6_CH2, 1, 0),
472 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN31_1, I_DL4_CH2, 1, 0),
473 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN31_1, I_DL5_CH2, 1, 0),
474 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN31_1, I_DL8_CH2, 1, 0),
475 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN31_1, I_DL9_CH2, 1, 0),
476 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN31,
477 I_GAIN1_OUT_CH2, 1, 0),
478 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN31,
479 I_ADDA_UL_CH2, 1, 0),
480 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN31,
481 I_PCM_1_CAP_CH1, 1, 0),
482 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN31,
483 I_PCM_2_CAP_CH1, 1, 0),
484 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN31,
485 I_PCM_1_CAP_CH2, 1, 0),
486 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN31,
487 I_PCM_2_CAP_CH2, 1, 0),
488 };
489
490 static const struct snd_kcontrol_new mtk_i2s7_ch1_mix[] = {
491 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN54, I_DL1_CH1, 1, 0),
492 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN54, I_DL2_CH1, 1, 0),
493 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN54, I_DL3_CH1, 1, 0),
494 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN54, I_DL12_CH1, 1, 0),
495 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN54_1, I_DL6_CH1, 1, 0),
496 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN54_1, I_DL4_CH1, 1, 0),
497 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN54_1, I_DL5_CH1, 1, 0),
498 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN54_1, I_DL9_CH1, 1, 0),
499 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN54,
500 I_GAIN1_OUT_CH1, 1, 0),
501 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN54,
502 I_ADDA_UL_CH1, 1, 0),
503 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN54,
504 I_PCM_1_CAP_CH1, 1, 0),
505 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN54,
506 I_PCM_2_CAP_CH1, 1, 0),
507 };
508
509 static const struct snd_kcontrol_new mtk_i2s7_ch2_mix[] = {
510 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN55, I_DL1_CH2, 1, 0),
511 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN55, I_DL2_CH2, 1, 0),
512 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN55, I_DL3_CH2, 1, 0),
513 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN55, I_DL12_CH2, 1, 0),
514 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN55_1, I_DL6_CH2, 1, 0),
515 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN55_1, I_DL4_CH2, 1, 0),
516 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN55_1, I_DL5_CH2, 1, 0),
517 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN55_1, I_DL9_CH2, 1, 0),
518 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN55,
519 I_GAIN1_OUT_CH2, 1, 0),
520 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN55,
521 I_ADDA_UL_CH2, 1, 0),
522 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN55,
523 I_PCM_1_CAP_CH1, 1, 0),
524 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN55,
525 I_PCM_2_CAP_CH1, 1, 0),
526 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN55,
527 I_PCM_1_CAP_CH2, 1, 0),
528 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN55,
529 I_PCM_2_CAP_CH2, 1, 0),
530 };
531
532 static const struct snd_kcontrol_new mtk_i2s9_ch1_mix[] = {
533 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN56, I_DL1_CH1, 1, 0),
534 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN56, I_DL2_CH1, 1, 0),
535 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN56, I_DL3_CH1, 1, 0),
536 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN56, I_DL12_CH1, 1, 0),
537 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN56_1, I_DL6_CH1, 1, 0),
538 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN56_1, I_DL4_CH1, 1, 0),
539 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN56_1, I_DL5_CH1, 1, 0),
540 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN56_1, I_DL8_CH1, 1, 0),
541 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH1", AFE_CONN56_1, I_DL9_CH1, 1, 0),
542 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN56,
543 I_GAIN1_OUT_CH1, 1, 0),
544 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN56,
545 I_ADDA_UL_CH1, 1, 0),
546 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN56,
547 I_PCM_1_CAP_CH1, 1, 0),
548 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN56,
549 I_PCM_2_CAP_CH1, 1, 0),
550 };
551
552 static const struct snd_kcontrol_new mtk_i2s9_ch2_mix[] = {
553 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN57, I_DL1_CH2, 1, 0),
554 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN57, I_DL2_CH2, 1, 0),
555 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN57, I_DL3_CH2, 1, 0),
556 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN57, I_DL12_CH2, 1, 0),
557 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN57_1, I_DL6_CH2, 1, 0),
558 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN57_1, I_DL4_CH2, 1, 0),
559 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN57_1, I_DL5_CH2, 1, 0),
560 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN57_1, I_DL8_CH2, 1, 0),
561 SOC_DAPM_SINGLE_AUTODISABLE("DL9_CH2", AFE_CONN57_1, I_DL9_CH2, 1, 0),
562 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN57,
563 I_GAIN1_OUT_CH2, 1, 0),
564 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN57,
565 I_ADDA_UL_CH2, 1, 0),
566 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN57,
567 I_PCM_1_CAP_CH1, 1, 0),
568 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN57,
569 I_PCM_2_CAP_CH1, 1, 0),
570 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN57,
571 I_PCM_1_CAP_CH2, 1, 0),
572 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN57,
573 I_PCM_2_CAP_CH2, 1, 0),
574 };
575
576 enum {
577 SUPPLY_SEQ_APLL,
578 SUPPLY_SEQ_I2S_MCLK_EN,
579 SUPPLY_SEQ_I2S_HD_EN,
580 SUPPLY_SEQ_I2S_EN,
581 };
582
583 static int mtk_i2s_en_event(struct snd_soc_dapm_widget *w,
584 struct snd_kcontrol *kcontrol,
585 int event)
586 {
587 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
588 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
589 struct mtk_afe_i2s_priv *i2s_priv;
590
591 i2s_priv = get_i2s_priv_by_name(afe, w->name);
592
593 if (!i2s_priv) {
594 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
595 return -EINVAL;
596 }
597
598 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
599 __func__, w->name, event);
600
601 switch (event) {
602 case SND_SOC_DAPM_PRE_PMU:
603 mt8192_afe_gpio_request(afe->dev, true, i2s_priv->id, 0);
604 break;
605 case SND_SOC_DAPM_POST_PMD:
606 mt8192_afe_gpio_request(afe->dev, false, i2s_priv->id, 0);
607 break;
608 default:
609 break;
610 }
611
612 return 0;
613 }
614
615 static int mtk_apll_event(struct snd_soc_dapm_widget *w,
616 struct snd_kcontrol *kcontrol,
617 int event)
618 {
619 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
620 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
621
622 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
623 __func__, w->name, event);
624
625 switch (event) {
626 case SND_SOC_DAPM_PRE_PMU:
627 if (strcmp(w->name, APLL1_W_NAME) == 0)
628 mt8192_apll1_enable(afe);
629 else
630 mt8192_apll2_enable(afe);
631 break;
632 case SND_SOC_DAPM_POST_PMD:
633 if (strcmp(w->name, APLL1_W_NAME) == 0)
634 mt8192_apll1_disable(afe);
635 else
636 mt8192_apll2_disable(afe);
637 break;
638 default:
639 break;
640 }
641
642 return 0;
643 }
644
645 static int i2s_out_tinyconn_event(struct snd_soc_dapm_widget *w,
646 struct snd_kcontrol *kcontrol,
647 int event)
648 {
649 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
650 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
651 unsigned int reg;
652 unsigned int reg_shift;
653 unsigned int reg_mask_shift;
654
655 dev_dbg(afe->dev, "%s(), event 0x%x\n", __func__, event);
656
657 if (strstr(w->name, "I2S1")) {
658 reg = AFE_I2S_CON1;
659 reg_shift = I2S2_32BIT_EN_SFT;
660 reg_mask_shift = I2S2_32BIT_EN_MASK_SFT;
661 } else if (strstr(w->name, "I2S3")) {
662 reg = AFE_I2S_CON3;
663 reg_shift = I2S4_32BIT_EN_SFT;
664 reg_mask_shift = I2S4_32BIT_EN_MASK_SFT;
665 } else if (strstr(w->name, "I2S5")) {
666 reg = AFE_I2S_CON4;
667 reg_shift = I2S5_32BIT_EN_SFT;
668 reg_mask_shift = I2S5_32BIT_EN_MASK_SFT;
669 } else if (strstr(w->name, "I2S7")) {
670 reg = AFE_I2S_CON7;
671 reg_shift = I2S7_32BIT_EN_SFT;
672 reg_mask_shift = I2S7_32BIT_EN_MASK_SFT;
673 } else if (strstr(w->name, "I2S9")) {
674 reg = AFE_I2S_CON9;
675 reg_shift = I2S9_32BIT_EN_SFT;
676 reg_mask_shift = I2S9_32BIT_EN_MASK_SFT;
677 } else {
678 reg = AFE_I2S_CON1;
679 reg_shift = I2S2_32BIT_EN_SFT;
680 reg_mask_shift = I2S2_32BIT_EN_MASK_SFT;
681 dev_warn(afe->dev, "%s(), error widget name %s, use i2s1\n",
682 __func__, w->name);
683 }
684
685 switch (event) {
686 case SND_SOC_DAPM_PRE_PMU:
687 regmap_update_bits(afe->regmap, reg, reg_mask_shift,
688 0x1 << reg_shift);
689 break;
690 case SND_SOC_DAPM_PRE_PMD:
691 regmap_update_bits(afe->regmap, reg, reg_mask_shift,
692 0x0 << reg_shift);
693 break;
694 default:
695 break;
696 }
697
698 return 0;
699 }
700
701 static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w,
702 struct snd_kcontrol *kcontrol,
703 int event)
704 {
705 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
706 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
707 struct mtk_afe_i2s_priv *i2s_priv;
708
709 dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",
710 __func__, w->name, event);
711
712 i2s_priv = get_i2s_priv_by_name(afe, w->name);
713 if (!i2s_priv) {
714 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
715 return -EINVAL;
716 }
717
718 switch (event) {
719 case SND_SOC_DAPM_PRE_PMU:
720 mt8192_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate);
721 break;
722 case SND_SOC_DAPM_POST_PMD:
723 i2s_priv->mclk_rate = 0;
724 mt8192_mck_disable(afe, i2s_priv->mclk_id);
725 break;
726 default:
727 break;
728 }
729
730 return 0;
731 }
732
733 static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
734 SND_SOC_DAPM_INPUT("CONNSYS"),
735
736 SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0,
737 mtk_i2s1_ch1_mix,
738 ARRAY_SIZE(mtk_i2s1_ch1_mix)),
739 SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0,
740 mtk_i2s1_ch2_mix,
741 ARRAY_SIZE(mtk_i2s1_ch2_mix)),
742
743 SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0,
744 mtk_i2s3_ch1_mix,
745 ARRAY_SIZE(mtk_i2s3_ch1_mix)),
746 SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0,
747 mtk_i2s3_ch2_mix,
748 ARRAY_SIZE(mtk_i2s3_ch2_mix)),
749
750 SND_SOC_DAPM_MIXER("I2S5_CH1", SND_SOC_NOPM, 0, 0,
751 mtk_i2s5_ch1_mix,
752 ARRAY_SIZE(mtk_i2s5_ch1_mix)),
753 SND_SOC_DAPM_MIXER("I2S5_CH2", SND_SOC_NOPM, 0, 0,
754 mtk_i2s5_ch2_mix,
755 ARRAY_SIZE(mtk_i2s5_ch2_mix)),
756
757 SND_SOC_DAPM_MIXER("I2S7_CH1", SND_SOC_NOPM, 0, 0,
758 mtk_i2s7_ch1_mix,
759 ARRAY_SIZE(mtk_i2s7_ch1_mix)),
760 SND_SOC_DAPM_MIXER("I2S7_CH2", SND_SOC_NOPM, 0, 0,
761 mtk_i2s7_ch2_mix,
762 ARRAY_SIZE(mtk_i2s7_ch2_mix)),
763
764 SND_SOC_DAPM_MIXER("I2S9_CH1", SND_SOC_NOPM, 0, 0,
765 mtk_i2s9_ch1_mix,
766 ARRAY_SIZE(mtk_i2s9_ch1_mix)),
767 SND_SOC_DAPM_MIXER("I2S9_CH2", SND_SOC_NOPM, 0, 0,
768 mtk_i2s9_ch2_mix,
769 ARRAY_SIZE(mtk_i2s9_ch2_mix)),
770
771 SND_SOC_DAPM_MUX_E("I2S1_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0,
772 &i2s1_tinyconn_ch1_mux_control,
773 i2s_out_tinyconn_event,
774 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
775 SND_SOC_DAPM_MUX_E("I2S1_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0,
776 &i2s1_tinyconn_ch2_mux_control,
777 i2s_out_tinyconn_event,
778 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
779 SND_SOC_DAPM_MUX_E("I2S3_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0,
780 &i2s3_tinyconn_ch1_mux_control,
781 i2s_out_tinyconn_event,
782 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
783 SND_SOC_DAPM_MUX_E("I2S3_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0,
784 &i2s3_tinyconn_ch2_mux_control,
785 i2s_out_tinyconn_event,
786 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
787
788 /* i2s en*/
789 SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN,
790 AFE_I2S_CON, I2S_EN_SFT, 0,
791 mtk_i2s_en_event,
792 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
793 SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN,
794 AFE_I2S_CON1, I2S_EN_SFT, 0,
795 mtk_i2s_en_event,
796 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
797 SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN,
798 AFE_I2S_CON2, I2S_EN_SFT, 0,
799 mtk_i2s_en_event,
800 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
801 SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN,
802 AFE_I2S_CON3, I2S_EN_SFT, 0,
803 mtk_i2s_en_event,
804 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
805 SND_SOC_DAPM_SUPPLY_S("I2S5_EN", SUPPLY_SEQ_I2S_EN,
806 AFE_I2S_CON4, I2S5_EN_SFT, 0,
807 mtk_i2s_en_event,
808 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
809 SND_SOC_DAPM_SUPPLY_S("I2S6_EN", SUPPLY_SEQ_I2S_EN,
810 AFE_I2S_CON6, I2S6_EN_SFT, 0,
811 mtk_i2s_en_event,
812 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
813 SND_SOC_DAPM_SUPPLY_S("I2S7_EN", SUPPLY_SEQ_I2S_EN,
814 AFE_I2S_CON7, I2S7_EN_SFT, 0,
815 mtk_i2s_en_event,
816 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
817 SND_SOC_DAPM_SUPPLY_S("I2S8_EN", SUPPLY_SEQ_I2S_EN,
818 AFE_I2S_CON8, I2S8_EN_SFT, 0,
819 mtk_i2s_en_event,
820 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
821 SND_SOC_DAPM_SUPPLY_S("I2S9_EN", SUPPLY_SEQ_I2S_EN,
822 AFE_I2S_CON9, I2S9_EN_SFT, 0,
823 mtk_i2s_en_event,
824 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
825 /* i2s hd en */
826 SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
827 AFE_I2S_CON, I2S1_HD_EN_SFT, 0, NULL, 0),
828 SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
829 AFE_I2S_CON1, I2S2_HD_EN_SFT, 0, NULL, 0),
830 SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
831 AFE_I2S_CON2, I2S3_HD_EN_SFT, 0, NULL, 0),
832 SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
833 AFE_I2S_CON3, I2S4_HD_EN_SFT, 0, NULL, 0),
834 SND_SOC_DAPM_SUPPLY_S(I2S5_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
835 AFE_I2S_CON4, I2S5_HD_EN_SFT, 0, NULL, 0),
836 SND_SOC_DAPM_SUPPLY_S(I2S6_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
837 AFE_I2S_CON6, I2S6_HD_EN_SFT, 0, NULL, 0),
838 SND_SOC_DAPM_SUPPLY_S(I2S7_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
839 AFE_I2S_CON7, I2S7_HD_EN_SFT, 0, NULL, 0),
840 SND_SOC_DAPM_SUPPLY_S(I2S8_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
841 AFE_I2S_CON8, I2S8_HD_EN_SFT, 0, NULL, 0),
842 SND_SOC_DAPM_SUPPLY_S(I2S9_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
843 AFE_I2S_CON9, I2S9_HD_EN_SFT, 0, NULL, 0),
844
845 /* i2s mclk en */
846 SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
847 SND_SOC_NOPM, 0, 0,
848 mtk_mclk_en_event,
849 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
850 SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
851 SND_SOC_NOPM, 0, 0,
852 mtk_mclk_en_event,
853 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
854 SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
855 SND_SOC_NOPM, 0, 0,
856 mtk_mclk_en_event,
857 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
858 SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
859 SND_SOC_NOPM, 0, 0,
860 mtk_mclk_en_event,
861 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
862 SND_SOC_DAPM_SUPPLY_S(I2S5_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
863 SND_SOC_NOPM, 0, 0,
864 mtk_mclk_en_event,
865 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
866 SND_SOC_DAPM_SUPPLY_S(I2S6_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
867 SND_SOC_NOPM, 0, 0,
868 mtk_mclk_en_event,
869 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
870 SND_SOC_DAPM_SUPPLY_S(I2S7_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
871 SND_SOC_NOPM, 0, 0,
872 mtk_mclk_en_event,
873 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
874 SND_SOC_DAPM_SUPPLY_S(I2S8_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
875 SND_SOC_NOPM, 0, 0,
876 mtk_mclk_en_event,
877 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
878 SND_SOC_DAPM_SUPPLY_S(I2S9_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
879 SND_SOC_NOPM, 0, 0,
880 mtk_mclk_en_event,
881 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
882
883 /* apll */
884 SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
885 SND_SOC_NOPM, 0, 0,
886 mtk_apll_event,
887 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
888 SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
889 SND_SOC_NOPM, 0, 0,
890 mtk_apll_event,
891 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
892
893 /* allow i2s on without codec on */
894 SND_SOC_DAPM_OUTPUT("I2S_DUMMY_OUT"),
895 SND_SOC_DAPM_MUX("I2S1_Out_Mux",
896 SND_SOC_NOPM, 0, 0, &i2s1_out_mux_control),
897 SND_SOC_DAPM_MUX("I2S3_Out_Mux",
898 SND_SOC_NOPM, 0, 0, &i2s3_out_mux_control),
899 SND_SOC_DAPM_MUX("I2S5_Out_Mux",
900 SND_SOC_NOPM, 0, 0, &i2s5_out_mux_control),
901 SND_SOC_DAPM_MUX("I2S7_Out_Mux",
902 SND_SOC_NOPM, 0, 0, &i2s7_out_mux_control),
903 SND_SOC_DAPM_MUX("I2S9_Out_Mux",
904 SND_SOC_NOPM, 0, 0, &i2s9_out_mux_control),
905
906 SND_SOC_DAPM_INPUT("I2S_DUMMY_IN"),
907 SND_SOC_DAPM_MUX("I2S0_In_Mux",
908 SND_SOC_NOPM, 0, 0, &i2s0_in_mux_control),
909 SND_SOC_DAPM_MUX("I2S8_In_Mux",
910 SND_SOC_NOPM, 0, 0, &i2s8_in_mux_control),
911
912 /* i2s in lpbk */
913 SND_SOC_DAPM_MUX("I2S0_Lpbk_Mux",
914 SND_SOC_NOPM, 0, 0, &i2s0_lpbk_mux_control),
915 SND_SOC_DAPM_MUX("I2S2_Lpbk_Mux",
916 SND_SOC_NOPM, 0, 0, &i2s2_lpbk_mux_control),
917 };
918
919 static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source,
920 struct snd_soc_dapm_widget *sink)
921 {
922 struct snd_soc_dapm_widget *w = sink;
923 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
924 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
925 struct mtk_afe_i2s_priv *i2s_priv;
926
927 i2s_priv = get_i2s_priv_by_name(afe, sink->name);
928 if (!i2s_priv) {
929 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
930 return 0;
931 }
932
933 if (i2s_priv->share_i2s_id < 0)
934 return 0;
935
936 return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name);
937 }
938
939 static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source,
940 struct snd_soc_dapm_widget *sink)
941 {
942 struct snd_soc_dapm_widget *w = sink;
943 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
944 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
945 struct mtk_afe_i2s_priv *i2s_priv;
946
947 i2s_priv = get_i2s_priv_by_name(afe, sink->name);
948 if (!i2s_priv) {
949 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
950 return 0;
951 }
952
953 if (get_i2s_id_by_name(afe, sink->name) ==
954 get_i2s_id_by_name(afe, source->name))
955 return i2s_priv->low_jitter_en;
956
957 /* check if share i2s need hd en */
958 if (i2s_priv->share_i2s_id < 0)
959 return 0;
960
961 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
962 return i2s_priv->low_jitter_en;
963
964 return 0;
965 }
966
967 static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source,
968 struct snd_soc_dapm_widget *sink)
969 {
970 struct snd_soc_dapm_widget *w = sink;
971 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
972 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
973 struct mtk_afe_i2s_priv *i2s_priv;
974 int cur_apll;
975 int i2s_need_apll;
976
977 i2s_priv = get_i2s_priv_by_name(afe, w->name);
978 if (!i2s_priv) {
979 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
980 return 0;
981 }
982
983 /* which apll */
984 cur_apll = mt8192_get_apll_by_name(afe, source->name);
985
986 /* choose APLL from i2s rate */
987 i2s_need_apll = mt8192_get_apll_by_rate(afe, i2s_priv->rate);
988
989 if (i2s_need_apll == cur_apll)
990 return 1;
991
992 return 0;
993 }
994
995 static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source,
996 struct snd_soc_dapm_widget *sink)
997 {
998 struct snd_soc_dapm_widget *w = sink;
999 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1000 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
1001 struct mtk_afe_i2s_priv *i2s_priv;
1002
1003 i2s_priv = get_i2s_priv_by_name(afe, sink->name);
1004 if (!i2s_priv) {
1005 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
1006 return 0;
1007 }
1008
1009 if (get_i2s_id_by_name(afe, sink->name) ==
1010 get_i2s_id_by_name(afe, source->name))
1011 return (i2s_priv->mclk_rate > 0) ? 1 : 0;
1012
1013 /* check if share i2s need mclk */
1014 if (i2s_priv->share_i2s_id < 0)
1015 return 0;
1016
1017 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
1018 return (i2s_priv->mclk_rate > 0) ? 1 : 0;
1019
1020 return 0;
1021 }
1022
1023 static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
1024 struct snd_soc_dapm_widget *sink)
1025 {
1026 struct snd_soc_dapm_widget *w = sink;
1027 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1028 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
1029 struct mtk_afe_i2s_priv *i2s_priv;
1030 int cur_apll;
1031
1032 i2s_priv = get_i2s_priv_by_name(afe, w->name);
1033 if (!i2s_priv) {
1034 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
1035 return 0;
1036 }
1037
1038 /* which apll */
1039 cur_apll = mt8192_get_apll_by_name(afe, source->name);
1040
1041 if (i2s_priv->mclk_apll == cur_apll)
1042 return 1;
1043
1044 return 0;
1045 }
1046
1047 static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
1048 {"Connsys I2S", NULL, "CONNSYS"},
1049
1050 /* i2s0 */
1051 {"I2S0", NULL, "I2S0_EN"},
1052 {"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
1053 {"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
1054 {"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
1055 {"I2S0", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
1056 {"I2S0", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
1057 {"I2S0", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
1058 {"I2S0", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
1059 {"I2S0", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
1060
1061 {"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1062 {"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1063 {"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1064 {"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1065 {"I2S0", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1066 {"I2S0", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1067 {"I2S0", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1068 {"I2S0", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1069 {"I2S0", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1070 {I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1071 {I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1072
1073 {"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1074 {"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1075 {"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1076 {"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1077 {"I2S0", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1078 {"I2S0", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1079 {"I2S0", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1080 {"I2S0", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1081 {"I2S0", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1082 {I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1083 {I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1084
1085 /* i2s1 */
1086 {"I2S1_CH1", "DL1_CH1", "DL1"},
1087 {"I2S1_CH2", "DL1_CH2", "DL1"},
1088 {"I2S1_TINYCONN_CH1_MUX", "DL1_CH1", "DL1"},
1089 {"I2S1_TINYCONN_CH2_MUX", "DL1_CH2", "DL1"},
1090
1091 {"I2S1_CH1", "DL2_CH1", "DL2"},
1092 {"I2S1_CH2", "DL2_CH2", "DL2"},
1093 {"I2S1_TINYCONN_CH1_MUX", "DL2_CH1", "DL2"},
1094 {"I2S1_TINYCONN_CH2_MUX", "DL2_CH2", "DL2"},
1095
1096 {"I2S1_CH1", "DL3_CH1", "DL3"},
1097 {"I2S1_CH2", "DL3_CH2", "DL3"},
1098 {"I2S1_TINYCONN_CH1_MUX", "DL3_CH1", "DL3"},
1099 {"I2S1_TINYCONN_CH2_MUX", "DL3_CH2", "DL3"},
1100
1101 {"I2S1_CH1", "DL12_CH1", "DL12"},
1102 {"I2S1_CH2", "DL12_CH2", "DL12"},
1103 {"I2S1_TINYCONN_CH1_MUX", "DL12_CH1", "DL12"},
1104 {"I2S1_TINYCONN_CH2_MUX", "DL12_CH2", "DL12"},
1105
1106 {"I2S1_CH1", "DL4_CH1", "DL4"},
1107 {"I2S1_CH2", "DL4_CH2", "DL4"},
1108
1109 {"I2S1_CH1", "DL5_CH1", "DL5"},
1110 {"I2S1_CH2", "DL5_CH2", "DL5"},
1111
1112 {"I2S1_CH1", "DL6_CH1", "DL6"},
1113 {"I2S1_CH2", "DL6_CH2", "DL6"},
1114
1115 {"I2S1_CH1", "DL8_CH1", "DL8"},
1116 {"I2S1_CH2", "DL8_CH2", "DL8"},
1117
1118 {"I2S1", NULL, "I2S1_CH1"},
1119 {"I2S1", NULL, "I2S1_CH2"},
1120 {"I2S1", NULL, "I2S3_TINYCONN_CH1_MUX"},
1121 {"I2S1", NULL, "I2S3_TINYCONN_CH2_MUX"},
1122
1123 {"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
1124 {"I2S1", NULL, "I2S1_EN"},
1125 {"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
1126 {"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
1127 {"I2S1", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
1128 {"I2S1", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
1129 {"I2S1", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
1130 {"I2S1", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
1131 {"I2S1", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
1132
1133 {"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1134 {"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1135 {"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1136 {"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1137 {"I2S1", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1138 {"I2S1", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1139 {"I2S1", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1140 {"I2S1", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1141 {"I2S1", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1142 {I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1143 {I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1144
1145 {"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1146 {"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1147 {"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1148 {"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1149 {"I2S1", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1150 {"I2S1", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1151 {"I2S1", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1152 {"I2S1", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1153 {"I2S1", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1154 {I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1155 {I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1156
1157 /* i2s2 */
1158 {"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
1159 {"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
1160 {"I2S2", NULL, "I2S2_EN"},
1161 {"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
1162 {"I2S2", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
1163 {"I2S2", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
1164 {"I2S2", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
1165 {"I2S2", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
1166 {"I2S2", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
1167
1168 {"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1169 {"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1170 {"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1171 {"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1172 {"I2S2", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1173 {"I2S2", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1174 {"I2S2", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1175 {"I2S2", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1176 {"I2S2", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1177 {I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1178 {I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1179
1180 {"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1181 {"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1182 {"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1183 {"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1184 {"I2S2", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1185 {"I2S2", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1186 {"I2S2", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1187 {"I2S2", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1188 {"I2S2", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1189 {I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1190 {I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1191
1192 /* i2s3 */
1193 {"I2S3_CH1", "DL1_CH1", "DL1"},
1194 {"I2S3_CH2", "DL1_CH2", "DL1"},
1195 {"I2S3_TINYCONN_CH1_MUX", "DL1_CH1", "DL1"},
1196 {"I2S3_TINYCONN_CH2_MUX", "DL1_CH2", "DL1"},
1197
1198 {"I2S3_CH1", "DL2_CH1", "DL2"},
1199 {"I2S3_CH2", "DL2_CH2", "DL2"},
1200 {"I2S3_TINYCONN_CH1_MUX", "DL2_CH1", "DL2"},
1201 {"I2S3_TINYCONN_CH2_MUX", "DL2_CH2", "DL2"},
1202
1203 {"I2S3_CH1", "DL3_CH1", "DL3"},
1204 {"I2S3_CH2", "DL3_CH2", "DL3"},
1205 {"I2S3_TINYCONN_CH1_MUX", "DL3_CH1", "DL3"},
1206 {"I2S3_TINYCONN_CH2_MUX", "DL3_CH2", "DL3"},
1207
1208 {"I2S3_CH1", "DL12_CH1", "DL12"},
1209 {"I2S3_CH2", "DL12_CH2", "DL12"},
1210 {"I2S3_TINYCONN_CH1_MUX", "DL12_CH1", "DL12"},
1211 {"I2S3_TINYCONN_CH2_MUX", "DL12_CH2", "DL12"},
1212
1213 {"I2S3_CH1", "DL4_CH1", "DL4"},
1214 {"I2S3_CH2", "DL4_CH2", "DL4"},
1215
1216 {"I2S3_CH1", "DL5_CH1", "DL5"},
1217 {"I2S3_CH2", "DL5_CH2", "DL5"},
1218
1219 {"I2S3_CH1", "DL6_CH1", "DL6"},
1220 {"I2S3_CH2", "DL6_CH2", "DL6"},
1221
1222 {"I2S3_CH1", "DL8_CH1", "DL8"},
1223 {"I2S3_CH2", "DL8_CH2", "DL8"},
1224
1225 {"I2S3", NULL, "I2S3_CH1"},
1226 {"I2S3", NULL, "I2S3_CH2"},
1227 {"I2S3", NULL, "I2S3_TINYCONN_CH1_MUX"},
1228 {"I2S3", NULL, "I2S3_TINYCONN_CH2_MUX"},
1229
1230 {"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
1231 {"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
1232 {"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
1233 {"I2S3", NULL, "I2S3_EN"},
1234 {"I2S3", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
1235 {"I2S3", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
1236 {"I2S3", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
1237 {"I2S3", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
1238 {"I2S3", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
1239
1240 {"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1241 {"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1242 {"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1243 {"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1244 {"I2S3", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1245 {"I2S3", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1246 {"I2S3", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1247 {"I2S3", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1248 {"I2S3", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1249 {I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1250 {I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1251
1252 {"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1253 {"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1254 {"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1255 {"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1256 {"I2S3", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1257 {"I2S3", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1258 {"I2S3", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1259 {"I2S3", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1260 {"I2S3", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1261 {I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1262 {I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1263
1264 /* i2s5 */
1265 {"I2S5_CH1", "DL1_CH1", "DL1"},
1266 {"I2S5_CH2", "DL1_CH2", "DL1"},
1267
1268 {"I2S5_CH1", "DL2_CH1", "DL2"},
1269 {"I2S5_CH2", "DL2_CH2", "DL2"},
1270
1271 {"I2S5_CH1", "DL3_CH1", "DL3"},
1272 {"I2S5_CH2", "DL3_CH2", "DL3"},
1273
1274 {"I2S5_CH1", "DL12_CH1", "DL12"},
1275 {"I2S5_CH2", "DL12_CH2", "DL12"},
1276
1277 {"I2S5_CH1", "DL4_CH1", "DL4"},
1278 {"I2S5_CH2", "DL4_CH2", "DL4"},
1279
1280 {"I2S5_CH1", "DL5_CH1", "DL5"},
1281 {"I2S5_CH2", "DL5_CH2", "DL5"},
1282
1283 {"I2S5_CH1", "DL6_CH1", "DL6"},
1284 {"I2S5_CH2", "DL6_CH2", "DL6"},
1285
1286 {"I2S5_CH1", "DL8_CH1", "DL8"},
1287 {"I2S5_CH2", "DL8_CH2", "DL8"},
1288
1289 {"I2S5", NULL, "I2S5_CH1"},
1290 {"I2S5", NULL, "I2S5_CH2"},
1291
1292 {"I2S5", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
1293 {"I2S5", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
1294 {"I2S5", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
1295 {"I2S5", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
1296 {"I2S5", NULL, "I2S5_EN"},
1297 {"I2S5", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
1298 {"I2S5", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
1299 {"I2S5", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
1300 {"I2S5", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
1301
1302 {"I2S5", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1303 {"I2S5", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1304 {"I2S5", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1305 {"I2S5", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1306 {"I2S5", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1307 {"I2S5", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1308 {"I2S5", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1309 {"I2S5", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1310 {"I2S5", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1311 {I2S5_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1312 {I2S5_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1313
1314 {"I2S5", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1315 {"I2S5", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1316 {"I2S5", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1317 {"I2S5", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1318 {"I2S5", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1319 {"I2S5", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1320 {"I2S5", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1321 {"I2S5", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1322 {"I2S5", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1323 {I2S5_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1324 {I2S5_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1325
1326 /* i2s6 */
1327 {"I2S6", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
1328 {"I2S6", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
1329 {"I2S6", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
1330 {"I2S6", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
1331 {"I2S6", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
1332 {"I2S6", NULL, "I2S6_EN"},
1333 {"I2S6", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
1334 {"I2S6", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
1335 {"I2S6", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
1336
1337 {"I2S6", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1338 {"I2S6", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1339 {"I2S6", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1340 {"I2S6", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1341 {"I2S6", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1342 {"I2S6", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1343 {"I2S6", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1344 {"I2S6", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1345 {"I2S6", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1346 {I2S6_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1347 {I2S6_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1348
1349 {"I2S6", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1350 {"I2S6", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1351 {"I2S6", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1352 {"I2S6", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1353 {"I2S6", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1354 {"I2S6", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1355 {"I2S6", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1356 {"I2S6", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1357 {"I2S6", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1358 {I2S6_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1359 {I2S6_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1360
1361 /* i2s7 */
1362 {"I2S7", NULL, "I2S7_CH1"},
1363 {"I2S7", NULL, "I2S7_CH2"},
1364
1365 {"I2S7", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
1366 {"I2S7", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
1367 {"I2S7", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
1368 {"I2S7", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
1369 {"I2S7", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
1370 {"I2S7", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
1371 {"I2S7", NULL, "I2S7_EN"},
1372 {"I2S7", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
1373 {"I2S7", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
1374
1375 {"I2S7", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1376 {"I2S7", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1377 {"I2S7", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1378 {"I2S7", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1379 {"I2S7", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1380 {"I2S7", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1381 {"I2S7", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1382 {"I2S7", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1383 {"I2S7", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1384 {I2S7_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1385 {I2S7_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1386
1387 {"I2S7", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1388 {"I2S7", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1389 {"I2S7", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1390 {"I2S7", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1391 {"I2S7", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1392 {"I2S7", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1393 {"I2S7", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1394 {"I2S7", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1395 {"I2S7", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1396 {I2S7_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1397 {I2S7_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1398
1399 /* i2s8 */
1400 {"I2S8", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
1401 {"I2S8", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
1402 {"I2S8", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
1403 {"I2S8", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
1404 {"I2S8", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
1405 {"I2S8", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
1406 {"I2S8", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
1407 {"I2S8", NULL, "I2S8_EN"},
1408 {"I2S8", NULL, "I2S9_EN", mtk_afe_i2s_share_connect},
1409
1410 {"I2S8", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1411 {"I2S8", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1412 {"I2S8", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1413 {"I2S8", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1414 {"I2S8", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1415 {"I2S8", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1416 {"I2S8", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1417 {"I2S8", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1418 {"I2S8", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1419 {I2S8_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1420 {I2S8_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1421
1422 {"I2S8", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1423 {"I2S8", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1424 {"I2S8", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1425 {"I2S8", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1426 {"I2S8", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1427 {"I2S8", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1428 {"I2S8", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1429 {"I2S8", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1430 {"I2S8", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1431 {I2S8_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1432 {I2S8_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1433
1434 /* i2s9 */
1435 {"I2S9_CH1", "DL1_CH1", "DL1"},
1436 {"I2S9_CH2", "DL1_CH2", "DL1"},
1437
1438 {"I2S9_CH1", "DL2_CH1", "DL2"},
1439 {"I2S9_CH2", "DL2_CH2", "DL2"},
1440
1441 {"I2S9_CH1", "DL3_CH1", "DL3"},
1442 {"I2S9_CH2", "DL3_CH2", "DL3"},
1443
1444 {"I2S9_CH1", "DL12_CH1", "DL12"},
1445 {"I2S9_CH2", "DL12_CH2", "DL12"},
1446
1447 {"I2S9_CH1", "DL4_CH1", "DL4"},
1448 {"I2S9_CH2", "DL4_CH2", "DL4"},
1449
1450 {"I2S9_CH1", "DL5_CH1", "DL5"},
1451 {"I2S9_CH2", "DL5_CH2", "DL5"},
1452
1453 {"I2S9_CH1", "DL6_CH1", "DL6"},
1454 {"I2S9_CH2", "DL6_CH2", "DL6"},
1455
1456 {"I2S9_CH1", "DL8_CH1", "DL8"},
1457 {"I2S9_CH2", "DL8_CH2", "DL8"},
1458
1459 {"I2S9_CH1", "DL9_CH1", "DL9"},
1460 {"I2S9_CH2", "DL9_CH2", "DL9"},
1461
1462 {"I2S9", NULL, "I2S9_CH1"},
1463 {"I2S9", NULL, "I2S9_CH2"},
1464
1465 {"I2S9", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
1466 {"I2S9", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
1467 {"I2S9", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
1468 {"I2S9", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
1469 {"I2S9", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
1470 {"I2S9", NULL, "I2S6_EN", mtk_afe_i2s_share_connect},
1471 {"I2S9", NULL, "I2S7_EN", mtk_afe_i2s_share_connect},
1472 {"I2S9", NULL, "I2S8_EN", mtk_afe_i2s_share_connect},
1473 {"I2S9", NULL, "I2S9_EN"},
1474
1475 {"I2S9", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1476 {"I2S9", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1477 {"I2S9", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1478 {"I2S9", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1479 {"I2S9", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1480 {"I2S9", NULL, I2S6_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1481 {"I2S9", NULL, I2S7_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1482 {"I2S9", NULL, I2S8_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1483 {"I2S9", NULL, I2S9_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
1484 {I2S9_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
1485 {I2S9_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
1486
1487 {"I2S9", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1488 {"I2S9", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1489 {"I2S9", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1490 {"I2S9", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1491 {"I2S9", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1492 {"I2S9", NULL, I2S6_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1493 {"I2S9", NULL, I2S7_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1494 {"I2S9", NULL, I2S8_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1495 {"I2S9", NULL, I2S9_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
1496 {I2S9_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
1497 {I2S9_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
1498
1499 /* allow i2s on without codec on */
1500 {"I2S0", NULL, "I2S0_In_Mux"},
1501 {"I2S0_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
1502
1503 {"I2S8", NULL, "I2S8_In_Mux"},
1504 {"I2S8_In_Mux", "Dummy_Widget", "I2S_DUMMY_IN"},
1505
1506 {"I2S1_Out_Mux", "Dummy_Widget", "I2S1"},
1507 {"I2S_DUMMY_OUT", NULL, "I2S1_Out_Mux"},
1508
1509 {"I2S3_Out_Mux", "Dummy_Widget", "I2S3"},
1510 {"I2S_DUMMY_OUT", NULL, "I2S3_Out_Mux"},
1511
1512 {"I2S5_Out_Mux", "Dummy_Widget", "I2S5"},
1513 {"I2S_DUMMY_OUT", NULL, "I2S5_Out_Mux"},
1514
1515 {"I2S7_Out_Mux", "Dummy_Widget", "I2S7"},
1516 {"I2S_DUMMY_OUT", NULL, "I2S7_Out_Mux"},
1517
1518 {"I2S9_Out_Mux", "Dummy_Widget", "I2S9"},
1519 {"I2S_DUMMY_OUT", NULL, "I2S9_Out_Mux"},
1520
1521 /* i2s in lpbk */
1522 {"I2S0_Lpbk_Mux", "Lpbk", "I2S3"},
1523 {"I2S2_Lpbk_Mux", "Lpbk", "I2S1"},
1524 {"I2S0", NULL, "I2S0_Lpbk_Mux"},
1525 {"I2S2", NULL, "I2S2_Lpbk_Mux"},
1526 };
1527
1528 /* dai ops */
1529 static int mtk_dai_connsys_i2s_hw_params(struct snd_pcm_substream *substream,
1530 struct snd_pcm_hw_params *params,
1531 struct snd_soc_dai *dai)
1532 {
1533 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1534 unsigned int rate = params_rate(params);
1535 unsigned int rate_reg = mt8192_rate_transform(afe->dev,
1536 rate, dai->id);
1537 unsigned int i2s_con = 0;
1538
1539 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
1540 __func__, dai->id, substream->stream, rate);
1541
1542 /* non-inverse, i2s mode, proxy mode, 16bits, from connsys */
1543 i2s_con |= 0 << INV_PAD_CTRL_SFT;
1544 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
1545 i2s_con |= 1 << I2S_SRC_SFT;
1546 i2s_con |= get_i2s_wlen(SNDRV_PCM_FORMAT_S16_LE) << I2S_WLEN_SFT;
1547 i2s_con |= 0 << I2SIN_PAD_SEL_SFT;
1548 regmap_write(afe->regmap, AFE_CONNSYS_I2S_CON, i2s_con);
1549
1550 /* use asrc */
1551 regmap_update_bits(afe->regmap,
1552 AFE_CONNSYS_I2S_CON,
1553 I2S_BYPSRC_MASK_SFT,
1554 0x0 << I2S_BYPSRC_SFT);
1555
1556 /* proxy mode, set i2s for asrc */
1557 regmap_update_bits(afe->regmap,
1558 AFE_CONNSYS_I2S_CON,
1559 I2S_MODE_MASK_SFT,
1560 rate_reg << I2S_MODE_SFT);
1561
1562 switch (rate) {
1563 case 32000:
1564 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x140000);
1565 break;
1566 case 44100:
1567 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x001B9000);
1568 break;
1569 default:
1570 regmap_write(afe->regmap, AFE_ASRC_2CH_CON3, 0x001E0000);
1571 break;
1572 }
1573
1574 /* Calibration setting */
1575 regmap_write(afe->regmap, AFE_ASRC_2CH_CON4, 0x00140000);
1576 regmap_write(afe->regmap, AFE_ASRC_2CH_CON9, 0x00036000);
1577 regmap_write(afe->regmap, AFE_ASRC_2CH_CON10, 0x0002FC00);
1578 regmap_write(afe->regmap, AFE_ASRC_2CH_CON6, 0x00007EF4);
1579 regmap_write(afe->regmap, AFE_ASRC_2CH_CON5, 0x00FF5986);
1580
1581 /* 0:Stereo 1:Mono */
1582 regmap_update_bits(afe->regmap,
1583 AFE_ASRC_2CH_CON2,
1584 CHSET_IS_MONO_MASK_SFT,
1585 0x0 << CHSET_IS_MONO_SFT);
1586
1587 return 0;
1588 }
1589
1590 static int mtk_dai_connsys_i2s_trigger(struct snd_pcm_substream *substream,
1591 int cmd, struct snd_soc_dai *dai)
1592 {
1593 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1594 struct mt8192_afe_private *afe_priv = afe->platform_priv;
1595
1596 dev_dbg(afe->dev, "%s(), cmd %d, stream %d\n",
1597 __func__, cmd, substream->stream);
1598
1599 switch (cmd) {
1600 case SNDRV_PCM_TRIGGER_START:
1601 case SNDRV_PCM_TRIGGER_RESUME:
1602 /* i2s enable */
1603 regmap_update_bits(afe->regmap,
1604 AFE_CONNSYS_I2S_CON,
1605 I2S_EN_MASK_SFT,
1606 0x1 << I2S_EN_SFT);
1607
1608 /* calibrator enable */
1609 regmap_update_bits(afe->regmap,
1610 AFE_ASRC_2CH_CON5,
1611 CALI_EN_MASK_SFT,
1612 0x1 << CALI_EN_SFT);
1613
1614 /* asrc enable */
1615 regmap_update_bits(afe->regmap,
1616 AFE_ASRC_2CH_CON0,
1617 CON0_CHSET_STR_CLR_MASK_SFT,
1618 0x1 << CON0_CHSET_STR_CLR_SFT);
1619 regmap_update_bits(afe->regmap,
1620 AFE_ASRC_2CH_CON0,
1621 CON0_ASM_ON_MASK_SFT,
1622 0x1 << CON0_ASM_ON_SFT);
1623
1624 afe_priv->dai_on[dai->id] = true;
1625 break;
1626 case SNDRV_PCM_TRIGGER_STOP:
1627 case SNDRV_PCM_TRIGGER_SUSPEND:
1628 regmap_update_bits(afe->regmap,
1629 AFE_ASRC_2CH_CON0,
1630 CON0_ASM_ON_MASK_SFT,
1631 0 << CON0_ASM_ON_SFT);
1632 regmap_update_bits(afe->regmap,
1633 AFE_ASRC_2CH_CON5,
1634 CALI_EN_MASK_SFT,
1635 0 << CALI_EN_SFT);
1636
1637 /* i2s disable */
1638 regmap_update_bits(afe->regmap,
1639 AFE_CONNSYS_I2S_CON,
1640 I2S_EN_MASK_SFT,
1641 0x0 << I2S_EN_SFT);
1642
1643 /* bypass asrc */
1644 regmap_update_bits(afe->regmap,
1645 AFE_CONNSYS_I2S_CON,
1646 I2S_BYPSRC_MASK_SFT,
1647 0x1 << I2S_BYPSRC_SFT);
1648
1649 afe_priv->dai_on[dai->id] = false;
1650 break;
1651 default:
1652 return -EINVAL;
1653 }
1654 return 0;
1655 }
1656
1657 static const struct snd_soc_dai_ops mtk_dai_connsys_i2s_ops = {
1658 .hw_params = mtk_dai_connsys_i2s_hw_params,
1659 .trigger = mtk_dai_connsys_i2s_trigger,
1660 };
1661
1662 /* i2s */
1663 static int mtk_dai_i2s_config(struct mtk_base_afe *afe,
1664 struct snd_pcm_hw_params *params,
1665 int i2s_id)
1666 {
1667 struct mt8192_afe_private *afe_priv = afe->platform_priv;
1668 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id];
1669
1670 unsigned int rate = params_rate(params);
1671 unsigned int rate_reg = mt8192_rate_transform(afe->dev,
1672 rate, i2s_id);
1673 snd_pcm_format_t format = params_format(params);
1674 unsigned int i2s_con = 0;
1675 int ret = 0;
1676
1677 dev_dbg(afe->dev, "%s(), id %d, rate %d, format %d\n",
1678 __func__, i2s_id, rate, format);
1679
1680 if (i2s_priv)
1681 i2s_priv->rate = rate;
1682 else
1683 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
1684
1685 switch (i2s_id) {
1686 case MT8192_DAI_I2S_0:
1687 i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT;
1688 i2s_con |= rate_reg << I2S_OUT_MODE_SFT;
1689 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
1690 i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT;
1691 regmap_update_bits(afe->regmap, AFE_I2S_CON,
1692 0xffffeffe, i2s_con);
1693 break;
1694 case MT8192_DAI_I2S_1:
1695 i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT;
1696 i2s_con |= rate_reg << I2S2_OUT_MODE_SFT;
1697 i2s_con |= I2S_FMT_I2S << I2S2_FMT_SFT;
1698 i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT;
1699 regmap_update_bits(afe->regmap, AFE_I2S_CON1,
1700 0xffffeffe, i2s_con);
1701 break;
1702 case MT8192_DAI_I2S_2:
1703 i2s_con = 8 << I2S3_UPDATE_WORD_SFT;
1704 i2s_con |= rate_reg << I2S3_OUT_MODE_SFT;
1705 i2s_con |= I2S_FMT_I2S << I2S3_FMT_SFT;
1706 i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT;
1707 regmap_update_bits(afe->regmap, AFE_I2S_CON2,
1708 0xffffeffe, i2s_con);
1709 break;
1710 case MT8192_DAI_I2S_3:
1711 i2s_con = rate_reg << I2S4_OUT_MODE_SFT;
1712 i2s_con |= I2S_FMT_I2S << I2S4_FMT_SFT;
1713 i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT;
1714 regmap_update_bits(afe->regmap, AFE_I2S_CON3,
1715 0xffffeffe, i2s_con);
1716 break;
1717 case MT8192_DAI_I2S_5:
1718 i2s_con = rate_reg << I2S5_OUT_MODE_SFT;
1719 i2s_con |= I2S_FMT_I2S << I2S5_FMT_SFT;
1720 i2s_con |= get_i2s_wlen(format) << I2S5_WLEN_SFT;
1721 regmap_update_bits(afe->regmap, AFE_I2S_CON4,
1722 0xffffeffe, i2s_con);
1723 break;
1724 case MT8192_DAI_I2S_6:
1725 i2s_con = rate_reg << I2S6_OUT_MODE_SFT;
1726 i2s_con |= I2S_FMT_I2S << I2S6_FMT_SFT;
1727 i2s_con |= get_i2s_wlen(format) << I2S6_WLEN_SFT;
1728 regmap_update_bits(afe->regmap, AFE_I2S_CON6,
1729 0xffffeffe, i2s_con);
1730 break;
1731 case MT8192_DAI_I2S_7:
1732 i2s_con = rate_reg << I2S7_OUT_MODE_SFT;
1733 i2s_con |= I2S_FMT_I2S << I2S7_FMT_SFT;
1734 i2s_con |= get_i2s_wlen(format) << I2S7_WLEN_SFT;
1735 regmap_update_bits(afe->regmap, AFE_I2S_CON7,
1736 0xffffeffe, i2s_con);
1737 break;
1738 case MT8192_DAI_I2S_8:
1739 i2s_con = rate_reg << I2S8_OUT_MODE_SFT;
1740 i2s_con |= I2S_FMT_I2S << I2S8_FMT_SFT;
1741 i2s_con |= get_i2s_wlen(format) << I2S8_WLEN_SFT;
1742 regmap_update_bits(afe->regmap, AFE_I2S_CON8,
1743 0xffffeffe, i2s_con);
1744 break;
1745 case MT8192_DAI_I2S_9:
1746 i2s_con = rate_reg << I2S9_OUT_MODE_SFT;
1747 i2s_con |= I2S_FMT_I2S << I2S9_FMT_SFT;
1748 i2s_con |= get_i2s_wlen(format) << I2S9_WLEN_SFT;
1749 regmap_update_bits(afe->regmap, AFE_I2S_CON9,
1750 0xffffeffe, i2s_con);
1751 break;
1752 default:
1753 dev_warn(afe->dev, "%s(), id %d not support\n",
1754 __func__, i2s_id);
1755 return -EINVAL;
1756 }
1757
1758 /* set share i2s */
1759 if (i2s_priv && i2s_priv->share_i2s_id >= 0)
1760 ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id);
1761
1762 return ret;
1763 }
1764
1765 static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream,
1766 struct snd_pcm_hw_params *params,
1767 struct snd_soc_dai *dai)
1768 {
1769 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
1770
1771 return mtk_dai_i2s_config(afe, params, dai->id);
1772 }
1773
1774 static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai,
1775 int clk_id, unsigned int freq, int dir)
1776 {
1777 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
1778 struct mt8192_afe_private *afe_priv = afe->platform_priv;
1779 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id];
1780 int apll;
1781 int apll_rate;
1782
1783 if (!i2s_priv) {
1784 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
1785 return -EINVAL;
1786 }
1787
1788 if (dir != SND_SOC_CLOCK_OUT) {
1789 dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
1790 return -EINVAL;
1791 }
1792
1793 dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);
1794
1795 apll = mt8192_get_apll_by_rate(afe, freq);
1796 apll_rate = mt8192_get_apll_rate(afe, apll);
1797
1798 if (freq > apll_rate) {
1799 dev_warn(afe->dev, "%s(), freq > apll rate", __func__);
1800 return -EINVAL;
1801 }
1802
1803 if (apll_rate % freq != 0) {
1804 dev_warn(afe->dev, "%s(), APLL can't gen freq Hz", __func__);
1805 return -EINVAL;
1806 }
1807
1808 i2s_priv->mclk_rate = freq;
1809 i2s_priv->mclk_apll = apll;
1810
1811 if (i2s_priv->share_i2s_id > 0) {
1812 struct mtk_afe_i2s_priv *share_i2s_priv;
1813
1814 share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
1815 if (!share_i2s_priv) {
1816 dev_warn(afe->dev, "%s(), share_i2s_priv = NULL",
1817 __func__);
1818 return -EINVAL;
1819 }
1820
1821 share_i2s_priv->mclk_rate = i2s_priv->mclk_rate;
1822 share_i2s_priv->mclk_apll = i2s_priv->mclk_apll;
1823 }
1824
1825 return 0;
1826 }
1827
1828 static const struct snd_soc_dai_ops mtk_dai_i2s_ops = {
1829 .hw_params = mtk_dai_i2s_hw_params,
1830 .set_sysclk = mtk_dai_i2s_set_sysclk,
1831 };
1832
1833 /* dai driver */
1834 #define MTK_CONNSYS_I2S_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1835
1836 #define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\
1837 SNDRV_PCM_RATE_88200 |\
1838 SNDRV_PCM_RATE_96000 |\
1839 SNDRV_PCM_RATE_176400 |\
1840 SNDRV_PCM_RATE_192000)
1841
1842 #define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1843 SNDRV_PCM_FMTBIT_S24_LE |\
1844 SNDRV_PCM_FMTBIT_S32_LE)
1845
1846 static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
1847 {
1848 .name = "CONNSYS_I2S",
1849 .id = MT8192_DAI_CONNSYS_I2S,
1850 .capture = {
1851 .stream_name = "Connsys I2S",
1852 .channels_min = 1,
1853 .channels_max = 2,
1854 .rates = MTK_CONNSYS_I2S_RATES,
1855 .formats = MTK_I2S_FORMATS,
1856 },
1857 .ops = &mtk_dai_connsys_i2s_ops,
1858 },
1859 {
1860 .name = "I2S0",
1861 .id = MT8192_DAI_I2S_0,
1862 .capture = {
1863 .stream_name = "I2S0",
1864 .channels_min = 1,
1865 .channels_max = 2,
1866 .rates = MTK_I2S_RATES,
1867 .formats = MTK_I2S_FORMATS,
1868 },
1869 .ops = &mtk_dai_i2s_ops,
1870 },
1871 {
1872 .name = "I2S1",
1873 .id = MT8192_DAI_I2S_1,
1874 .playback = {
1875 .stream_name = "I2S1",
1876 .channels_min = 1,
1877 .channels_max = 2,
1878 .rates = MTK_I2S_RATES,
1879 .formats = MTK_I2S_FORMATS,
1880 },
1881 .ops = &mtk_dai_i2s_ops,
1882 },
1883 {
1884 .name = "I2S2",
1885 .id = MT8192_DAI_I2S_2,
1886 .capture = {
1887 .stream_name = "I2S2",
1888 .channels_min = 1,
1889 .channels_max = 2,
1890 .rates = MTK_I2S_RATES,
1891 .formats = MTK_I2S_FORMATS,
1892 },
1893 .ops = &mtk_dai_i2s_ops,
1894 },
1895 {
1896 .name = "I2S3",
1897 .id = MT8192_DAI_I2S_3,
1898 .playback = {
1899 .stream_name = "I2S3",
1900 .channels_min = 1,
1901 .channels_max = 2,
1902 .rates = MTK_I2S_RATES,
1903 .formats = MTK_I2S_FORMATS,
1904 },
1905 .ops = &mtk_dai_i2s_ops,
1906 },
1907 {
1908 .name = "I2S5",
1909 .id = MT8192_DAI_I2S_5,
1910 .playback = {
1911 .stream_name = "I2S5",
1912 .channels_min = 1,
1913 .channels_max = 2,
1914 .rates = MTK_I2S_RATES,
1915 .formats = MTK_I2S_FORMATS,
1916 },
1917 .ops = &mtk_dai_i2s_ops,
1918 },
1919 {
1920 .name = "I2S6",
1921 .id = MT8192_DAI_I2S_6,
1922 .capture = {
1923 .stream_name = "I2S6",
1924 .channels_min = 1,
1925 .channels_max = 2,
1926 .rates = MTK_I2S_RATES,
1927 .formats = MTK_I2S_FORMATS,
1928 },
1929 .ops = &mtk_dai_i2s_ops,
1930 },
1931 {
1932 .name = "I2S7",
1933 .id = MT8192_DAI_I2S_7,
1934 .playback = {
1935 .stream_name = "I2S7",
1936 .channels_min = 1,
1937 .channels_max = 2,
1938 .rates = MTK_I2S_RATES,
1939 .formats = MTK_I2S_FORMATS,
1940 },
1941 .ops = &mtk_dai_i2s_ops,
1942 },
1943 {
1944 .name = "I2S8",
1945 .id = MT8192_DAI_I2S_8,
1946 .capture = {
1947 .stream_name = "I2S8",
1948 .channels_min = 1,
1949 .channels_max = 2,
1950 .rates = MTK_I2S_RATES,
1951 .formats = MTK_I2S_FORMATS,
1952 },
1953 .ops = &mtk_dai_i2s_ops,
1954 },
1955 {
1956 .name = "I2S9",
1957 .id = MT8192_DAI_I2S_9,
1958 .playback = {
1959 .stream_name = "I2S9",
1960 .channels_min = 1,
1961 .channels_max = 2,
1962 .rates = MTK_I2S_RATES,
1963 .formats = MTK_I2S_FORMATS,
1964 },
1965 .ops = &mtk_dai_i2s_ops,
1966 }
1967 };
1968
1969 /* this enum is merely for mtk_afe_i2s_priv declare */
1970 enum {
1971 DAI_I2S0 = 0,
1972 DAI_I2S1,
1973 DAI_I2S2,
1974 DAI_I2S3,
1975 DAI_I2S5,
1976 DAI_I2S6,
1977 DAI_I2S7,
1978 DAI_I2S8,
1979 DAI_I2S9,
1980 DAI_I2S_NUM,
1981 };
1982
1983 static const struct mtk_afe_i2s_priv mt8192_i2s_priv[DAI_I2S_NUM] = {
1984 [DAI_I2S0] = {
1985 .id = MT8192_DAI_I2S_0,
1986 .mclk_id = MT8192_I2S0_MCK,
1987 .share_property_name = "i2s0-share",
1988 .share_i2s_id = -1,
1989 },
1990 [DAI_I2S1] = {
1991 .id = MT8192_DAI_I2S_1,
1992 .mclk_id = MT8192_I2S1_MCK,
1993 .share_property_name = "i2s1-share",
1994 .share_i2s_id = -1,
1995 },
1996 [DAI_I2S2] = {
1997 .id = MT8192_DAI_I2S_2,
1998 .mclk_id = MT8192_I2S2_MCK,
1999 .share_property_name = "i2s2-share",
2000 .share_i2s_id = -1,
2001 },
2002 [DAI_I2S3] = {
2003 .id = MT8192_DAI_I2S_3,
2004 .mclk_id = MT8192_I2S3_MCK,
2005 .share_property_name = "i2s3-share",
2006 .share_i2s_id = -1,
2007 },
2008 [DAI_I2S5] = {
2009 .id = MT8192_DAI_I2S_5,
2010 .mclk_id = MT8192_I2S5_MCK,
2011 .share_property_name = "i2s5-share",
2012 .share_i2s_id = -1,
2013 },
2014 [DAI_I2S6] = {
2015 .id = MT8192_DAI_I2S_6,
2016 .mclk_id = MT8192_I2S6_MCK,
2017 .share_property_name = "i2s6-share",
2018 .share_i2s_id = -1,
2019 },
2020 [DAI_I2S7] = {
2021 .id = MT8192_DAI_I2S_7,
2022 .mclk_id = MT8192_I2S7_MCK,
2023 .share_property_name = "i2s7-share",
2024 .share_i2s_id = -1,
2025 },
2026 [DAI_I2S8] = {
2027 .id = MT8192_DAI_I2S_8,
2028 .mclk_id = MT8192_I2S8_MCK,
2029 .share_property_name = "i2s8-share",
2030 .share_i2s_id = -1,
2031 },
2032 [DAI_I2S9] = {
2033 .id = MT8192_DAI_I2S_9,
2034 .mclk_id = MT8192_I2S9_MCK,
2035 .share_property_name = "i2s9-share",
2036 .share_i2s_id = -1,
2037 },
2038 };
2039
2040 static int mt8192_dai_i2s_get_share(struct mtk_base_afe *afe)
2041 {
2042 struct mt8192_afe_private *afe_priv = afe->platform_priv;
2043 const struct device_node *of_node = afe->dev->of_node;
2044 const char *of_str;
2045 const char *property_name;
2046 struct mtk_afe_i2s_priv *i2s_priv;
2047 int i;
2048
2049 for (i = 0; i < DAI_I2S_NUM; i++) {
2050 i2s_priv = afe_priv->dai_priv[mt8192_i2s_priv[i].id];
2051 property_name = mt8192_i2s_priv[i].share_property_name;
2052 if (of_property_read_string(of_node, property_name, &of_str))
2053 continue;
2054 i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str);
2055 }
2056
2057 return 0;
2058 }
2059
2060 static int mt8192_dai_i2s_set_priv(struct mtk_base_afe *afe)
2061 {
2062 int i;
2063 int ret;
2064
2065 for (i = 0; i < DAI_I2S_NUM; i++) {
2066 ret = mt8192_dai_set_priv(afe, mt8192_i2s_priv[i].id,
2067 sizeof(struct mtk_afe_i2s_priv),
2068 &mt8192_i2s_priv[i]);
2069 if (ret)
2070 return ret;
2071 }
2072
2073 return 0;
2074 }
2075
2076 int mt8192_dai_i2s_register(struct mtk_base_afe *afe)
2077 {
2078 struct mtk_base_afe_dai *dai;
2079 int ret;
2080
2081 dev_dbg(afe->dev, "%s()\n", __func__);
2082
2083 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
2084 if (!dai)
2085 return -ENOMEM;
2086
2087 list_add(&dai->list, &afe->sub_dais);
2088
2089 dai->dai_drivers = mtk_dai_i2s_driver;
2090 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
2091
2092 dai->controls = mtk_dai_i2s_controls;
2093 dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls);
2094 dai->dapm_widgets = mtk_dai_i2s_widgets;
2095 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
2096 dai->dapm_routes = mtk_dai_i2s_routes;
2097 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
2098
2099 /* set all dai i2s private data */
2100 ret = mt8192_dai_i2s_set_priv(afe);
2101 if (ret)
2102 return ret;
2103
2104 /* parse share i2s */
2105 ret = mt8192_dai_i2s_get_share(afe);
2106 if (ret)
2107 return ret;
2108
2109 return 0;
2110 }
Linux with added FPC-III support