sound/soc/ti/davinci-mcasp.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * ALSA SoC McASP Audio Layer for TI DAVINCI processor
   4  *
   5  * MCASP related definitions
   6  *
   7  * Author: Nirmal Pandey <n-pandey@ti.com>,
   8  *         Suresh Rajashekara <suresh.r@ti.com>
   9  *         Steve Chen <schen@.mvista.com>
  10  *
  11  * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
  12  * Copyright:   (C) 2009  Texas Instruments, India
  13  */
  14
  15 #ifndef DAVINCI_MCASP_H
  16 #define DAVINCI_MCASP_H
  17
  18 /*
  19  * McASP register definitions
  20  */
  21 #define DAVINCI_MCASP_PID_REG           0x00
  22 #define DAVINCI_MCASP_PWREMUMGT_REG     0x04
  23
  24 #define DAVINCI_MCASP_PFUNC_REG         0x10
  25 #define DAVINCI_MCASP_PDIR_REG          0x14
  26 #define DAVINCI_MCASP_PDOUT_REG         0x18
  27 #define DAVINCI_MCASP_PDSET_REG         0x1c
  28
  29 #define DAVINCI_MCASP_PDCLR_REG         0x20
  30
  31 #define DAVINCI_MCASP_TLGC_REG          0x30
  32 #define DAVINCI_MCASP_TLMR_REG          0x34
  33
  34 #define DAVINCI_MCASP_GBLCTL_REG        0x44
  35 #define DAVINCI_MCASP_AMUTE_REG         0x48
  36 #define DAVINCI_MCASP_LBCTL_REG         0x4c
  37
  38 #define DAVINCI_MCASP_TXDITCTL_REG      0x50
  39
  40 #define DAVINCI_MCASP_GBLCTLR_REG       0x60
  41 #define DAVINCI_MCASP_RXMASK_REG        0x64
  42 #define DAVINCI_MCASP_RXFMT_REG         0x68
  43 #define DAVINCI_MCASP_RXFMCTL_REG       0x6c
  44
  45 #define DAVINCI_MCASP_ACLKRCTL_REG      0x70
  46 #define DAVINCI_MCASP_AHCLKRCTL_REG     0x74
  47 #define DAVINCI_MCASP_RXTDM_REG         0x78
  48 #define DAVINCI_MCASP_EVTCTLR_REG       0x7c
  49
  50 #define DAVINCI_MCASP_RXSTAT_REG        0x80
  51 #define DAVINCI_MCASP_RXTDMSLOT_REG     0x84
  52 #define DAVINCI_MCASP_RXCLKCHK_REG      0x88
  53 #define DAVINCI_MCASP_REVTCTL_REG       0x8c
  54
  55 #define DAVINCI_MCASP_GBLCTLX_REG       0xa0
  56 #define DAVINCI_MCASP_TXMASK_REG        0xa4
  57 #define DAVINCI_MCASP_TXFMT_REG         0xa8
  58 #define DAVINCI_MCASP_TXFMCTL_REG       0xac
  59
  60 #define DAVINCI_MCASP_ACLKXCTL_REG      0xb0
  61 #define DAVINCI_MCASP_AHCLKXCTL_REG     0xb4
  62 #define DAVINCI_MCASP_TXTDM_REG         0xb8
  63 #define DAVINCI_MCASP_EVTCTLX_REG       0xbc
  64
  65 #define DAVINCI_MCASP_TXSTAT_REG        0xc0
  66 #define DAVINCI_MCASP_TXTDMSLOT_REG     0xc4
  67 #define DAVINCI_MCASP_TXCLKCHK_REG      0xc8
  68 #define DAVINCI_MCASP_XEVTCTL_REG       0xcc
  69
  70 /* Left(even TDM Slot) Channel Status Register File */
  71 #define DAVINCI_MCASP_DITCSRA_REG       0x100
  72 /* Right(odd TDM slot) Channel Status Register File */
  73 #define DAVINCI_MCASP_DITCSRB_REG       0x118
  74 /* Left(even TDM slot) User Data Register File */
  75 #define DAVINCI_MCASP_DITUDRA_REG       0x130
  76 /* Right(odd TDM Slot) User Data Register File */
  77 #define DAVINCI_MCASP_DITUDRB_REG       0x148
  78
  79 /* Serializer n Control Register */
  80 #define DAVINCI_MCASP_XRSRCTL_BASE_REG  0x180
  81 #define DAVINCI_MCASP_XRSRCTL_REG(n)    (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
  82                                                 (n << 2))
  83
  84 /* Transmit Buffer for Serializer n */
  85 #define DAVINCI_MCASP_TXBUF_REG(n)      (0x200 + (n << 2))
  86 /* Receive Buffer for Serializer n */
  87 #define DAVINCI_MCASP_RXBUF_REG(n)      (0x280 + (n << 2))
  88
  89 /* McASP FIFO Registers */
  90 #define DAVINCI_MCASP_V2_AFIFO_BASE     (0x1010)
  91 #define DAVINCI_MCASP_V3_AFIFO_BASE     (0x1000)
  92
  93 /* FIFO register offsets from AFIFO base */
  94 #define MCASP_WFIFOCTL_OFFSET           (0x0)
  95 #define MCASP_WFIFOSTS_OFFSET           (0x4)
  96 #define MCASP_RFIFOCTL_OFFSET           (0x8)
  97 #define MCASP_RFIFOSTS_OFFSET           (0xc)
  98
  99 /*
 100  * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
 101  *     Register Bits
 102  */
 103 #define MCASP_FREE      BIT(0)
 104 #define MCASP_SOFT      BIT(1)
 105
 106 /*
 107  * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
 108  * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
 109  * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode
 110  * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode
 111  */
 112 #define PIN_BIT_AXR(n)  (n)
 113 #define PIN_BIT_AMUTE   25
 114 #define PIN_BIT_ACLKX   26
 115 #define PIN_BIT_AHCLKX  27
 116 #define PIN_BIT_AFSX    28
 117 #define PIN_BIT_ACLKR   29
 118 #define PIN_BIT_AHCLKR  30
 119 #define PIN_BIT_AFSR    31
 120
 121 /*
 122  * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
 123  */
 124 #define DITEN   BIT(0)  /* Transmit DIT mode enable/disable */
 125 #define VA      BIT(2)
 126 #define VB      BIT(3)
 127
 128 /*
 129  * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
 130  */
 131 #define TXROT(val)      (val)
 132 #define TXSEL           BIT(3)
 133 #define TXSSZ(val)      (val<<4)
 134 #define TXPBIT(val)     (val<<8)
 135 #define TXPAD(val)      (val<<13)
 136 #define TXORD           BIT(15)
 137 #define FSXDLY(val)     (val<<16)
 138
 139 /*
 140  * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
 141  */
 142 #define RXROT(val)      (val)
 143 #define RXSEL           BIT(3)
 144 #define RXSSZ(val)      (val<<4)
 145 #define RXPBIT(val)     (val<<8)
 146 #define RXPAD(val)      (val<<13)
 147 #define RXORD           BIT(15)
 148 #define FSRDLY(val)     (val<<16)
 149
 150 /*
 151  * DAVINCI_MCASP_TXFMCTL_REG -  Transmit Frame Control Register Bits
 152  */
 153 #define FSXPOL          BIT(0)
 154 #define AFSXE           BIT(1)
 155 #define FSXDUR          BIT(4)
 156 #define FSXMOD(val)     (val<<7)
 157
 158 /*
 159  * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
 160  */
 161 #define FSRPOL          BIT(0)
 162 #define AFSRE           BIT(1)
 163 #define FSRDUR          BIT(4)
 164 #define FSRMOD(val)     (val<<7)
 165
 166 /*
 167  * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
 168  */
 169 #define ACLKXDIV(val)   (val)
 170 #define ACLKXE          BIT(5)
 171 #define TX_ASYNC        BIT(6)
 172 #define ACLKXPOL        BIT(7)
 173 #define ACLKXDIV_MASK   0x1f
 174
 175 /*
 176  * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
 177  */
 178 #define ACLKRDIV(val)   (val)
 179 #define ACLKRE          BIT(5)
 180 #define RX_ASYNC        BIT(6)
 181 #define ACLKRPOL        BIT(7)
 182 #define ACLKRDIV_MASK   0x1f
 183
 184 /*
 185  * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
 186  *     Register Bits
 187  */
 188 #define AHCLKXDIV(val)  (val)
 189 #define AHCLKXPOL       BIT(14)
 190 #define AHCLKXE         BIT(15)
 191 #define AHCLKXDIV_MASK  0xfff
 192
 193 /*
 194  * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
 195  *     Register Bits
 196  */
 197 #define AHCLKRDIV(val)  (val)
 198 #define AHCLKRPOL       BIT(14)
 199 #define AHCLKRE         BIT(15)
 200 #define AHCLKRDIV_MASK  0xfff
 201
 202 /*
 203  * DAVINCI_MCASP_XRSRCTL_BASE_REG -  Serializer Control Register Bits
 204  */
 205 #define MODE(val)       (val)
 206 #define DISMOD_3STATE   (0x0)
 207 #define DISMOD_LOW      (0x2 << 2)
 208 #define DISMOD_HIGH     (0x3 << 2)
 209 #define DISMOD_VAL(x)   ((x) << 2)
 210 #define DISMOD_MASK     DISMOD_HIGH
 211 #define TXSTATE         BIT(4)
 212 #define RXSTATE         BIT(5)
 213 #define SRMOD_MASK      3
 214 #define SRMOD_INACTIVE  0
 215
 216 /*
 217  * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
 218  */
 219 #define LBEN            BIT(0)
 220 #define LBORD           BIT(1)
 221 #define LBGENMODE(val)  (val<<2)
 222
 223 /*
 224  * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
 225  */
 226 #define TXTDMS(n)       (1<<n)
 227
 228 /*
 229  * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
 230  */
 231 #define RXTDMS(n)       (1<<n)
 232
 233 /*
 234  * DAVINCI_MCASP_GBLCTL_REG -  Global Control Register Bits
 235  */
 236 #define RXCLKRST        BIT(0)  /* Receiver Clock Divider Reset */
 237 #define RXHCLKRST       BIT(1)  /* Receiver High Frequency Clock Divider */
 238 #define RXSERCLR        BIT(2)  /* Receiver Serializer Clear */
 239 #define RXSMRST         BIT(3)  /* Receiver State Machine Reset */
 240 #define RXFSRST         BIT(4)  /* Frame Sync Generator Reset */
 241 #define TXCLKRST        BIT(8)  /* Transmitter Clock Divider Reset */
 242 #define TXHCLKRST       BIT(9)  /* Transmitter High Frequency Clock Divider*/
 243 #define TXSERCLR        BIT(10) /* Transmit Serializer Clear */
 244 #define TXSMRST         BIT(11) /* Transmitter State Machine Reset */
 245 #define TXFSRST         BIT(12) /* Frame Sync Generator Reset */
 246
 247 /*
 248  * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
 249  * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
 250  */
 251 #define XRERR           BIT(8) /* Transmit/Receive error */
 252 #define XRDATA          BIT(5) /* Transmit/Receive data ready */
 253
 254 /*
 255  * DAVINCI_MCASP_AMUTE_REG -  Mute Control Register Bits
 256  */
 257 #define MUTENA(val)     (val)
 258 #define MUTEINPOL       BIT(2)
 259 #define MUTEINENA       BIT(3)
 260 #define MUTEIN          BIT(4)
 261 #define MUTER           BIT(5)
 262 #define MUTEX           BIT(6)
 263 #define MUTEFSR         BIT(7)
 264 #define MUTEFSX         BIT(8)
 265 #define MUTEBADCLKR     BIT(9)
 266 #define MUTEBADCLKX     BIT(10)
 267 #define MUTERXDMAERR    BIT(11)
 268 #define MUTETXDMAERR    BIT(12)
 269
 270 /*
 271  * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
 272  */
 273 #define RXDATADMADIS    BIT(0)
 274
 275 /*
 276  * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
 277  */
 278 #define TXDATADMADIS    BIT(0)
 279
 280 /*
 281  * DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits
 282  */
 283 #define ROVRN           BIT(0)
 284
 285 /*
 286  * DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits
 287  */
 288 #define XUNDRN          BIT(0)
 289
 290 /*
 291  * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
 292  */
 293 #define FIFO_ENABLE     BIT(16)
 294 #define NUMEVT_MASK     (0xFF << 8)
 295 #define NUMEVT(x)       (((x) & 0xFF) << 8)
 296 #define NUMDMA_MASK     (0xFF)
 297
 298 /* Source of High-frequency transmit/receive clock */
 299 #define MCASP_CLK_HCLK_AHCLK            0 /* AHCLKX/R */
 300 #define MCASP_CLK_HCLK_AUXCLK           1 /* Internal functional clock */
 301
 302 /* clock divider IDs */
 303 #define MCASP_CLKDIV_AUXCLK             0 /* HCLK divider from AUXCLK */
 304 #define MCASP_CLKDIV_BCLK               1 /* BCLK divider from HCLK */
 305 #define MCASP_CLKDIV_BCLK_FS_RATIO      2 /* to set BCLK FS ration */
 306
 307 #endif  /* DAVINCI_MCASP_H */