sound/soc/ti/omap-mcbsp-priv.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * OMAP Multi-Channel Buffered Serial Port
   4  *
   5  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   6  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   7  */
   8
   9 #ifndef __OMAP_MCBSP_PRIV_H__
  10 #define __OMAP_MCBSP_PRIV_H__
  11
  12 #include <linux/platform_data/asoc-ti-mcbsp.h>
  13
  14 #ifdef CONFIG_ARCH_OMAP1
  15 #define mcbsp_omap1()   1
  16 #else
  17 #define mcbsp_omap1()   0
  18 #endif
  19
  20 /* McBSP register numbers. Register address offset = num * reg_step */
  21 enum {
  22         /* Common registers */
  23         OMAP_MCBSP_REG_SPCR2 = 4,
  24         OMAP_MCBSP_REG_SPCR1,
  25         OMAP_MCBSP_REG_RCR2,
  26         OMAP_MCBSP_REG_RCR1,
  27         OMAP_MCBSP_REG_XCR2,
  28         OMAP_MCBSP_REG_XCR1,
  29         OMAP_MCBSP_REG_SRGR2,
  30         OMAP_MCBSP_REG_SRGR1,
  31         OMAP_MCBSP_REG_MCR2,
  32         OMAP_MCBSP_REG_MCR1,
  33         OMAP_MCBSP_REG_RCERA,
  34         OMAP_MCBSP_REG_RCERB,
  35         OMAP_MCBSP_REG_XCERA,
  36         OMAP_MCBSP_REG_XCERB,
  37         OMAP_MCBSP_REG_PCR0,
  38         OMAP_MCBSP_REG_RCERC,
  39         OMAP_MCBSP_REG_RCERD,
  40         OMAP_MCBSP_REG_XCERC,
  41         OMAP_MCBSP_REG_XCERD,
  42         OMAP_MCBSP_REG_RCERE,
  43         OMAP_MCBSP_REG_RCERF,
  44         OMAP_MCBSP_REG_XCERE,
  45         OMAP_MCBSP_REG_XCERF,
  46         OMAP_MCBSP_REG_RCERG,
  47         OMAP_MCBSP_REG_RCERH,
  48         OMAP_MCBSP_REG_XCERG,
  49         OMAP_MCBSP_REG_XCERH,
  50
  51         /* OMAP1-OMAP2420 registers */
  52         OMAP_MCBSP_REG_DRR2 = 0,
  53         OMAP_MCBSP_REG_DRR1,
  54         OMAP_MCBSP_REG_DXR2,
  55         OMAP_MCBSP_REG_DXR1,
  56
  57         /* OMAP2430 and onwards */
  58         OMAP_MCBSP_REG_DRR = 0,
  59         OMAP_MCBSP_REG_DXR = 2,
  60         OMAP_MCBSP_REG_SYSCON = 35,
  61         OMAP_MCBSP_REG_THRSH2,
  62         OMAP_MCBSP_REG_THRSH1,
  63         OMAP_MCBSP_REG_IRQST = 40,
  64         OMAP_MCBSP_REG_IRQEN,
  65         OMAP_MCBSP_REG_WAKEUPEN,
  66         OMAP_MCBSP_REG_XCCR,
  67         OMAP_MCBSP_REG_RCCR,
  68         OMAP_MCBSP_REG_XBUFFSTAT,
  69         OMAP_MCBSP_REG_RBUFFSTAT,
  70         OMAP_MCBSP_REG_SSELCR,
  71 };
  72
  73 /************************** McBSP SPCR1 bit definitions ***********************/
  74 #define RRST                    BIT(0)
  75 #define RRDY                    BIT(1)
  76 #define RFULL                   BIT(2)
  77 #define RSYNC_ERR               BIT(3)
  78 #define RINTM(value)            (((value) & 0x3) << 4)  /* bits 4:5 */
  79 #define ABIS                    BIT(6)
  80 #define DXENA                   BIT(7)
  81 #define CLKSTP(value)           (((value) & 0x3) << 11) /* bits 11:12 */
  82 #define RJUST(value)            (((value) & 0x3) << 13) /* bits 13:14 */
  83 #define ALB                     BIT(15)
  84 #define DLB                     BIT(15)
  85
  86 /************************** McBSP SPCR2 bit definitions ***********************/
  87 #define XRST                    BIT(0)
  88 #define XRDY                    BIT(1)
  89 #define XEMPTY                  BIT(2)
  90 #define XSYNC_ERR               BIT(3)
  91 #define XINTM(value)            (((value) & 0x3) << 4)  /* bits 4:5 */
  92 #define GRST                    BIT(6)
  93 #define FRST                    BIT(7)
  94 #define SOFT                    BIT(8)
  95 #define FREE                    BIT(9)
  96
  97 /************************** McBSP PCR bit definitions *************************/
  98 #define CLKRP                   BIT(0)
  99 #define CLKXP                   BIT(1)
 100 #define FSRP                    BIT(2)
 101 #define FSXP                    BIT(3)
 102 #define DR_STAT                 BIT(4)
 103 #define DX_STAT                 BIT(5)
 104 #define CLKS_STAT               BIT(6)
 105 #define SCLKME                  BIT(7)
 106 #define CLKRM                   BIT(8)
 107 #define CLKXM                   BIT(9)
 108 #define FSRM                    BIT(10)
 109 #define FSXM                    BIT(11)
 110 #define RIOEN                   BIT(12)
 111 #define XIOEN                   BIT(13)
 112 #define IDLE_EN                 BIT(14)
 113
 114 /************************** McBSP RCR1 bit definitions ************************/
 115 #define RWDLEN1(value)          (((value) & 0x7) << 5)  /* Bits 5:7 */
 116 #define RFRLEN1(value)          (((value) & 0x7f) << 8) /* Bits 8:14 */
 117
 118 /************************** McBSP XCR1 bit definitions ************************/
 119 #define XWDLEN1(value)          (((value) & 0x7) << 5)  /* Bits 5:7 */
 120 #define XFRLEN1(value)          (((value) & 0x7f) << 8) /* Bits 8:14 */
 121
 122 /*************************** McBSP RCR2 bit definitions ***********************/
 123 #define RDATDLY(value)          ((value) & 0x3)         /* Bits 0:1 */
 124 #define RFIG                    BIT(2)
 125 #define RCOMPAND(value)         (((value) & 0x3) << 3)  /* Bits 3:4 */
 126 #define RWDLEN2(value)          (((value) & 0x7) << 5)  /* Bits 5:7 */
 127 #define RFRLEN2(value)          (((value) & 0x7f) << 8) /* Bits 8:14 */
 128 #define RPHASE                  BIT(15)
 129
 130 /*************************** McBSP XCR2 bit definitions ***********************/
 131 #define XDATDLY(value)          ((value) & 0x3)         /* Bits 0:1 */
 132 #define XFIG                    BIT(2)
 133 #define XCOMPAND(value)         (((value) & 0x3) << 3)  /* Bits 3:4 */
 134 #define XWDLEN2(value)          (((value) & 0x7) << 5)  /* Bits 5:7 */
 135 #define XFRLEN2(value)          (((value) & 0x7f) << 8) /* Bits 8:14 */
 136 #define XPHASE                  BIT(15)
 137
 138 /************************* McBSP SRGR1 bit definitions ************************/
 139 #define CLKGDV(value)           ((value) & 0x7f)                /* Bits 0:7 */
 140 #define FWID(value)             (((value) & 0xff) << 8) /* Bits 8:15 */
 141
 142 /************************* McBSP SRGR2 bit definitions ************************/
 143 #define FPER(value)             ((value) & 0x0fff)      /* Bits 0:11 */
 144 #define FSGM                    BIT(12)
 145 #define CLKSM                   BIT(13)
 146 #define CLKSP                   BIT(14)
 147 #define GSYNC                   BIT(15)
 148
 149 /************************* McBSP MCR1 bit definitions *************************/
 150 #define RMCM                    BIT(0)
 151 #define RCBLK(value)            (((value) & 0x7) << 2)  /* Bits 2:4 */
 152 #define RPABLK(value)           (((value) & 0x3) << 5)  /* Bits 5:6 */
 153 #define RPBBLK(value)           (((value) & 0x3) << 7)  /* Bits 7:8 */
 154
 155 /************************* McBSP MCR2 bit definitions *************************/
 156 #define XMCM(value)             ((value) & 0x3)         /* Bits 0:1 */
 157 #define XCBLK(value)            (((value) & 0x7) << 2)  /* Bits 2:4 */
 158 #define XPABLK(value)           (((value) & 0x3) << 5)  /* Bits 5:6 */
 159 #define XPBBLK(value)           (((value) & 0x3) << 7)  /* Bits 7:8 */
 160
 161 /*********************** McBSP XCCR bit definitions *************************/
 162 #define XDISABLE                BIT(0)
 163 #define XDMAEN                  BIT(3)
 164 #define DILB                    BIT(5)
 165 #define XFULL_CYCLE             BIT(11)
 166 #define DXENDLY(value)          (((value) & 0x3) << 12) /* Bits 12:13 */
 167 #define PPCONNECT               BIT(14)
 168 #define EXTCLKGATE              BIT(15)
 169
 170 /********************** McBSP RCCR bit definitions *************************/
 171 #define RDISABLE                BIT(0)
 172 #define RDMAEN                  BIT(3)
 173 #define RFULL_CYCLE             BIT(11)
 174
 175 /********************** McBSP SYSCONFIG bit definitions ********************/
 176 #define SOFTRST                 BIT(1)
 177 #define ENAWAKEUP               BIT(2)
 178 #define SIDLEMODE(value)        (((value) & 0x3) << 3)
 179 #define CLOCKACTIVITY(value)    (((value) & 0x3) << 8)
 180
 181 /********************** McBSP DMA operating modes **************************/
 182 #define MCBSP_DMA_MODE_ELEMENT          0
 183 #define MCBSP_DMA_MODE_THRESHOLD        1
 184
 185 /********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/
 186 #define RSYNCERREN              BIT(0)
 187 #define RFSREN                  BIT(1)
 188 #define REOFEN                  BIT(2)
 189 #define RRDYEN                  BIT(3)
 190 #define RUNDFLEN                BIT(4)
 191 #define ROVFLEN                 BIT(5)
 192 #define XSYNCERREN              BIT(7)
 193 #define XFSXEN                  BIT(8)
 194 #define XEOFEN                  BIT(9)
 195 #define XRDYEN                  BIT(10)
 196 #define XUNDFLEN                BIT(11)
 197 #define XOVFLEN                 BIT(12)
 198 #define XEMPTYEOFEN             BIT(14)
 199
 200 /* Clock signal muxing options */
 201 #define CLKR_SRC_CLKR           0 /* CLKR signal is from the CLKR pin */
 202 #define CLKR_SRC_CLKX           1 /* CLKR signal is from the CLKX pin */
 203 #define FSR_SRC_FSR             2 /* FSR signal is from the FSR pin */
 204 #define FSR_SRC_FSX             3 /* FSR signal is from the FSX pin */
 205
 206 /* McBSP functional clock sources */
 207 #define MCBSP_CLKS_PRCM_SRC     0
 208 #define MCBSP_CLKS_PAD_SRC      1
 209
 210 /* we don't do multichannel for now */
 211 struct omap_mcbsp_reg_cfg {
 212         u16 spcr2;
 213         u16 spcr1;
 214         u16 rcr2;
 215         u16 rcr1;
 216         u16 xcr2;
 217         u16 xcr1;
 218         u16 srgr2;
 219         u16 srgr1;
 220         u16 mcr2;
 221         u16 mcr1;
 222         u16 pcr0;
 223         u16 rcerc;
 224         u16 rcerd;
 225         u16 xcerc;
 226         u16 xcerd;
 227         u16 rcere;
 228         u16 rcerf;
 229         u16 xcere;
 230         u16 xcerf;
 231         u16 rcerg;
 232         u16 rcerh;
 233         u16 xcerg;
 234         u16 xcerh;
 235         u16 xccr;
 236         u16 rccr;
 237 };
 238
 239 struct omap_mcbsp_st_data;
 240
 241 struct omap_mcbsp {
 242         struct device *dev;
 243         struct clk *fclk;
 244         spinlock_t lock;
 245         unsigned long phys_base;
 246         unsigned long phys_dma_base;
 247         void __iomem *io_base;
 248         u8 id;
 249         /*
 250          * Flags indicating is the bus already activated and configured by
 251          * another substream
 252          */
 253         int active;
 254         int configured;
 255         u8 free;
 256
 257         int irq;
 258         int rx_irq;
 259         int tx_irq;
 260
 261         /* Protect the field .free, while checking if the mcbsp is in use */
 262         struct omap_mcbsp_platform_data *pdata;
 263         struct omap_mcbsp_st_data *st_data;
 264         struct omap_mcbsp_reg_cfg cfg_regs;
 265         struct snd_dmaengine_dai_dma_data dma_data[2];
 266         unsigned int dma_req[2];
 267         int dma_op_mode;
 268         u16 max_tx_thres;
 269         u16 max_rx_thres;
 270         void *reg_cache;
 271         int reg_cache_size;
 272
 273         unsigned int fmt;
 274         unsigned int in_freq;
 275         unsigned int latency[2];
 276         int clk_div;
 277         int wlen;
 278
 279         struct pm_qos_request pm_qos_req;
 280 };
 281
 282 static inline void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
 283 {
 284         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
 285
 286         if (mcbsp->pdata->reg_size == 2) {
 287                 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
 288                 writew_relaxed((u16)val, addr);
 289         } else {
 290                 ((u32 *)mcbsp->reg_cache)[reg] = val;
 291                 writel_relaxed(val, addr);
 292         }
 293 }
 294
 295 static inline int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg,
 296                                   bool from_cache)
 297 {
 298         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
 299
 300         if (mcbsp->pdata->reg_size == 2) {
 301                 return !from_cache ? readw_relaxed(addr) :
 302                                      ((u16 *)mcbsp->reg_cache)[reg];
 303         } else {
 304                 return !from_cache ? readl_relaxed(addr) :
 305                                      ((u32 *)mcbsp->reg_cache)[reg];
 306         }
 307 }
 308
 309 #define MCBSP_READ(mcbsp, reg) \
 310                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
 311 #define MCBSP_WRITE(mcbsp, reg, val) \
 312                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
 313 #define MCBSP_READ_CACHE(mcbsp, reg) \
 314                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
 315
 316
 317 /* Sidetone specific API */
 318 int omap_mcbsp_st_init(struct platform_device *pdev);
 319 void omap_mcbsp_st_cleanup(struct platform_device *pdev);
 320
 321 int omap_mcbsp_st_start(struct omap_mcbsp *mcbsp);
 322 int omap_mcbsp_st_stop(struct omap_mcbsp *mcbsp);
 323
 324 #endif /* __OMAP_MCBSP_PRIV_H__ */