tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json

   1 [
   2     {
   3         "ArchStdEvent": "LD_SPEC"
   4     },
   5     {
   6         "ArchStdEvent": "ST_SPEC"
   7     },
   8     {
   9         "ArchStdEvent": "LDST_SPEC"
  10     },
  11     {
  12         "ArchStdEvent": "DP_SPEC"
  13     },
  14     {
  15         "ArchStdEvent": "ASE_SPEC"
  16     },
  17     {
  18         "ArchStdEvent": "VFP_SPEC"
  19     },
  20     {
  21         "ArchStdEvent": "PC_WRITE_SPEC"
  22     },
  23     {
  24         "ArchStdEvent": "CRYPTO_SPEC"
  25     },
  26     {
  27         "ArchStdEvent": "ISB_SPEC"
  28     },
  29     {
  30         "ArchStdEvent": "DSB_SPEC"
  31     },
  32     {
  33         "ArchStdEvent": "DMB_SPEC"
  34     },
  35     {
  36         "ArchStdEvent": "RC_LD_SPEC"
  37     },
  38     {
  39         "ArchStdEvent": "RC_ST_SPEC"
  40     },
  41     {
  42         "PublicDescription": "Instruction architecturally executed, software increment",
  43         "EventCode": "0x00",
  44         "EventName": "SW_INCR",
  45         "BriefDescription": "Software increment"
  46     },
  47     {
  48         "PublicDescription": "Instruction architecturally executed",
  49         "EventCode": "0x08",
  50         "EventName": "INST_RETIRED",
  51         "BriefDescription": "Instruction retired"
  52     },
  53     {
  54         "PublicDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR",
  55         "EventCode": "0x0b",
  56         "EventName": "CID_WRITE_RETIRED",
  57         "BriefDescription": "Write to CONTEXTIDR"
  58     },
  59     {
  60         "PublicDescription": "Operation speculatively executed",
  61         "EventCode": "0x1b",
  62         "EventName": "INST_SPEC",
  63         "BriefDescription": "Speculatively executed"
  64     },
  65     {
  66         "PublicDescription": "Instruction architecturally executed (condition check pass), write to TTBR",
  67         "EventCode": "0x1c",
  68         "EventName": "TTBR_WRITE_RETIRED",
  69         "BriefDescription": "Instruction executed, TTBR write"
  70     },
  71     {
  72         "PublicDescription": "Instruction architecturally executed, branch. This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches",
  73         "EventCode": "0x21",
  74         "EventName": "BR_RETIRED",
  75         "BriefDescription": "Branch retired"
  76     },
  77     {
  78         "PublicDescription": "Instruction architecturally executed, mispredicted branch. This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush",
  79         "EventCode": "0x22",
  80         "EventName": "BR_MISPRED_RETIRED",
  81         "BriefDescription": "Mispredicted branch retired"
  82     },
  83     {
  84         "PublicDescription": "Operation speculatively executed, NOP",
  85         "EventCode": "0x100",
  86         "EventName": "NOP_SPEC",
  87         "BriefDescription": "Speculatively executed, NOP"
  88     }
  89 ]