tools/perf/pmu-events/arch/x86/broadwellde/memory.json

   1 [
   2     {
   3         "EventCode": "0x05",
   4         "UMask": "0x1",
   5         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
   6         "Counter": "0,1,2,3",
   7         "EventName": "MISALIGN_MEM_REF.LOADS",
   8         "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
   9         "SampleAfterValue": "2000003",
  10         "CounterHTOff": "0,1,2,3,4,5,6,7"
  11     },
  12     {
  13         "EventCode": "0x05",
  14         "UMask": "0x2",
  15         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
  16         "Counter": "0,1,2,3",
  17         "EventName": "MISALIGN_MEM_REF.STORES",
  18         "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
  19         "SampleAfterValue": "2000003",
  20         "CounterHTOff": "0,1,2,3,4,5,6,7"
  21     },
  22     {
  23         "EventCode": "0x54",
  24         "UMask": "0x1",
  25         "BriefDescription": "Number of times a TSX line had a cache conflict",
  26         "Counter": "0,1,2,3",
  27         "EventName": "TX_MEM.ABORT_CONFLICT",
  28         "PublicDescription": "Number of times a TSX line had a cache conflict.",
  29         "SampleAfterValue": "2000003",
  30         "CounterHTOff": "0,1,2,3,4,5,6,7"
  31     },
  32     {
  33         "EventCode": "0x54",
  34         "UMask": "0x2",
  35         "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
  36         "Counter": "0,1,2,3",
  37         "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
  38         "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
  39         "SampleAfterValue": "2000003",
  40         "CounterHTOff": "0,1,2,3,4,5,6,7"
  41     },
  42     {
  43         "EventCode": "0x54",
  44         "UMask": "0x4",
  45         "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
  46         "Counter": "0,1,2,3",
  47         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
  48         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
  49         "SampleAfterValue": "2000003",
  50         "CounterHTOff": "0,1,2,3,4,5,6,7"
  51     },
  52     {
  53         "EventCode": "0x54",
  54         "UMask": "0x8",
  55         "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
  56         "Counter": "0,1,2,3",
  57         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
  58         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
  59         "SampleAfterValue": "2000003",
  60         "CounterHTOff": "0,1,2,3,4,5,6,7"
  61     },
  62     {
  63         "EventCode": "0x54",
  64         "UMask": "0x10",
  65         "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
  66         "Counter": "0,1,2,3",
  67         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
  68         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
  69         "SampleAfterValue": "2000003",
  70         "CounterHTOff": "0,1,2,3,4,5,6,7"
  71     },
  72     {
  73         "EventCode": "0x54",
  74         "UMask": "0x20",
  75         "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
  76         "Counter": "0,1,2,3",
  77         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
  78         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
  79         "SampleAfterValue": "2000003",
  80         "CounterHTOff": "0,1,2,3,4,5,6,7"
  81     },
  82     {
  83         "EventCode": "0x54",
  84         "UMask": "0x40",
  85         "BriefDescription": "Number of times we could not allocate Lock Buffer",
  86         "Counter": "0,1,2,3",
  87         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
  88         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
  89         "SampleAfterValue": "2000003",
  90         "CounterHTOff": "0,1,2,3,4,5,6,7"
  91     },
  92     {
  93         "EventCode": "0x5d",
  94         "UMask": "0x1",
  95         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
  96         "Counter": "0,1,2,3",
  97         "EventName": "TX_EXEC.MISC1",
  98         "SampleAfterValue": "2000003",
  99         "CounterHTOff": "0,1,2,3,4,5,6,7"
 100     },
 101     {
 102         "EventCode": "0x5d",
 103         "UMask": "0x2",
 104         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
 105         "Counter": "0,1,2,3",
 106         "EventName": "TX_EXEC.MISC2",
 107         "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction.",
 108         "SampleAfterValue": "2000003",
 109         "CounterHTOff": "0,1,2,3,4,5,6,7"
 110     },
 111     {
 112         "EventCode": "0x5d",
 113         "UMask": "0x4",
 114         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
 115         "Counter": "0,1,2,3",
 116         "EventName": "TX_EXEC.MISC3",
 117         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
 118         "SampleAfterValue": "2000003",
 119         "CounterHTOff": "0,1,2,3,4,5,6,7"
 120     },
 121     {
 122         "EventCode": "0x5d",
 123         "UMask": "0x8",
 124         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
 125         "Counter": "0,1,2,3",
 126         "EventName": "TX_EXEC.MISC4",
 127         "PublicDescription": "RTM region detected inside HLE.",
 128         "SampleAfterValue": "2000003",
 129         "CounterHTOff": "0,1,2,3,4,5,6,7"
 130     },
 131     {
 132         "EventCode": "0x5d",
 133         "UMask": "0x10",
 134         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
 135         "Counter": "0,1,2,3",
 136         "EventName": "TX_EXEC.MISC5",
 137         "SampleAfterValue": "2000003",
 138         "CounterHTOff": "0,1,2,3,4,5,6,7"
 139     },
 140     {
 141         "EventCode": "0xC3",
 142         "UMask": "0x2",
 143         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
 144         "Counter": "0,1,2,3",
 145         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
 146         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
 147         "SampleAfterValue": "100003",
 148         "CounterHTOff": "0,1,2,3,4,5,6,7"
 149     },
 150     {
 151         "EventCode": "0xc8",
 152         "UMask": "0x1",
 153         "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
 154         "Counter": "0,1,2,3",
 155         "EventName": "HLE_RETIRED.START",
 156         "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
 157         "SampleAfterValue": "2000003",
 158         "CounterHTOff": "0,1,2,3,4,5,6,7"
 159     },
 160     {
 161         "EventCode": "0xc8",
 162         "UMask": "0x2",
 163         "BriefDescription": "Number of times HLE commit succeeded",
 164         "Counter": "0,1,2,3",
 165         "EventName": "HLE_RETIRED.COMMIT",
 166         "PublicDescription": "Number of times HLE commit succeeded.",
 167         "SampleAfterValue": "2000003",
 168         "CounterHTOff": "0,1,2,3,4,5,6,7"
 169     },
 170     {
 171         "EventCode": "0xc8",
 172         "UMask": "0x4",
 173         "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
 174         "PEBS": "1",
 175         "Counter": "0,1,2,3",
 176         "EventName": "HLE_RETIRED.ABORTED",
 177         "PublicDescription": "Number of times HLE abort was triggered (PEBS).",
 178         "SampleAfterValue": "2000003",
 179         "CounterHTOff": "0,1,2,3,4,5,6,7"
 180     },
 181     {
 182         "EventCode": "0xc8",
 183         "UMask": "0x8",
 184         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
 185         "Counter": "0,1,2,3",
 186         "EventName": "HLE_RETIRED.ABORTED_MISC1",
 187         "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
 188         "SampleAfterValue": "2000003",
 189         "CounterHTOff": "0,1,2,3,4,5,6,7"
 190     },
 191     {
 192         "EventCode": "0xc8",
 193         "UMask": "0x10",
 194         "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
 195         "Counter": "0,1,2,3",
 196         "EventName": "HLE_RETIRED.ABORTED_MISC2",
 197         "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
 198         "SampleAfterValue": "2000003",
 199         "CounterHTOff": "0,1,2,3,4,5,6,7"
 200     },
 201     {
 202         "EventCode": "0xc8",
 203         "UMask": "0x20",
 204         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
 205         "Counter": "0,1,2,3",
 206         "EventName": "HLE_RETIRED.ABORTED_MISC3",
 207         "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
 208         "SampleAfterValue": "2000003",
 209         "CounterHTOff": "0,1,2,3,4,5,6,7"
 210     },
 211     {
 212         "EventCode": "0xc8",
 213         "UMask": "0x40",
 214         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
 215         "Counter": "0,1,2,3",
 216         "EventName": "HLE_RETIRED.ABORTED_MISC4",
 217         "PublicDescription": "Number of times HLE caused a fault.",
 218         "SampleAfterValue": "2000003",
 219         "CounterHTOff": "0,1,2,3,4,5,6,7"
 220     },
 221     {
 222         "EventCode": "0xc8",
 223         "UMask": "0x80",
 224         "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
 225         "Counter": "0,1,2,3",
 226         "EventName": "HLE_RETIRED.ABORTED_MISC5",
 227         "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
 228         "SampleAfterValue": "2000003",
 229         "CounterHTOff": "0,1,2,3,4,5,6,7"
 230     },
 231     {
 232         "EventCode": "0xc9",
 233         "UMask": "0x1",
 234         "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
 235         "Counter": "0,1,2,3",
 236         "EventName": "RTM_RETIRED.START",
 237         "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
 238         "SampleAfterValue": "2000003",
 239         "CounterHTOff": "0,1,2,3"
 240     },
 241     {
 242         "EventCode": "0xc9",
 243         "UMask": "0x2",
 244         "BriefDescription": "Number of times RTM commit succeeded",
 245         "Counter": "0,1,2,3",
 246         "EventName": "RTM_RETIRED.COMMIT",
 247         "PublicDescription": "Number of times RTM commit succeeded.",
 248         "SampleAfterValue": "2000003",
 249         "CounterHTOff": "0,1,2,3"
 250     },
 251     {
 252         "EventCode": "0xc9",
 253         "UMask": "0x4",
 254         "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
 255         "PEBS": "1",
 256         "Counter": "0,1,2,3",
 257         "EventName": "RTM_RETIRED.ABORTED",
 258         "PublicDescription": "Number of times RTM abort was triggered (PEBS).",
 259         "SampleAfterValue": "2000003",
 260         "CounterHTOff": "0,1,2,3"
 261     },
 262     {
 263         "EventCode": "0xc9",
 264         "UMask": "0x8",
 265         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
 266         "Counter": "0,1,2,3",
 267         "EventName": "RTM_RETIRED.ABORTED_MISC1",
 268         "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
 269         "SampleAfterValue": "2000003",
 270         "CounterHTOff": "0,1,2,3"
 271     },
 272     {
 273         "EventCode": "0xc9",
 274         "UMask": "0x10",
 275         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
 276         "Counter": "0,1,2,3",
 277         "EventName": "RTM_RETIRED.ABORTED_MISC2",
 278         "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
 279         "SampleAfterValue": "2000003",
 280         "CounterHTOff": "0,1,2,3"
 281     },
 282     {
 283         "EventCode": "0xc9",
 284         "UMask": "0x20",
 285         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
 286         "Counter": "0,1,2,3",
 287         "EventName": "RTM_RETIRED.ABORTED_MISC3",
 288         "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
 289         "SampleAfterValue": "2000003",
 290         "CounterHTOff": "0,1,2,3"
 291     },
 292     {
 293         "EventCode": "0xc9",
 294         "UMask": "0x40",
 295         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
 296         "Counter": "0,1,2,3",
 297         "EventName": "RTM_RETIRED.ABORTED_MISC4",
 298         "PublicDescription": "Number of times a RTM caused a fault.",
 299         "SampleAfterValue": "2000003",
 300         "CounterHTOff": "0,1,2,3"
 301     },
 302     {
 303         "EventCode": "0xc9",
 304         "UMask": "0x80",
 305         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
 306         "Counter": "0,1,2,3",
 307         "EventName": "RTM_RETIRED.ABORTED_MISC5",
 308         "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
 309         "SampleAfterValue": "2000003",
 310         "CounterHTOff": "0,1,2,3"
 311     },
 312     {
 313         "EventCode": "0xCD",
 314         "UMask": "0x1",
 315         "BriefDescription": "Loads with latency value being above 4",
 316         "PEBS": "2",
 317         "MSRValue": "0x4",
 318         "Counter": "3",
 319         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
 320         "MSRIndex": "0x3F6",
 321         "Errata": "BDM100, BDM35",
 322         "PublicDescription": "This event counts loads with latency value being above four.",
 323         "TakenAlone": "1",
 324         "SampleAfterValue": "100003",
 325         "CounterHTOff": "3"
 326     },
 327     {
 328         "EventCode": "0xCD",
 329         "UMask": "0x1",
 330         "BriefDescription": "Loads with latency value being above 8",
 331         "PEBS": "2",
 332         "MSRValue": "0x8",
 333         "Counter": "3",
 334         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
 335         "MSRIndex": "0x3F6",
 336         "Errata": "BDM100, BDM35",
 337         "PublicDescription": "This event counts loads with latency value being above eight.",
 338         "TakenAlone": "1",
 339         "SampleAfterValue": "50021",
 340         "CounterHTOff": "3"
 341     },
 342     {
 343         "EventCode": "0xCD",
 344         "UMask": "0x1",
 345         "BriefDescription": "Loads with latency value being above 16",
 346         "PEBS": "2",
 347         "MSRValue": "0x10",
 348         "Counter": "3",
 349         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
 350         "MSRIndex": "0x3F6",
 351         "Errata": "BDM100, BDM35",
 352         "PublicDescription": "This event counts loads with latency value being above 16.",
 353         "TakenAlone": "1",
 354         "SampleAfterValue": "20011",
 355         "CounterHTOff": "3"
 356     },
 357     {
 358         "EventCode": "0xCD",
 359         "UMask": "0x1",
 360         "BriefDescription": "Loads with latency value being above 32",
 361         "PEBS": "2",
 362         "MSRValue": "0x20",
 363         "Counter": "3",
 364         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
 365         "MSRIndex": "0x3F6",
 366         "Errata": "BDM100, BDM35",
 367         "PublicDescription": "This event counts loads with latency value being above 32.",
 368         "TakenAlone": "1",
 369         "SampleAfterValue": "100007",
 370         "CounterHTOff": "3"
 371     },
 372     {
 373         "EventCode": "0xCD",
 374         "UMask": "0x1",
 375         "BriefDescription": "Loads with latency value being above 64",
 376         "PEBS": "2",
 377         "MSRValue": "0x40",
 378         "Counter": "3",
 379         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
 380         "MSRIndex": "0x3F6",
 381         "Errata": "BDM100, BDM35",
 382         "PublicDescription": "This event counts loads with latency value being above 64.",
 383         "TakenAlone": "1",
 384         "SampleAfterValue": "2003",
 385         "CounterHTOff": "3"
 386     },
 387     {
 388         "EventCode": "0xCD",
 389         "UMask": "0x1",
 390         "BriefDescription": "Loads with latency value being above 128",
 391         "PEBS": "2",
 392         "MSRValue": "0x80",
 393         "Counter": "3",
 394         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
 395         "MSRIndex": "0x3F6",
 396         "Errata": "BDM100, BDM35",
 397         "PublicDescription": "This event counts loads with latency value being above 128.",
 398         "TakenAlone": "1",
 399         "SampleAfterValue": "1009",
 400         "CounterHTOff": "3"
 401     },
 402     {
 403         "EventCode": "0xCD",
 404         "UMask": "0x1",
 405         "BriefDescription": "Loads with latency value being above 256",
 406         "PEBS": "2",
 407         "MSRValue": "0x100",
 408         "Counter": "3",
 409         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
 410         "MSRIndex": "0x3F6",
 411         "Errata": "BDM100, BDM35",
 412         "PublicDescription": "This event counts loads with latency value being above 256.",
 413         "TakenAlone": "1",
 414         "SampleAfterValue": "503",
 415         "CounterHTOff": "3"
 416     },
 417     {
 418         "EventCode": "0xCD",
 419         "UMask": "0x1",
 420         "BriefDescription": "Loads with latency value being above 512",
 421         "PEBS": "2",
 422         "MSRValue": "0x200",
 423         "Counter": "3",
 424         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
 425         "MSRIndex": "0x3F6",
 426         "Errata": "BDM100, BDM35",
 427         "PublicDescription": "This event counts loads with latency value being above 512.",
 428         "TakenAlone": "1",
 429         "SampleAfterValue": "101",
 430         "CounterHTOff": "3"
 431     }
 432 ]