tools/perf/pmu-events/arch/x86/haswell/floating-point.json

   1 [
   2     {
   3         "PEBS": "1",
   4         "PublicDescription": "",
   5         "EventCode": "0xC1",
   6         "Counter": "0,1,2,3",
   7         "UMask": "0x8",
   8         "Errata": "HSD56, HSM57",
   9         "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
  10         "SampleAfterValue": "100003",
  11         "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable",
  12         "CounterHTOff": "0,1,2,3,4,5,6,7"
  13     },
  14     {
  15         "PEBS": "1",
  16         "PublicDescription": "",
  17         "EventCode": "0xC1",
  18         "Counter": "0,1,2,3",
  19         "UMask": "0x10",
  20         "Errata": "HSD56, HSM57",
  21         "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
  22         "SampleAfterValue": "100003",
  23         "BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable",
  24         "CounterHTOff": "0,1,2,3,4,5,6,7"
  25     },
  26     {
  27         "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
  28         "EventCode": "0xC6",
  29         "Counter": "0,1,2,3",
  30         "UMask": "0x7",
  31         "EventName": "AVX_INSTS.ALL",
  32         "SampleAfterValue": "2000003",
  33         "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores.  May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
  34         "CounterHTOff": "0,1,2,3,4,5,6,7"
  35     },
  36     {
  37         "PEBS": "1",
  38         "PublicDescription": "",
  39         "EventCode": "0xCA",
  40         "Counter": "0,1,2,3",
  41         "UMask": "0x2",
  42         "EventName": "FP_ASSIST.X87_OUTPUT",
  43         "SampleAfterValue": "100003",
  44         "BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result",
  45         "CounterHTOff": "0,1,2,3,4,5,6,7"
  46     },
  47     {
  48         "PEBS": "1",
  49         "PublicDescription": "",
  50         "EventCode": "0xCA",
  51         "Counter": "0,1,2,3",
  52         "UMask": "0x4",
  53         "EventName": "FP_ASSIST.X87_INPUT",
  54         "SampleAfterValue": "100003",
  55         "BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand",
  56         "CounterHTOff": "0,1,2,3,4,5,6,7"
  57     },
  58     {
  59         "PEBS": "1",
  60         "PublicDescription": "",
  61         "EventCode": "0xCA",
  62         "Counter": "0,1,2,3",
  63         "UMask": "0x8",
  64         "EventName": "FP_ASSIST.SIMD_OUTPUT",
  65         "SampleAfterValue": "100003",
  66         "BriefDescription": "SSE* FP micro-code assist when output value is invalid.",
  67         "CounterHTOff": "0,1,2,3,4,5,6,7"
  68     },
  69     {
  70         "PEBS": "1",
  71         "PublicDescription": "",
  72         "EventCode": "0xCA",
  73         "Counter": "0,1,2,3",
  74         "UMask": "0x10",
  75         "EventName": "FP_ASSIST.SIMD_INPUT",
  76         "SampleAfterValue": "100003",
  77         "BriefDescription": "Any input SSE* FP Assist",
  78         "CounterHTOff": "0,1,2,3,4,5,6,7"
  79     },
  80     {
  81         "PEBS": "1",
  82         "PublicDescription": "",
  83         "EventCode": "0xCA",
  84         "Counter": "0,1,2,3",
  85         "UMask": "0x1e",
  86         "EventName": "FP_ASSIST.ANY",
  87         "SampleAfterValue": "100003",
  88         "BriefDescription": "Counts any FP_ASSIST umask was incrementing",
  89         "CounterMask": "1",
  90         "CounterHTOff": "0,1,2,3"
  91     }
  92 ]