tools/perf/pmu-events/arch/x86/westmereex/other.json

   1 [
   2     {
   3         "EventCode": "0xE8",
   4         "Counter": "0,1,2,3",
   5         "UMask": "0x1",
   6         "EventName": "BPU_CLEARS.EARLY",
   7         "SampleAfterValue": "2000000",
   8         "BriefDescription": "Early Branch Prediciton Unit clears"
   9     },
  10     {
  11         "EventCode": "0xE8",
  12         "Counter": "0,1,2,3",
  13         "UMask": "0x2",
  14         "EventName": "BPU_CLEARS.LATE",
  15         "SampleAfterValue": "2000000",
  16         "BriefDescription": "Late Branch Prediction Unit clears"
  17     },
  18     {
  19         "EventCode": "0xE5",
  20         "Counter": "0,1,2,3",
  21         "UMask": "0x1",
  22         "EventName": "BPU_MISSED_CALL_RET",
  23         "SampleAfterValue": "2000000",
  24         "BriefDescription": "Branch prediction unit missed call or return"
  25     },
  26     {
  27         "EventCode": "0xD5",
  28         "Counter": "0,1,2,3",
  29         "UMask": "0x1",
  30         "EventName": "ES_REG_RENAMES",
  31         "SampleAfterValue": "2000000",
  32         "BriefDescription": "ES segment renames"
  33     },
  34     {
  35         "EventCode": "0x6C",
  36         "Counter": "0,1,2,3",
  37         "UMask": "0x1",
  38         "EventName": "IO_TRANSACTIONS",
  39         "SampleAfterValue": "2000000",
  40         "BriefDescription": "I/O transactions"
  41     },
  42     {
  43         "EventCode": "0x80",
  44         "Counter": "0,1,2,3",
  45         "UMask": "0x4",
  46         "EventName": "L1I.CYCLES_STALLED",
  47         "SampleAfterValue": "2000000",
  48         "BriefDescription": "L1I instruction fetch stall cycles"
  49     },
  50     {
  51         "EventCode": "0x80",
  52         "Counter": "0,1,2,3",
  53         "UMask": "0x1",
  54         "EventName": "L1I.HITS",
  55         "SampleAfterValue": "2000000",
  56         "BriefDescription": "L1I instruction fetch hits"
  57     },
  58     {
  59         "EventCode": "0x80",
  60         "Counter": "0,1,2,3",
  61         "UMask": "0x2",
  62         "EventName": "L1I.MISSES",
  63         "SampleAfterValue": "2000000",
  64         "BriefDescription": "L1I instruction fetch misses"
  65     },
  66     {
  67         "EventCode": "0x80",
  68         "Counter": "0,1,2,3",
  69         "UMask": "0x3",
  70         "EventName": "L1I.READS",
  71         "SampleAfterValue": "2000000",
  72         "BriefDescription": "L1I Instruction fetches"
  73     },
  74     {
  75         "EventCode": "0x82",
  76         "Counter": "0,1,2,3",
  77         "UMask": "0x1",
  78         "EventName": "LARGE_ITLB.HIT",
  79         "SampleAfterValue": "200000",
  80         "BriefDescription": "Large ITLB hit"
  81     },
  82     {
  83         "EventCode": "0x3",
  84         "Counter": "0,1,2,3",
  85         "UMask": "0x2",
  86         "EventName": "LOAD_BLOCK.OVERLAP_STORE",
  87         "SampleAfterValue": "200000",
  88         "BriefDescription": "Loads that partially overlap an earlier store"
  89     },
  90     {
  91         "EventCode": "0x13",
  92         "Counter": "0,1,2,3",
  93         "UMask": "0x7",
  94         "EventName": "LOAD_DISPATCH.ANY",
  95         "SampleAfterValue": "2000000",
  96         "BriefDescription": "All loads dispatched"
  97     },
  98     {
  99         "EventCode": "0x13",
 100         "Counter": "0,1,2,3",
 101         "UMask": "0x4",
 102         "EventName": "LOAD_DISPATCH.MOB",
 103         "SampleAfterValue": "2000000",
 104         "BriefDescription": "Loads dispatched from the MOB"
 105     },
 106     {
 107         "EventCode": "0x13",
 108         "Counter": "0,1,2,3",
 109         "UMask": "0x1",
 110         "EventName": "LOAD_DISPATCH.RS",
 111         "SampleAfterValue": "2000000",
 112         "BriefDescription": "Loads dispatched that bypass the MOB"
 113     },
 114     {
 115         "EventCode": "0x13",
 116         "Counter": "0,1,2,3",
 117         "UMask": "0x2",
 118         "EventName": "LOAD_DISPATCH.RS_DELAYED",
 119         "SampleAfterValue": "2000000",
 120         "BriefDescription": "Loads dispatched from stage 305"
 121     },
 122     {
 123         "EventCode": "0x7",
 124         "Counter": "0,1,2,3",
 125         "UMask": "0x1",
 126         "EventName": "PARTIAL_ADDRESS_ALIAS",
 127         "SampleAfterValue": "200000",
 128         "BriefDescription": "False dependencies due to partial address aliasing"
 129     },
 130     {
 131         "EventCode": "0xD2",
 132         "Counter": "0,1,2,3",
 133         "UMask": "0xf",
 134         "EventName": "RAT_STALLS.ANY",
 135         "SampleAfterValue": "2000000",
 136         "BriefDescription": "All RAT stall cycles"
 137     },
 138     {
 139         "EventCode": "0xD2",
 140         "Counter": "0,1,2,3",
 141         "UMask": "0x1",
 142         "EventName": "RAT_STALLS.FLAGS",
 143         "SampleAfterValue": "2000000",
 144         "BriefDescription": "Flag stall cycles"
 145     },
 146     {
 147         "EventCode": "0xD2",
 148         "Counter": "0,1,2,3",
 149         "UMask": "0x2",
 150         "EventName": "RAT_STALLS.REGISTERS",
 151         "SampleAfterValue": "2000000",
 152         "BriefDescription": "Partial register stall cycles"
 153     },
 154     {
 155         "EventCode": "0xD2",
 156         "Counter": "0,1,2,3",
 157         "UMask": "0x4",
 158         "EventName": "RAT_STALLS.ROB_READ_PORT",
 159         "SampleAfterValue": "2000000",
 160         "BriefDescription": "ROB read port stalls cycles"
 161     },
 162     {
 163         "EventCode": "0xD2",
 164         "Counter": "0,1,2,3",
 165         "UMask": "0x8",
 166         "EventName": "RAT_STALLS.SCOREBOARD",
 167         "SampleAfterValue": "2000000",
 168         "BriefDescription": "Scoreboard stall cycles"
 169     },
 170     {
 171         "EventCode": "0x4",
 172         "Counter": "0,1,2,3",
 173         "UMask": "0x7",
 174         "EventName": "SB_DRAIN.ANY",
 175         "SampleAfterValue": "200000",
 176         "BriefDescription": "All Store buffer stall cycles"
 177     },
 178     {
 179         "EventCode": "0xD4",
 180         "Counter": "0,1,2,3",
 181         "UMask": "0x1",
 182         "EventName": "SEG_RENAME_STALLS",
 183         "SampleAfterValue": "2000000",
 184         "BriefDescription": "Segment rename stall cycles"
 185     },
 186     {
 187         "EventCode": "0xB8",
 188         "Counter": "0,1,2,3",
 189         "UMask": "0x1",
 190         "EventName": "SNOOP_RESPONSE.HIT",
 191         "SampleAfterValue": "100000",
 192         "BriefDescription": "Thread responded HIT to snoop"
 193     },
 194     {
 195         "EventCode": "0xB8",
 196         "Counter": "0,1,2,3",
 197         "UMask": "0x2",
 198         "EventName": "SNOOP_RESPONSE.HITE",
 199         "SampleAfterValue": "100000",
 200         "BriefDescription": "Thread responded HITE to snoop"
 201     },
 202     {
 203         "EventCode": "0xB8",
 204         "Counter": "0,1,2,3",
 205         "UMask": "0x4",
 206         "EventName": "SNOOP_RESPONSE.HITM",
 207         "SampleAfterValue": "100000",
 208         "BriefDescription": "Thread responded HITM to snoop"
 209     },
 210     {
 211         "EventCode": "0xB4",
 212         "Counter": "0,1,2,3",
 213         "UMask": "0x4",
 214         "EventName": "SNOOPQ_REQUESTS.CODE",
 215         "SampleAfterValue": "100000",
 216         "BriefDescription": "Snoop code requests"
 217     },
 218     {
 219         "EventCode": "0xB4",
 220         "Counter": "0,1,2,3",
 221         "UMask": "0x1",
 222         "EventName": "SNOOPQ_REQUESTS.DATA",
 223         "SampleAfterValue": "100000",
 224         "BriefDescription": "Snoop data requests"
 225     },
 226     {
 227         "EventCode": "0xB4",
 228         "Counter": "0,1,2,3",
 229         "UMask": "0x2",
 230         "EventName": "SNOOPQ_REQUESTS.INVALIDATE",
 231         "SampleAfterValue": "100000",
 232         "BriefDescription": "Snoop invalidate requests"
 233     },
 234     {
 235         "EventCode": "0xB3",
 236         "UMask": "0x4",
 237         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
 238         "SampleAfterValue": "2000000",
 239         "BriefDescription": "Outstanding snoop code requests"
 240     },
 241     {
 242         "EventCode": "0xB3",
 243         "UMask": "0x4",
 244         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
 245         "SampleAfterValue": "2000000",
 246         "BriefDescription": "Cycles snoop code requests queued",
 247         "CounterMask": "1"
 248     },
 249     {
 250         "EventCode": "0xB3",
 251         "UMask": "0x1",
 252         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
 253         "SampleAfterValue": "2000000",
 254         "BriefDescription": "Outstanding snoop data requests"
 255     },
 256     {
 257         "EventCode": "0xB3",
 258         "UMask": "0x1",
 259         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
 260         "SampleAfterValue": "2000000",
 261         "BriefDescription": "Cycles snoop data requests queued",
 262         "CounterMask": "1"
 263     },
 264     {
 265         "EventCode": "0xB3",
 266         "UMask": "0x2",
 267         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
 268         "SampleAfterValue": "2000000",
 269         "BriefDescription": "Outstanding snoop invalidate requests"
 270     },
 271     {
 272         "EventCode": "0xB3",
 273         "UMask": "0x2",
 274         "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
 275         "SampleAfterValue": "2000000",
 276         "BriefDescription": "Cycles snoop invalidate requests queued",
 277         "CounterMask": "1"
 278     },
 279     {
 280         "EventCode": "0xF6",
 281         "Counter": "0,1,2,3",
 282         "UMask": "0x1",
 283         "EventName": "SQ_FULL_STALL_CYCLES",
 284         "SampleAfterValue": "2000000",
 285         "BriefDescription": "Super Queue full stall cycles"
 286     }
 287 ]