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ipv6: reallocate addrconf router for ipv6 address when lo device up
[linux/fpc-iii.git] / drivers / hwmon / w83627ehf.c
blob88effda191984cd24aea82cc78d01a762473ba54
1 /*
2 * w83627ehf - Driver for the hardware monitoring functionality of
3 * the Winbond W83627EHF Super-I/O chip
4 * Copyright (C) 2005-2011 Jean Delvare <khali@linux-fr.org>
5 * Copyright (C) 2006 Yuan Mu (Winbond),
6 * Rudolf Marek <r.marek@assembler.cz>
7 * David Hubbard <david.c.hubbard@gmail.com>
8 * Daniel J Blueman <daniel.blueman@gmail.com>
9 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
10 *
11 * Shamelessly ripped from the w83627hf driver
12 * Copyright (C) 2003 Mark Studebaker
13 *
14 * Thanks to Leon Moonen, Steve Cliffe and Grant Coady for their help
15 * in testing and debugging this driver.
16 *
17 * This driver also supports the W83627EHG, which is the lead-free
18 * version of the W83627EHF.
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 * Supports the following chips:
35 *
36 * Chip #vin #fan #pwm #temp chip IDs man ID
37 * w83627ehf 10 5 4 3 0x8850 0x88 0x5ca3
38 * 0x8860 0xa1
39 * w83627dhg 9 5 4 3 0xa020 0xc1 0x5ca3
40 * w83627dhg-p 9 5 4 3 0xb070 0xc1 0x5ca3
41 * w83627uhg 8 2 2 3 0xa230 0xc1 0x5ca3
42 * w83667hg 9 5 3 3 0xa510 0xc1 0x5ca3
43 * w83667hg-b 9 5 3 4 0xb350 0xc1 0x5ca3
44 * nct6775f 9 4 3 9 0xb470 0xc1 0x5ca3
45 * nct6776f 9 5 3 9 0xC330 0xc1 0x5ca3
46 */
47
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50 #include <linux/module.h>
51 #include <linux/init.h>
52 #include <linux/slab.h>
53 #include <linux/jiffies.h>
54 #include <linux/platform_device.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
57 #include <linux/hwmon-vid.h>
58 #include <linux/err.h>
59 #include <linux/mutex.h>
60 #include <linux/acpi.h>
61 #include <linux/io.h>
62 #include "lm75.h"
63
64 enum kinds {
65 w83627ehf, w83627dhg, w83627dhg_p, w83627uhg,
66 w83667hg, w83667hg_b, nct6775, nct6776,
67 };
68
69 /* used to set data->name = w83627ehf_device_names[data->sio_kind] */
70 static const char * const w83627ehf_device_names[] = {
71 "w83627ehf",
72 "w83627dhg",
73 "w83627dhg",
74 "w83627uhg",
75 "w83667hg",
76 "w83667hg",
77 "nct6775",
78 "nct6776",
79 };
80
81 static unsigned short force_id;
82 module_param(force_id, ushort, 0);
83 MODULE_PARM_DESC(force_id, "Override the detected device ID");
84
85 static unsigned short fan_debounce;
86 module_param(fan_debounce, ushort, 0);
87 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
88
89 #define DRVNAME "w83627ehf"
90
91 /*
92 * Super-I/O constants and functions
93 */
94
95 #define W83627EHF_LD_HWM 0x0b
96 #define W83667HG_LD_VID 0x0d
97
98 #define SIO_REG_LDSEL 0x07 /* Logical device select */
99 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
100 #define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
101 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
102 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
103 #define SIO_REG_VID_CTRL 0xF0 /* VID control */
104 #define SIO_REG_VID_DATA 0xF1 /* VID data */
105
106 #define SIO_W83627EHF_ID 0x8850
107 #define SIO_W83627EHG_ID 0x8860
108 #define SIO_W83627DHG_ID 0xa020
109 #define SIO_W83627DHG_P_ID 0xb070
110 #define SIO_W83627UHG_ID 0xa230
111 #define SIO_W83667HG_ID 0xa510
112 #define SIO_W83667HG_B_ID 0xb350
113 #define SIO_NCT6775_ID 0xb470
114 #define SIO_NCT6776_ID 0xc330
115 #define SIO_ID_MASK 0xFFF0
116
117 static inline void
118 superio_outb(int ioreg, int reg, int val)
119 {
120 outb(reg, ioreg);
121 outb(val, ioreg + 1);
122 }
123
124 static inline int
125 superio_inb(int ioreg, int reg)
126 {
127 outb(reg, ioreg);
128 return inb(ioreg + 1);
129 }
130
131 static inline void
132 superio_select(int ioreg, int ld)
133 {
134 outb(SIO_REG_LDSEL, ioreg);
135 outb(ld, ioreg + 1);
136 }
137
138 static inline void
139 superio_enter(int ioreg)
140 {
141 outb(0x87, ioreg);
142 outb(0x87, ioreg);
143 }
144
145 static inline void
146 superio_exit(int ioreg)
147 {
148 outb(0xaa, ioreg);
149 outb(0x02, ioreg);
150 outb(0x02, ioreg + 1);
151 }
152
153 /*
154 * ISA constants
155 */
156
157 #define IOREGION_ALIGNMENT (~7)
158 #define IOREGION_OFFSET 5
159 #define IOREGION_LENGTH 2
160 #define ADDR_REG_OFFSET 0
161 #define DATA_REG_OFFSET 1
162
163 #define W83627EHF_REG_BANK 0x4E
164 #define W83627EHF_REG_CONFIG 0x40
165
166 /*
167 * Not currently used:
168 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
169 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
170 * REG_MAN_ID is at port 0x4f
171 * REG_CHIP_ID is at port 0x58
172 */
173
174 static const u16 W83627EHF_REG_FAN[] = { 0x28, 0x29, 0x2a, 0x3f, 0x553 };
175 static const u16 W83627EHF_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d, 0x3e, 0x55c };
176
177 /* The W83627EHF registers for nr=7,8,9 are in bank 5 */
178 #define W83627EHF_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
179 (0x554 + (((nr) - 7) * 2)))
180 #define W83627EHF_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
181 (0x555 + (((nr) - 7) * 2)))
182 #define W83627EHF_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
183 (0x550 + (nr) - 7))
184
185 static const u16 W83627EHF_REG_TEMP[] = { 0x27, 0x150, 0x250, 0x7e };
186 static const u16 W83627EHF_REG_TEMP_HYST[] = { 0x3a, 0x153, 0x253, 0 };
187 static const u16 W83627EHF_REG_TEMP_OVER[] = { 0x39, 0x155, 0x255, 0 };
188 static const u16 W83627EHF_REG_TEMP_CONFIG[] = { 0, 0x152, 0x252, 0 };
189
190 /* Fan clock dividers are spread over the following five registers */
191 #define W83627EHF_REG_FANDIV1 0x47
192 #define W83627EHF_REG_FANDIV2 0x4B
193 #define W83627EHF_REG_VBAT 0x5D
194 #define W83627EHF_REG_DIODE 0x59
195 #define W83627EHF_REG_SMI_OVT 0x4C
196
197 /* NCT6775F has its own fan divider registers */
198 #define NCT6775_REG_FANDIV1 0x506
199 #define NCT6775_REG_FANDIV2 0x507
200 #define NCT6775_REG_FAN_DEBOUNCE 0xf0
201
202 #define W83627EHF_REG_ALARM1 0x459
203 #define W83627EHF_REG_ALARM2 0x45A
204 #define W83627EHF_REG_ALARM3 0x45B
205
206 #define W83627EHF_REG_CASEOPEN_DET 0x42 /* SMI STATUS #2 */
207 #define W83627EHF_REG_CASEOPEN_CLR 0x46 /* SMI MASK #3 */
208
209 /* SmartFan registers */
210 #define W83627EHF_REG_FAN_STEPUP_TIME 0x0f
211 #define W83627EHF_REG_FAN_STEPDOWN_TIME 0x0e
212
213 /* DC or PWM output fan configuration */
214 static const u8 W83627EHF_REG_PWM_ENABLE[] = {
215 0x04, /* SYS FAN0 output mode and PWM mode */
216 0x04, /* CPU FAN0 output mode and PWM mode */
217 0x12, /* AUX FAN mode */
218 0x62, /* CPU FAN1 mode */
219 };
220
221 static const u8 W83627EHF_PWM_MODE_SHIFT[] = { 0, 1, 0, 6 };
222 static const u8 W83627EHF_PWM_ENABLE_SHIFT[] = { 2, 4, 1, 4 };
223
224 /* FAN Duty Cycle, be used to control */
225 static const u16 W83627EHF_REG_PWM[] = { 0x01, 0x03, 0x11, 0x61 };
226 static const u16 W83627EHF_REG_TARGET[] = { 0x05, 0x06, 0x13, 0x63 };
227 static const u8 W83627EHF_REG_TOLERANCE[] = { 0x07, 0x07, 0x14, 0x62 };
228
229 /* Advanced Fan control, some values are common for all fans */
230 static const u16 W83627EHF_REG_FAN_START_OUTPUT[] = { 0x0a, 0x0b, 0x16, 0x65 };
231 static const u16 W83627EHF_REG_FAN_STOP_OUTPUT[] = { 0x08, 0x09, 0x15, 0x64 };
232 static const u16 W83627EHF_REG_FAN_STOP_TIME[] = { 0x0c, 0x0d, 0x17, 0x66 };
233
234 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON[]
235 = { 0xff, 0x67, 0xff, 0x69 };
236 static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON[]
237 = { 0xff, 0x68, 0xff, 0x6a };
238
239 static const u16 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B[] = { 0x67, 0x69, 0x6b };
240 static const u16 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B[]
241 = { 0x68, 0x6a, 0x6c };
242
243 static const u16 W83627EHF_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
244
245 static const u16 NCT6775_REG_TARGET[] = { 0x101, 0x201, 0x301 };
246 static const u16 NCT6775_REG_FAN_MODE[] = { 0x102, 0x202, 0x302 };
247 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = { 0x105, 0x205, 0x305 };
248 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = { 0x106, 0x206, 0x306 };
249 static const u16 NCT6775_REG_FAN_STOP_TIME[] = { 0x107, 0x207, 0x307 };
250 static const u16 NCT6775_REG_PWM[] = { 0x109, 0x209, 0x309 };
251 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
252 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
253 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
254 static const u16 NCT6776_REG_FAN_MIN[] = { 0x63a, 0x63c, 0x63e, 0x640, 0x642};
255
256 static const u16 NCT6775_REG_TEMP[]
257 = { 0x27, 0x150, 0x250, 0x73, 0x75, 0x77, 0x62b, 0x62c, 0x62d };
258 static const u16 NCT6775_REG_TEMP_CONFIG[]
259 = { 0, 0x152, 0x252, 0, 0, 0, 0x628, 0x629, 0x62A };
260 static const u16 NCT6775_REG_TEMP_HYST[]
261 = { 0x3a, 0x153, 0x253, 0, 0, 0, 0x673, 0x678, 0x67D };
262 static const u16 NCT6775_REG_TEMP_OVER[]
263 = { 0x39, 0x155, 0x255, 0, 0, 0, 0x672, 0x677, 0x67C };
264 static const u16 NCT6775_REG_TEMP_SOURCE[]
265 = { 0x621, 0x622, 0x623, 0x100, 0x200, 0x300, 0x624, 0x625, 0x626 };
266
267 static const char *const w83667hg_b_temp_label[] = {
268 "SYSTIN",
269 "CPUTIN",
270 "AUXTIN",
271 "AMDTSI",
272 "PECI Agent 1",
273 "PECI Agent 2",
274 "PECI Agent 3",
275 "PECI Agent 4"
276 };
277
278 static const char *const nct6775_temp_label[] = {
279 "",
280 "SYSTIN",
281 "CPUTIN",
282 "AUXTIN",
283 "AMD SB-TSI",
284 "PECI Agent 0",
285 "PECI Agent 1",
286 "PECI Agent 2",
287 "PECI Agent 3",
288 "PECI Agent 4",
289 "PECI Agent 5",
290 "PECI Agent 6",
291 "PECI Agent 7",
292 "PCH_CHIP_CPU_MAX_TEMP",
293 "PCH_CHIP_TEMP",
294 "PCH_CPU_TEMP",
295 "PCH_MCH_TEMP",
296 "PCH_DIM0_TEMP",
297 "PCH_DIM1_TEMP",
298 "PCH_DIM2_TEMP",
299 "PCH_DIM3_TEMP"
300 };
301
302 static const char *const nct6776_temp_label[] = {
303 "",
304 "SYSTIN",
305 "CPUTIN",
306 "AUXTIN",
307 "SMBUSMASTER 0",
308 "SMBUSMASTER 1",
309 "SMBUSMASTER 2",
310 "SMBUSMASTER 3",
311 "SMBUSMASTER 4",
312 "SMBUSMASTER 5",
313 "SMBUSMASTER 6",
314 "SMBUSMASTER 7",
315 "PECI Agent 0",
316 "PECI Agent 1",
317 "PCH_CHIP_CPU_MAX_TEMP",
318 "PCH_CHIP_TEMP",
319 "PCH_CPU_TEMP",
320 "PCH_MCH_TEMP",
321 "PCH_DIM0_TEMP",
322 "PCH_DIM1_TEMP",
323 "PCH_DIM2_TEMP",
324 "PCH_DIM3_TEMP",
325 "BYTE_TEMP"
326 };
327
328 #define NUM_REG_TEMP ARRAY_SIZE(NCT6775_REG_TEMP)
329
330 static int is_word_sized(u16 reg)
331 {
332 return ((((reg & 0xff00) == 0x100
333 || (reg & 0xff00) == 0x200)
334 && ((reg & 0x00ff) == 0x50
335 || (reg & 0x00ff) == 0x53
336 || (reg & 0x00ff) == 0x55))
337 || (reg & 0xfff0) == 0x630
338 || reg == 0x640 || reg == 0x642
339 || ((reg & 0xfff0) == 0x650
340 && (reg & 0x000f) >= 0x06)
341 || reg == 0x73 || reg == 0x75 || reg == 0x77
342 );
343 }
344
345 /*
346 * Conversions
347 */
348
349 /* 1 is PWM mode, output in ms */
350 static inline unsigned int step_time_from_reg(u8 reg, u8 mode)
351 {
352 return mode ? 100 * reg : 400 * reg;
353 }
354
355 static inline u8 step_time_to_reg(unsigned int msec, u8 mode)
356 {
357 return SENSORS_LIMIT((mode ? (msec + 50) / 100 :
358 (msec + 200) / 400), 1, 255);
359 }
360
361 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
362 {
363 if (reg == 0 || reg == 255)
364 return 0;
365 return 1350000U / (reg << divreg);
366 }
367
368 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
369 {
370 if ((reg & 0xff1f) == 0xff1f)
371 return 0;
372
373 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
374
375 if (reg == 0)
376 return 0;
377
378 return 1350000U / reg;
379 }
380
381 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
382 {
383 if (reg == 0 || reg == 0xffff)
384 return 0;
385
386 /*
387 * Even though the registers are 16 bit wide, the fan divisor
388 * still applies.
389 */
390 return 1350000U / (reg << divreg);
391 }
392
393 static inline unsigned int
394 div_from_reg(u8 reg)
395 {
396 return 1 << reg;
397 }
398
399 /*
400 * Some of the voltage inputs have internal scaling, the tables below
401 * contain 8 (the ADC LSB in mV) * scaling factor * 100
402 */
403 static const u16 scale_in_common[10] = {
404 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800
405 };
406 static const u16 scale_in_w83627uhg[9] = {
407 800, 800, 3328, 3424, 800, 800, 0, 3328, 3400
408 };
409
410 static inline long in_from_reg(u8 reg, u8 nr, const u16 *scale_in)
411 {
412 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
413 }
414
415 static inline u8 in_to_reg(u32 val, u8 nr, const u16 *scale_in)
416 {
417 return SENSORS_LIMIT(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0,
418 255);
419 }
420
421 /*
422 * Data structures and manipulation thereof
423 */
424
425 struct w83627ehf_data {
426 int addr; /* IO base of hw monitor block */
427 const char *name;
428
429 struct device *hwmon_dev;
430 struct mutex lock;
431
432 u16 reg_temp[NUM_REG_TEMP];
433 u16 reg_temp_over[NUM_REG_TEMP];
434 u16 reg_temp_hyst[NUM_REG_TEMP];
435 u16 reg_temp_config[NUM_REG_TEMP];
436 u8 temp_src[NUM_REG_TEMP];
437 const char * const *temp_label;
438
439 const u16 *REG_PWM;
440 const u16 *REG_TARGET;
441 const u16 *REG_FAN;
442 const u16 *REG_FAN_MIN;
443 const u16 *REG_FAN_START_OUTPUT;
444 const u16 *REG_FAN_STOP_OUTPUT;
445 const u16 *REG_FAN_STOP_TIME;
446 const u16 *REG_FAN_MAX_OUTPUT;
447 const u16 *REG_FAN_STEP_OUTPUT;
448 const u16 *scale_in;
449
450 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
451 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
452
453 struct mutex update_lock;
454 char valid; /* !=0 if following fields are valid */
455 unsigned long last_updated; /* In jiffies */
456
457 /* Register values */
458 u8 bank; /* current register bank */
459 u8 in_num; /* number of in inputs we have */
460 u8 in[10]; /* Register value */
461 u8 in_max[10]; /* Register value */
462 u8 in_min[10]; /* Register value */
463 unsigned int rpm[5];
464 u16 fan_min[5];
465 u8 fan_div[5];
466 u8 has_fan; /* some fan inputs can be disabled */
467 u8 has_fan_min; /* some fans don't have min register */
468 bool has_fan_div;
469 u8 temp_type[3];
470 s8 temp_offset[3];
471 s16 temp[9];
472 s16 temp_max[9];
473 s16 temp_max_hyst[9];
474 u32 alarms;
475 u8 caseopen;
476
477 u8 pwm_mode[4]; /* 0->DC variable voltage, 1->PWM variable duty cycle */
478 u8 pwm_enable[4]; /* 1->manual
479 * 2->thermal cruise mode (also called SmartFan I)
480 * 3->fan speed cruise mode
481 * 4->variable thermal cruise (also called
482 * SmartFan III)
483 * 5->enhanced variable thermal cruise (also called
484 * SmartFan IV)
485 */
486 u8 pwm_enable_orig[4]; /* original value of pwm_enable */
487 u8 pwm_num; /* number of pwm */
488 u8 pwm[4];
489 u8 target_temp[4];
490 u8 tolerance[4];
491
492 u8 fan_start_output[4]; /* minimum fan speed when spinning up */
493 u8 fan_stop_output[4]; /* minimum fan speed when spinning down */
494 u8 fan_stop_time[4]; /* time at minimum before disabling fan */
495 u8 fan_max_output[4]; /* maximum fan speed */
496 u8 fan_step_output[4]; /* rate of change output value */
497
498 u8 vid;
499 u8 vrm;
500
501 u16 have_temp;
502 u16 have_temp_offset;
503 u8 in6_skip:1;
504 u8 temp3_val_only:1;
505 };
506
507 struct w83627ehf_sio_data {
508 int sioreg;
509 enum kinds kind;
510 };
511
512 /*
513 * On older chips, only registers 0x50-0x5f are banked.
514 * On more recent chips, all registers are banked.
515 * Assume that is the case and set the bank number for each access.
516 * Cache the bank number so it only needs to be set if it changes.
517 */
518 static inline void w83627ehf_set_bank(struct w83627ehf_data *data, u16 reg)
519 {
520 u8 bank = reg >> 8;
521 if (data->bank != bank) {
522 outb_p(W83627EHF_REG_BANK, data->addr + ADDR_REG_OFFSET);
523 outb_p(bank, data->addr + DATA_REG_OFFSET);
524 data->bank = bank;
525 }
526 }
527
528 static u16 w83627ehf_read_value(struct w83627ehf_data *data, u16 reg)
529 {
530 int res, word_sized = is_word_sized(reg);
531
532 mutex_lock(&data->lock);
533
534 w83627ehf_set_bank(data, reg);
535 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
536 res = inb_p(data->addr + DATA_REG_OFFSET);
537 if (word_sized) {
538 outb_p((reg & 0xff) + 1,
539 data->addr + ADDR_REG_OFFSET);
540 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
541 }
542
543 mutex_unlock(&data->lock);
544 return res;
545 }
546
547 static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
548 u16 value)
549 {
550 int word_sized = is_word_sized(reg);
551
552 mutex_lock(&data->lock);
553
554 w83627ehf_set_bank(data, reg);
555 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
556 if (word_sized) {
557 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
558 outb_p((reg & 0xff) + 1,
559 data->addr + ADDR_REG_OFFSET);
560 }
561 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
562
563 mutex_unlock(&data->lock);
564 return 0;
565 }
566
567 /* We left-align 8-bit temperature values to make the code simpler */
568 static u16 w83627ehf_read_temp(struct w83627ehf_data *data, u16 reg)
569 {
570 u16 res;
571
572 res = w83627ehf_read_value(data, reg);
573 if (!is_word_sized(reg))
574 res <<= 8;
575
576 return res;
577 }
578
579 static int w83627ehf_write_temp(struct w83627ehf_data *data, u16 reg,
580 u16 value)
581 {
582 if (!is_word_sized(reg))
583 value >>= 8;
584 return w83627ehf_write_value(data, reg, value);
585 }
586
587 /* This function assumes that the caller holds data->update_lock */
588 static void nct6775_write_fan_div(struct w83627ehf_data *data, int nr)
589 {
590 u8 reg;
591
592 switch (nr) {
593 case 0:
594 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
595 | (data->fan_div[0] & 0x7);
596 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
597 break;
598 case 1:
599 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
600 | ((data->fan_div[1] << 4) & 0x70);
601 w83627ehf_write_value(data, NCT6775_REG_FANDIV1, reg);
602 case 2:
603 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
604 | (data->fan_div[2] & 0x7);
605 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
606 break;
607 case 3:
608 reg = (w83627ehf_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
609 | ((data->fan_div[3] << 4) & 0x70);
610 w83627ehf_write_value(data, NCT6775_REG_FANDIV2, reg);
611 break;
612 }
613 }
614
615 /* This function assumes that the caller holds data->update_lock */
616 static void w83627ehf_write_fan_div(struct w83627ehf_data *data, int nr)
617 {
618 u8 reg;
619
620 switch (nr) {
621 case 0:
622 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0xcf)
623 | ((data->fan_div[0] & 0x03) << 4);
624 /* fan5 input control bit is write only, compute the value */
625 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
626 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
627 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xdf)
628 | ((data->fan_div[0] & 0x04) << 3);
629 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
630 break;
631 case 1:
632 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV1) & 0x3f)
633 | ((data->fan_div[1] & 0x03) << 6);
634 /* fan5 input control bit is write only, compute the value */
635 reg |= (data->has_fan & (1 << 4)) ? 1 : 0;
636 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
637 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0xbf)
638 | ((data->fan_div[1] & 0x04) << 4);
639 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
640 break;
641 case 2:
642 reg = (w83627ehf_read_value(data, W83627EHF_REG_FANDIV2) & 0x3f)
643 | ((data->fan_div[2] & 0x03) << 6);
644 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
645 reg = (w83627ehf_read_value(data, W83627EHF_REG_VBAT) & 0x7f)
646 | ((data->fan_div[2] & 0x04) << 5);
647 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
648 break;
649 case 3:
650 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0xfc)
651 | (data->fan_div[3] & 0x03);
652 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
653 reg = (w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT) & 0x7f)
654 | ((data->fan_div[3] & 0x04) << 5);
655 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
656 break;
657 case 4:
658 reg = (w83627ehf_read_value(data, W83627EHF_REG_DIODE) & 0x73)
659 | ((data->fan_div[4] & 0x03) << 2)
660 | ((data->fan_div[4] & 0x04) << 5);
661 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
662 break;
663 }
664 }
665
666 static void w83627ehf_write_fan_div_common(struct device *dev,
667 struct w83627ehf_data *data, int nr)
668 {
669 struct w83627ehf_sio_data *sio_data = dev->platform_data;
670
671 if (sio_data->kind == nct6776)
672 ; /* no dividers, do nothing */
673 else if (sio_data->kind == nct6775)
674 nct6775_write_fan_div(data, nr);
675 else
676 w83627ehf_write_fan_div(data, nr);
677 }
678
679 static void nct6775_update_fan_div(struct w83627ehf_data *data)
680 {
681 u8 i;
682
683 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV1);
684 data->fan_div[0] = i & 0x7;
685 data->fan_div[1] = (i & 0x70) >> 4;
686 i = w83627ehf_read_value(data, NCT6775_REG_FANDIV2);
687 data->fan_div[2] = i & 0x7;
688 if (data->has_fan & (1<<3))
689 data->fan_div[3] = (i & 0x70) >> 4;
690 }
691
692 static void w83627ehf_update_fan_div(struct w83627ehf_data *data)
693 {
694 int i;
695
696 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
697 data->fan_div[0] = (i >> 4) & 0x03;
698 data->fan_div[1] = (i >> 6) & 0x03;
699 i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV2);
700 data->fan_div[2] = (i >> 6) & 0x03;
701 i = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
702 data->fan_div[0] |= (i >> 3) & 0x04;
703 data->fan_div[1] |= (i >> 4) & 0x04;
704 data->fan_div[2] |= (i >> 5) & 0x04;
705 if (data->has_fan & ((1 << 3) | (1 << 4))) {
706 i = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
707 data->fan_div[3] = i & 0x03;
708 data->fan_div[4] = ((i >> 2) & 0x03)
709 | ((i >> 5) & 0x04);
710 }
711 if (data->has_fan & (1 << 3)) {
712 i = w83627ehf_read_value(data, W83627EHF_REG_SMI_OVT);
713 data->fan_div[3] |= (i >> 5) & 0x04;
714 }
715 }
716
717 static void w83627ehf_update_fan_div_common(struct device *dev,
718 struct w83627ehf_data *data)
719 {
720 struct w83627ehf_sio_data *sio_data = dev->platform_data;
721
722 if (sio_data->kind == nct6776)
723 ; /* no dividers, do nothing */
724 else if (sio_data->kind == nct6775)
725 nct6775_update_fan_div(data);
726 else
727 w83627ehf_update_fan_div(data);
728 }
729
730 static void nct6775_update_pwm(struct w83627ehf_data *data)
731 {
732 int i;
733 int pwmcfg, fanmodecfg;
734
735 for (i = 0; i < data->pwm_num; i++) {
736 pwmcfg = w83627ehf_read_value(data,
737 W83627EHF_REG_PWM_ENABLE[i]);
738 fanmodecfg = w83627ehf_read_value(data,
739 NCT6775_REG_FAN_MODE[i]);
740 data->pwm_mode[i] =
741 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
742 data->pwm_enable[i] = ((fanmodecfg >> 4) & 7) + 1;
743 data->tolerance[i] = fanmodecfg & 0x0f;
744 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
745 }
746 }
747
748 static void w83627ehf_update_pwm(struct w83627ehf_data *data)
749 {
750 int i;
751 int pwmcfg = 0, tolerance = 0; /* shut up the compiler */
752
753 for (i = 0; i < data->pwm_num; i++) {
754 if (!(data->has_fan & (1 << i)))
755 continue;
756
757 /* pwmcfg, tolerance mapped for i=0, i=1 to same reg */
758 if (i != 1) {
759 pwmcfg = w83627ehf_read_value(data,
760 W83627EHF_REG_PWM_ENABLE[i]);
761 tolerance = w83627ehf_read_value(data,
762 W83627EHF_REG_TOLERANCE[i]);
763 }
764 data->pwm_mode[i] =
765 ((pwmcfg >> W83627EHF_PWM_MODE_SHIFT[i]) & 1) ? 0 : 1;
766 data->pwm_enable[i] = ((pwmcfg >> W83627EHF_PWM_ENABLE_SHIFT[i])
767 & 3) + 1;
768 data->pwm[i] = w83627ehf_read_value(data, data->REG_PWM[i]);
769
770 data->tolerance[i] = (tolerance >> (i == 1 ? 4 : 0)) & 0x0f;
771 }
772 }
773
774 static void w83627ehf_update_pwm_common(struct device *dev,
775 struct w83627ehf_data *data)
776 {
777 struct w83627ehf_sio_data *sio_data = dev->platform_data;
778
779 if (sio_data->kind == nct6775 || sio_data->kind == nct6776)
780 nct6775_update_pwm(data);
781 else
782 w83627ehf_update_pwm(data);
783 }
784
785 static struct w83627ehf_data *w83627ehf_update_device(struct device *dev)
786 {
787 struct w83627ehf_data *data = dev_get_drvdata(dev);
788 struct w83627ehf_sio_data *sio_data = dev->platform_data;
789
790 int i;
791
792 mutex_lock(&data->update_lock);
793
794 if (time_after(jiffies, data->last_updated + HZ + HZ/2)
795 || !data->valid) {
796 /* Fan clock dividers */
797 w83627ehf_update_fan_div_common(dev, data);
798
799 /* Measured voltages and limits */
800 for (i = 0; i < data->in_num; i++) {
801 if ((i == 6) && data->in6_skip)
802 continue;
803
804 data->in[i] = w83627ehf_read_value(data,
805 W83627EHF_REG_IN(i));
806 data->in_min[i] = w83627ehf_read_value(data,
807 W83627EHF_REG_IN_MIN(i));
808 data->in_max[i] = w83627ehf_read_value(data,
809 W83627EHF_REG_IN_MAX(i));
810 }
811
812 /* Measured fan speeds and limits */
813 for (i = 0; i < 5; i++) {
814 u16 reg;
815
816 if (!(data->has_fan & (1 << i)))
817 continue;
818
819 reg = w83627ehf_read_value(data, data->REG_FAN[i]);
820 data->rpm[i] = data->fan_from_reg(reg,
821 data->fan_div[i]);
822
823 if (data->has_fan_min & (1 << i))
824 data->fan_min[i] = w83627ehf_read_value(data,
825 data->REG_FAN_MIN[i]);
826
827 /*
828 * If we failed to measure the fan speed and clock
829 * divider can be increased, let's try that for next
830 * time
831 */
832 if (data->has_fan_div
833 && (reg >= 0xff || (sio_data->kind == nct6775
834 && reg == 0x00))
835 && data->fan_div[i] < 0x07) {
836 dev_dbg(dev, "Increasing fan%d "
837 "clock divider from %u to %u\n",
838 i + 1, div_from_reg(data->fan_div[i]),
839 div_from_reg(data->fan_div[i] + 1));
840 data->fan_div[i]++;
841 w83627ehf_write_fan_div_common(dev, data, i);
842 /* Preserve min limit if possible */
843 if ((data->has_fan_min & (1 << i))
844 && data->fan_min[i] >= 2
845 && data->fan_min[i] != 255)
846 w83627ehf_write_value(data,
847 data->REG_FAN_MIN[i],
848 (data->fan_min[i] /= 2));
849 }
850 }
851
852 w83627ehf_update_pwm_common(dev, data);
853
854 for (i = 0; i < data->pwm_num; i++) {
855 if (!(data->has_fan & (1 << i)))
856 continue;
857
858 data->fan_start_output[i] =
859 w83627ehf_read_value(data,
860 data->REG_FAN_START_OUTPUT[i]);
861 data->fan_stop_output[i] =
862 w83627ehf_read_value(data,
863 data->REG_FAN_STOP_OUTPUT[i]);
864 data->fan_stop_time[i] =
865 w83627ehf_read_value(data,
866 data->REG_FAN_STOP_TIME[i]);
867
868 if (data->REG_FAN_MAX_OUTPUT &&
869 data->REG_FAN_MAX_OUTPUT[i] != 0xff)
870 data->fan_max_output[i] =
871 w83627ehf_read_value(data,
872 data->REG_FAN_MAX_OUTPUT[i]);
873
874 if (data->REG_FAN_STEP_OUTPUT &&
875 data->REG_FAN_STEP_OUTPUT[i] != 0xff)
876 data->fan_step_output[i] =
877 w83627ehf_read_value(data,
878 data->REG_FAN_STEP_OUTPUT[i]);
879
880 data->target_temp[i] =
881 w83627ehf_read_value(data,
882 data->REG_TARGET[i]) &
883 (data->pwm_mode[i] == 1 ? 0x7f : 0xff);
884 }
885
886 /* Measured temperatures and limits */
887 for (i = 0; i < NUM_REG_TEMP; i++) {
888 if (!(data->have_temp & (1 << i)))
889 continue;
890 data->temp[i] = w83627ehf_read_temp(data,
891 data->reg_temp[i]);
892 if (data->reg_temp_over[i])
893 data->temp_max[i]
894 = w83627ehf_read_temp(data,
895 data->reg_temp_over[i]);
896 if (data->reg_temp_hyst[i])
897 data->temp_max_hyst[i]
898 = w83627ehf_read_temp(data,
899 data->reg_temp_hyst[i]);
900 if (data->have_temp_offset & (1 << i))
901 data->temp_offset[i]
902 = w83627ehf_read_value(data,
903 W83627EHF_REG_TEMP_OFFSET[i]);
904 }
905
906 data->alarms = w83627ehf_read_value(data,
907 W83627EHF_REG_ALARM1) |
908 (w83627ehf_read_value(data,
909 W83627EHF_REG_ALARM2) << 8) |
910 (w83627ehf_read_value(data,
911 W83627EHF_REG_ALARM3) << 16);
912
913 data->caseopen = w83627ehf_read_value(data,
914 W83627EHF_REG_CASEOPEN_DET);
915
916 data->last_updated = jiffies;
917 data->valid = 1;
918 }
919
920 mutex_unlock(&data->update_lock);
921 return data;
922 }
923
924 /*
925 * Sysfs callback functions
926 */
927 #define show_in_reg(reg) \
928 static ssize_t \
929 show_##reg(struct device *dev, struct device_attribute *attr, \
930 char *buf) \
931 { \
932 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
933 struct sensor_device_attribute *sensor_attr = \
934 to_sensor_dev_attr(attr); \
935 int nr = sensor_attr->index; \
936 return sprintf(buf, "%ld\n", in_from_reg(data->reg[nr], nr, \
937 data->scale_in)); \
938 }
939 show_in_reg(in)
940 show_in_reg(in_min)
941 show_in_reg(in_max)
942
943 #define store_in_reg(REG, reg) \
944 static ssize_t \
945 store_in_##reg(struct device *dev, struct device_attribute *attr, \
946 const char *buf, size_t count) \
947 { \
948 struct w83627ehf_data *data = dev_get_drvdata(dev); \
949 struct sensor_device_attribute *sensor_attr = \
950 to_sensor_dev_attr(attr); \
951 int nr = sensor_attr->index; \
952 unsigned long val; \
953 int err; \
954 err = kstrtoul(buf, 10, &val); \
955 if (err < 0) \
956 return err; \
957 mutex_lock(&data->update_lock); \
958 data->in_##reg[nr] = in_to_reg(val, nr, data->scale_in); \
959 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(nr), \
960 data->in_##reg[nr]); \
961 mutex_unlock(&data->update_lock); \
962 return count; \
963 }
964
965 store_in_reg(MIN, min)
966 store_in_reg(MAX, max)
967
968 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
969 char *buf)
970 {
971 struct w83627ehf_data *data = w83627ehf_update_device(dev);
972 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
973 int nr = sensor_attr->index;
974 return sprintf(buf, "%u\n", (data->alarms >> nr) & 0x01);
975 }
976
977 static struct sensor_device_attribute sda_in_input[] = {
978 SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
979 SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
980 SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
981 SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
982 SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
983 SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
984 SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
985 SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
986 SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
987 SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
988 };
989
990 static struct sensor_device_attribute sda_in_alarm[] = {
991 SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
992 SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
993 SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
994 SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
995 SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
996 SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 21),
997 SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 20),
998 SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 16),
999 SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 17),
1000 SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 19),
1001 };
1002
1003 static struct sensor_device_attribute sda_in_min[] = {
1004 SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
1005 SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
1006 SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
1007 SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
1008 SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
1009 SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
1010 SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
1011 SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
1012 SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
1013 SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
1014 };
1015
1016 static struct sensor_device_attribute sda_in_max[] = {
1017 SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
1018 SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
1019 SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
1020 SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
1021 SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
1022 SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
1023 SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
1024 SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
1025 SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
1026 SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
1027 };
1028
1029 static ssize_t
1030 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1031 {
1032 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1033 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1034 int nr = sensor_attr->index;
1035 return sprintf(buf, "%d\n", data->rpm[nr]);
1036 }
1037
1038 static ssize_t
1039 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1040 {
1041 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1042 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1043 int nr = sensor_attr->index;
1044 return sprintf(buf, "%d\n",
1045 data->fan_from_reg_min(data->fan_min[nr],
1046 data->fan_div[nr]));
1047 }
1048
1049 static ssize_t
1050 show_fan_div(struct device *dev, struct device_attribute *attr,
1051 char *buf)
1052 {
1053 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1054 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1055 int nr = sensor_attr->index;
1056 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
1057 }
1058
1059 static ssize_t
1060 store_fan_min(struct device *dev, struct device_attribute *attr,
1061 const char *buf, size_t count)
1062 {
1063 struct w83627ehf_data *data = dev_get_drvdata(dev);
1064 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1065 int nr = sensor_attr->index;
1066 unsigned long val;
1067 int err;
1068 unsigned int reg;
1069 u8 new_div;
1070
1071 err = kstrtoul(buf, 10, &val);
1072 if (err < 0)
1073 return err;
1074
1075 mutex_lock(&data->update_lock);
1076 if (!data->has_fan_div) {
1077 /*
1078 * Only NCT6776F for now, so we know that this is a 13 bit
1079 * register
1080 */
1081 if (!val) {
1082 val = 0xff1f;
1083 } else {
1084 if (val > 1350000U)
1085 val = 135000U;
1086 val = 1350000U / val;
1087 val = (val & 0x1f) | ((val << 3) & 0xff00);
1088 }
1089 data->fan_min[nr] = val;
1090 goto done; /* Leave fan divider alone */
1091 }
1092 if (!val) {
1093 /* No min limit, alarm disabled */
1094 data->fan_min[nr] = 255;
1095 new_div = data->fan_div[nr]; /* No change */
1096 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
1097 } else if ((reg = 1350000U / val) >= 128 * 255) {
1098 /*
1099 * Speed below this value cannot possibly be represented,
1100 * even with the highest divider (128)
1101 */
1102 data->fan_min[nr] = 254;
1103 new_div = 7; /* 128 == (1 << 7) */
1104 dev_warn(dev, "fan%u low limit %lu below minimum %u, set to "
1105 "minimum\n", nr + 1, val,
1106 data->fan_from_reg_min(254, 7));
1107 } else if (!reg) {
1108 /*
1109 * Speed above this value cannot possibly be represented,
1110 * even with the lowest divider (1)
1111 */
1112 data->fan_min[nr] = 1;
1113 new_div = 0; /* 1 == (1 << 0) */
1114 dev_warn(dev, "fan%u low limit %lu above maximum %u, set to "
1115 "maximum\n", nr + 1, val,
1116 data->fan_from_reg_min(1, 0));
1117 } else {
1118 /*
1119 * Automatically pick the best divider, i.e. the one such
1120 * that the min limit will correspond to a register value
1121 * in the 96..192 range
1122 */
1123 new_div = 0;
1124 while (reg > 192 && new_div < 7) {
1125 reg >>= 1;
1126 new_div++;
1127 }
1128 data->fan_min[nr] = reg;
1129 }
1130
1131 /*
1132 * Write both the fan clock divider (if it changed) and the new
1133 * fan min (unconditionally)
1134 */
1135 if (new_div != data->fan_div[nr]) {
1136 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
1137 nr + 1, div_from_reg(data->fan_div[nr]),
1138 div_from_reg(new_div));
1139 data->fan_div[nr] = new_div;
1140 w83627ehf_write_fan_div_common(dev, data, nr);
1141 /* Give the chip time to sample a new speed value */
1142 data->last_updated = jiffies;
1143 }
1144 done:
1145 w83627ehf_write_value(data, data->REG_FAN_MIN[nr],
1146 data->fan_min[nr]);
1147 mutex_unlock(&data->update_lock);
1148
1149 return count;
1150 }
1151
1152 static struct sensor_device_attribute sda_fan_input[] = {
1153 SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
1154 SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
1155 SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
1156 SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
1157 SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
1158 };
1159
1160 static struct sensor_device_attribute sda_fan_alarm[] = {
1161 SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
1162 SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
1163 SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
1164 SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 10),
1165 SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 23),
1166 };
1167
1168 static struct sensor_device_attribute sda_fan_min[] = {
1169 SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO, show_fan_min,
1170 store_fan_min, 0),
1171 SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO, show_fan_min,
1172 store_fan_min, 1),
1173 SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO, show_fan_min,
1174 store_fan_min, 2),
1175 SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO, show_fan_min,
1176 store_fan_min, 3),
1177 SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO, show_fan_min,
1178 store_fan_min, 4),
1179 };
1180
1181 static struct sensor_device_attribute sda_fan_div[] = {
1182 SENSOR_ATTR(fan1_div, S_IRUGO, show_fan_div, NULL, 0),
1183 SENSOR_ATTR(fan2_div, S_IRUGO, show_fan_div, NULL, 1),
1184 SENSOR_ATTR(fan3_div, S_IRUGO, show_fan_div, NULL, 2),
1185 SENSOR_ATTR(fan4_div, S_IRUGO, show_fan_div, NULL, 3),
1186 SENSOR_ATTR(fan5_div, S_IRUGO, show_fan_div, NULL, 4),
1187 };
1188
1189 static ssize_t
1190 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
1191 {
1192 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1193 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1194 int nr = sensor_attr->index;
1195 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
1196 }
1197
1198 #define show_temp_reg(addr, reg) \
1199 static ssize_t \
1200 show_##reg(struct device *dev, struct device_attribute *attr, \
1201 char *buf) \
1202 { \
1203 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1204 struct sensor_device_attribute *sensor_attr = \
1205 to_sensor_dev_attr(attr); \
1206 int nr = sensor_attr->index; \
1207 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->reg[nr])); \
1208 }
1209 show_temp_reg(reg_temp, temp);
1210 show_temp_reg(reg_temp_over, temp_max);
1211 show_temp_reg(reg_temp_hyst, temp_max_hyst);
1212
1213 #define store_temp_reg(addr, reg) \
1214 static ssize_t \
1215 store_##reg(struct device *dev, struct device_attribute *attr, \
1216 const char *buf, size_t count) \
1217 { \
1218 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1219 struct sensor_device_attribute *sensor_attr = \
1220 to_sensor_dev_attr(attr); \
1221 int nr = sensor_attr->index; \
1222 int err; \
1223 long val; \
1224 err = kstrtol(buf, 10, &val); \
1225 if (err < 0) \
1226 return err; \
1227 mutex_lock(&data->update_lock); \
1228 data->reg[nr] = LM75_TEMP_TO_REG(val); \
1229 w83627ehf_write_temp(data, data->addr[nr], data->reg[nr]); \
1230 mutex_unlock(&data->update_lock); \
1231 return count; \
1232 }
1233 store_temp_reg(reg_temp_over, temp_max);
1234 store_temp_reg(reg_temp_hyst, temp_max_hyst);
1235
1236 static ssize_t
1237 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
1238 {
1239 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1240 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1241
1242 return sprintf(buf, "%d\n",
1243 data->temp_offset[sensor_attr->index] * 1000);
1244 }
1245
1246 static ssize_t
1247 store_temp_offset(struct device *dev, struct device_attribute *attr,
1248 const char *buf, size_t count)
1249 {
1250 struct w83627ehf_data *data = dev_get_drvdata(dev);
1251 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1252 int nr = sensor_attr->index;
1253 long val;
1254 int err;
1255
1256 err = kstrtol(buf, 10, &val);
1257 if (err < 0)
1258 return err;
1259
1260 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
1261
1262 mutex_lock(&data->update_lock);
1263 data->temp_offset[nr] = val;
1264 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[nr], val);
1265 mutex_unlock(&data->update_lock);
1266 return count;
1267 }
1268
1269 static ssize_t
1270 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
1271 {
1272 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1273 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1274 int nr = sensor_attr->index;
1275 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
1276 }
1277
1278 static struct sensor_device_attribute sda_temp_input[] = {
1279 SENSOR_ATTR(temp1_input, S_IRUGO, show_temp, NULL, 0),
1280 SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 1),
1281 SENSOR_ATTR(temp3_input, S_IRUGO, show_temp, NULL, 2),
1282 SENSOR_ATTR(temp4_input, S_IRUGO, show_temp, NULL, 3),
1283 SENSOR_ATTR(temp5_input, S_IRUGO, show_temp, NULL, 4),
1284 SENSOR_ATTR(temp6_input, S_IRUGO, show_temp, NULL, 5),
1285 SENSOR_ATTR(temp7_input, S_IRUGO, show_temp, NULL, 6),
1286 SENSOR_ATTR(temp8_input, S_IRUGO, show_temp, NULL, 7),
1287 SENSOR_ATTR(temp9_input, S_IRUGO, show_temp, NULL, 8),
1288 };
1289
1290 static struct sensor_device_attribute sda_temp_label[] = {
1291 SENSOR_ATTR(temp1_label, S_IRUGO, show_temp_label, NULL, 0),
1292 SENSOR_ATTR(temp2_label, S_IRUGO, show_temp_label, NULL, 1),
1293 SENSOR_ATTR(temp3_label, S_IRUGO, show_temp_label, NULL, 2),
1294 SENSOR_ATTR(temp4_label, S_IRUGO, show_temp_label, NULL, 3),
1295 SENSOR_ATTR(temp5_label, S_IRUGO, show_temp_label, NULL, 4),
1296 SENSOR_ATTR(temp6_label, S_IRUGO, show_temp_label, NULL, 5),
1297 SENSOR_ATTR(temp7_label, S_IRUGO, show_temp_label, NULL, 6),
1298 SENSOR_ATTR(temp8_label, S_IRUGO, show_temp_label, NULL, 7),
1299 SENSOR_ATTR(temp9_label, S_IRUGO, show_temp_label, NULL, 8),
1300 };
1301
1302 static struct sensor_device_attribute sda_temp_max[] = {
1303 SENSOR_ATTR(temp1_max, S_IRUGO | S_IWUSR, show_temp_max,
1304 store_temp_max, 0),
1305 SENSOR_ATTR(temp2_max, S_IRUGO | S_IWUSR, show_temp_max,
1306 store_temp_max, 1),
1307 SENSOR_ATTR(temp3_max, S_IRUGO | S_IWUSR, show_temp_max,
1308 store_temp_max, 2),
1309 SENSOR_ATTR(temp4_max, S_IRUGO | S_IWUSR, show_temp_max,
1310 store_temp_max, 3),
1311 SENSOR_ATTR(temp5_max, S_IRUGO | S_IWUSR, show_temp_max,
1312 store_temp_max, 4),
1313 SENSOR_ATTR(temp6_max, S_IRUGO | S_IWUSR, show_temp_max,
1314 store_temp_max, 5),
1315 SENSOR_ATTR(temp7_max, S_IRUGO | S_IWUSR, show_temp_max,
1316 store_temp_max, 6),
1317 SENSOR_ATTR(temp8_max, S_IRUGO | S_IWUSR, show_temp_max,
1318 store_temp_max, 7),
1319 SENSOR_ATTR(temp9_max, S_IRUGO | S_IWUSR, show_temp_max,
1320 store_temp_max, 8),
1321 };
1322
1323 static struct sensor_device_attribute sda_temp_max_hyst[] = {
1324 SENSOR_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1325 store_temp_max_hyst, 0),
1326 SENSOR_ATTR(temp2_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1327 store_temp_max_hyst, 1),
1328 SENSOR_ATTR(temp3_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1329 store_temp_max_hyst, 2),
1330 SENSOR_ATTR(temp4_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1331 store_temp_max_hyst, 3),
1332 SENSOR_ATTR(temp5_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1333 store_temp_max_hyst, 4),
1334 SENSOR_ATTR(temp6_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1335 store_temp_max_hyst, 5),
1336 SENSOR_ATTR(temp7_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1337 store_temp_max_hyst, 6),
1338 SENSOR_ATTR(temp8_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1339 store_temp_max_hyst, 7),
1340 SENSOR_ATTR(temp9_max_hyst, S_IRUGO | S_IWUSR, show_temp_max_hyst,
1341 store_temp_max_hyst, 8),
1342 };
1343
1344 static struct sensor_device_attribute sda_temp_alarm[] = {
1345 SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1346 SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1347 SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
1348 };
1349
1350 static struct sensor_device_attribute sda_temp_type[] = {
1351 SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
1352 SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
1353 SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
1354 };
1355
1356 static struct sensor_device_attribute sda_temp_offset[] = {
1357 SENSOR_ATTR(temp1_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1358 store_temp_offset, 0),
1359 SENSOR_ATTR(temp2_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1360 store_temp_offset, 1),
1361 SENSOR_ATTR(temp3_offset, S_IRUGO | S_IWUSR, show_temp_offset,
1362 store_temp_offset, 2),
1363 };
1364
1365 #define show_pwm_reg(reg) \
1366 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1367 char *buf) \
1368 { \
1369 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1370 struct sensor_device_attribute *sensor_attr = \
1371 to_sensor_dev_attr(attr); \
1372 int nr = sensor_attr->index; \
1373 return sprintf(buf, "%d\n", data->reg[nr]); \
1374 }
1375
1376 show_pwm_reg(pwm_mode)
1377 show_pwm_reg(pwm_enable)
1378 show_pwm_reg(pwm)
1379
1380 static ssize_t
1381 store_pwm_mode(struct device *dev, struct device_attribute *attr,
1382 const char *buf, size_t count)
1383 {
1384 struct w83627ehf_data *data = dev_get_drvdata(dev);
1385 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1386 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1387 int nr = sensor_attr->index;
1388 unsigned long val;
1389 int err;
1390 u16 reg;
1391
1392 err = kstrtoul(buf, 10, &val);
1393 if (err < 0)
1394 return err;
1395
1396 if (val > 1)
1397 return -EINVAL;
1398
1399 /* On NCT67766F, DC mode is only supported for pwm1 */
1400 if (sio_data->kind == nct6776 && nr && val != 1)
1401 return -EINVAL;
1402
1403 mutex_lock(&data->update_lock);
1404 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1405 data->pwm_mode[nr] = val;
1406 reg &= ~(1 << W83627EHF_PWM_MODE_SHIFT[nr]);
1407 if (!val)
1408 reg |= 1 << W83627EHF_PWM_MODE_SHIFT[nr];
1409 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1410 mutex_unlock(&data->update_lock);
1411 return count;
1412 }
1413
1414 static ssize_t
1415 store_pwm(struct device *dev, struct device_attribute *attr,
1416 const char *buf, size_t count)
1417 {
1418 struct w83627ehf_data *data = dev_get_drvdata(dev);
1419 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1420 int nr = sensor_attr->index;
1421 unsigned long val;
1422 int err;
1423
1424 err = kstrtoul(buf, 10, &val);
1425 if (err < 0)
1426 return err;
1427
1428 val = SENSORS_LIMIT(val, 0, 255);
1429
1430 mutex_lock(&data->update_lock);
1431 data->pwm[nr] = val;
1432 w83627ehf_write_value(data, data->REG_PWM[nr], val);
1433 mutex_unlock(&data->update_lock);
1434 return count;
1435 }
1436
1437 static ssize_t
1438 store_pwm_enable(struct device *dev, struct device_attribute *attr,
1439 const char *buf, size_t count)
1440 {
1441 struct w83627ehf_data *data = dev_get_drvdata(dev);
1442 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1443 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1444 int nr = sensor_attr->index;
1445 unsigned long val;
1446 int err;
1447 u16 reg;
1448
1449 err = kstrtoul(buf, 10, &val);
1450 if (err < 0)
1451 return err;
1452
1453 if (!val || (val > 4 && val != data->pwm_enable_orig[nr]))
1454 return -EINVAL;
1455 /* SmartFan III mode is not supported on NCT6776F */
1456 if (sio_data->kind == nct6776 && val == 4)
1457 return -EINVAL;
1458
1459 mutex_lock(&data->update_lock);
1460 data->pwm_enable[nr] = val;
1461 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1462 reg = w83627ehf_read_value(data,
1463 NCT6775_REG_FAN_MODE[nr]);
1464 reg &= 0x0f;
1465 reg |= (val - 1) << 4;
1466 w83627ehf_write_value(data,
1467 NCT6775_REG_FAN_MODE[nr], reg);
1468 } else {
1469 reg = w83627ehf_read_value(data, W83627EHF_REG_PWM_ENABLE[nr]);
1470 reg &= ~(0x03 << W83627EHF_PWM_ENABLE_SHIFT[nr]);
1471 reg |= (val - 1) << W83627EHF_PWM_ENABLE_SHIFT[nr];
1472 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[nr], reg);
1473 }
1474 mutex_unlock(&data->update_lock);
1475 return count;
1476 }
1477
1478
1479 #define show_tol_temp(reg) \
1480 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1481 char *buf) \
1482 { \
1483 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1484 struct sensor_device_attribute *sensor_attr = \
1485 to_sensor_dev_attr(attr); \
1486 int nr = sensor_attr->index; \
1487 return sprintf(buf, "%d\n", data->reg[nr] * 1000); \
1488 }
1489
1490 show_tol_temp(tolerance)
1491 show_tol_temp(target_temp)
1492
1493 static ssize_t
1494 store_target_temp(struct device *dev, struct device_attribute *attr,
1495 const char *buf, size_t count)
1496 {
1497 struct w83627ehf_data *data = dev_get_drvdata(dev);
1498 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1499 int nr = sensor_attr->index;
1500 long val;
1501 int err;
1502
1503 err = kstrtol(buf, 10, &val);
1504 if (err < 0)
1505 return err;
1506
1507 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 127);
1508
1509 mutex_lock(&data->update_lock);
1510 data->target_temp[nr] = val;
1511 w83627ehf_write_value(data, data->REG_TARGET[nr], val);
1512 mutex_unlock(&data->update_lock);
1513 return count;
1514 }
1515
1516 static ssize_t
1517 store_tolerance(struct device *dev, struct device_attribute *attr,
1518 const char *buf, size_t count)
1519 {
1520 struct w83627ehf_data *data = dev_get_drvdata(dev);
1521 struct w83627ehf_sio_data *sio_data = dev->platform_data;
1522 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1523 int nr = sensor_attr->index;
1524 u16 reg;
1525 long val;
1526 int err;
1527
1528 err = kstrtol(buf, 10, &val);
1529 if (err < 0)
1530 return err;
1531
1532 /* Limit the temp to 0C - 15C */
1533 val = SENSORS_LIMIT(DIV_ROUND_CLOSEST(val, 1000), 0, 15);
1534
1535 mutex_lock(&data->update_lock);
1536 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
1537 /* Limit tolerance further for NCT6776F */
1538 if (sio_data->kind == nct6776 && val > 7)
1539 val = 7;
1540 reg = w83627ehf_read_value(data, NCT6775_REG_FAN_MODE[nr]);
1541 reg = (reg & 0xf0) | val;
1542 w83627ehf_write_value(data, NCT6775_REG_FAN_MODE[nr], reg);
1543 } else {
1544 reg = w83627ehf_read_value(data, W83627EHF_REG_TOLERANCE[nr]);
1545 if (nr == 1)
1546 reg = (reg & 0x0f) | (val << 4);
1547 else
1548 reg = (reg & 0xf0) | val;
1549 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
1550 }
1551 data->tolerance[nr] = val;
1552 mutex_unlock(&data->update_lock);
1553 return count;
1554 }
1555
1556 static struct sensor_device_attribute sda_pwm[] = {
1557 SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0),
1558 SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 1),
1559 SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 2),
1560 SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO, show_pwm, store_pwm, 3),
1561 };
1562
1563 static struct sensor_device_attribute sda_pwm_mode[] = {
1564 SENSOR_ATTR(pwm1_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1565 store_pwm_mode, 0),
1566 SENSOR_ATTR(pwm2_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1567 store_pwm_mode, 1),
1568 SENSOR_ATTR(pwm3_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1569 store_pwm_mode, 2),
1570 SENSOR_ATTR(pwm4_mode, S_IWUSR | S_IRUGO, show_pwm_mode,
1571 store_pwm_mode, 3),
1572 };
1573
1574 static struct sensor_device_attribute sda_pwm_enable[] = {
1575 SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1576 store_pwm_enable, 0),
1577 SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1578 store_pwm_enable, 1),
1579 SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1580 store_pwm_enable, 2),
1581 SENSOR_ATTR(pwm4_enable, S_IWUSR | S_IRUGO, show_pwm_enable,
1582 store_pwm_enable, 3),
1583 };
1584
1585 static struct sensor_device_attribute sda_target_temp[] = {
1586 SENSOR_ATTR(pwm1_target, S_IWUSR | S_IRUGO, show_target_temp,
1587 store_target_temp, 0),
1588 SENSOR_ATTR(pwm2_target, S_IWUSR | S_IRUGO, show_target_temp,
1589 store_target_temp, 1),
1590 SENSOR_ATTR(pwm3_target, S_IWUSR | S_IRUGO, show_target_temp,
1591 store_target_temp, 2),
1592 SENSOR_ATTR(pwm4_target, S_IWUSR | S_IRUGO, show_target_temp,
1593 store_target_temp, 3),
1594 };
1595
1596 static struct sensor_device_attribute sda_tolerance[] = {
1597 SENSOR_ATTR(pwm1_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1598 store_tolerance, 0),
1599 SENSOR_ATTR(pwm2_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1600 store_tolerance, 1),
1601 SENSOR_ATTR(pwm3_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1602 store_tolerance, 2),
1603 SENSOR_ATTR(pwm4_tolerance, S_IWUSR | S_IRUGO, show_tolerance,
1604 store_tolerance, 3),
1605 };
1606
1607 /* Smart Fan registers */
1608
1609 #define fan_functions(reg, REG) \
1610 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1611 char *buf) \
1612 { \
1613 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1614 struct sensor_device_attribute *sensor_attr = \
1615 to_sensor_dev_attr(attr); \
1616 int nr = sensor_attr->index; \
1617 return sprintf(buf, "%d\n", data->reg[nr]); \
1618 } \
1619 static ssize_t \
1620 store_##reg(struct device *dev, struct device_attribute *attr, \
1621 const char *buf, size_t count) \
1622 { \
1623 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1624 struct sensor_device_attribute *sensor_attr = \
1625 to_sensor_dev_attr(attr); \
1626 int nr = sensor_attr->index; \
1627 unsigned long val; \
1628 int err; \
1629 err = kstrtoul(buf, 10, &val); \
1630 if (err < 0) \
1631 return err; \
1632 val = SENSORS_LIMIT(val, 1, 255); \
1633 mutex_lock(&data->update_lock); \
1634 data->reg[nr] = val; \
1635 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
1636 mutex_unlock(&data->update_lock); \
1637 return count; \
1638 }
1639
1640 fan_functions(fan_start_output, FAN_START_OUTPUT)
1641 fan_functions(fan_stop_output, FAN_STOP_OUTPUT)
1642 fan_functions(fan_max_output, FAN_MAX_OUTPUT)
1643 fan_functions(fan_step_output, FAN_STEP_OUTPUT)
1644
1645 #define fan_time_functions(reg, REG) \
1646 static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
1647 char *buf) \
1648 { \
1649 struct w83627ehf_data *data = w83627ehf_update_device(dev); \
1650 struct sensor_device_attribute *sensor_attr = \
1651 to_sensor_dev_attr(attr); \
1652 int nr = sensor_attr->index; \
1653 return sprintf(buf, "%d\n", \
1654 step_time_from_reg(data->reg[nr], \
1655 data->pwm_mode[nr])); \
1656 } \
1657 \
1658 static ssize_t \
1659 store_##reg(struct device *dev, struct device_attribute *attr, \
1660 const char *buf, size_t count) \
1661 { \
1662 struct w83627ehf_data *data = dev_get_drvdata(dev); \
1663 struct sensor_device_attribute *sensor_attr = \
1664 to_sensor_dev_attr(attr); \
1665 int nr = sensor_attr->index; \
1666 unsigned long val; \
1667 int err; \
1668 err = kstrtoul(buf, 10, &val); \
1669 if (err < 0) \
1670 return err; \
1671 val = step_time_to_reg(val, data->pwm_mode[nr]); \
1672 mutex_lock(&data->update_lock); \
1673 data->reg[nr] = val; \
1674 w83627ehf_write_value(data, data->REG_##REG[nr], val); \
1675 mutex_unlock(&data->update_lock); \
1676 return count; \
1677 } \
1678
1679 fan_time_functions(fan_stop_time, FAN_STOP_TIME)
1680
1681 static ssize_t show_name(struct device *dev, struct device_attribute *attr,
1682 char *buf)
1683 {
1684 struct w83627ehf_data *data = dev_get_drvdata(dev);
1685
1686 return sprintf(buf, "%s\n", data->name);
1687 }
1688 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1689
1690 static struct sensor_device_attribute sda_sf3_arrays_fan4[] = {
1691 SENSOR_ATTR(pwm4_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1692 store_fan_stop_time, 3),
1693 SENSOR_ATTR(pwm4_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1694 store_fan_start_output, 3),
1695 SENSOR_ATTR(pwm4_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1696 store_fan_stop_output, 3),
1697 SENSOR_ATTR(pwm4_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1698 store_fan_max_output, 3),
1699 SENSOR_ATTR(pwm4_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1700 store_fan_step_output, 3),
1701 };
1702
1703 static struct sensor_device_attribute sda_sf3_arrays_fan3[] = {
1704 SENSOR_ATTR(pwm3_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1705 store_fan_stop_time, 2),
1706 SENSOR_ATTR(pwm3_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1707 store_fan_start_output, 2),
1708 SENSOR_ATTR(pwm3_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1709 store_fan_stop_output, 2),
1710 };
1711
1712 static struct sensor_device_attribute sda_sf3_arrays[] = {
1713 SENSOR_ATTR(pwm1_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1714 store_fan_stop_time, 0),
1715 SENSOR_ATTR(pwm2_stop_time, S_IWUSR | S_IRUGO, show_fan_stop_time,
1716 store_fan_stop_time, 1),
1717 SENSOR_ATTR(pwm1_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1718 store_fan_start_output, 0),
1719 SENSOR_ATTR(pwm2_start_output, S_IWUSR | S_IRUGO, show_fan_start_output,
1720 store_fan_start_output, 1),
1721 SENSOR_ATTR(pwm1_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1722 store_fan_stop_output, 0),
1723 SENSOR_ATTR(pwm2_stop_output, S_IWUSR | S_IRUGO, show_fan_stop_output,
1724 store_fan_stop_output, 1),
1725 };
1726
1727
1728 /*
1729 * pwm1 and pwm3 don't support max and step settings on all chips.
1730 * Need to check support while generating/removing attribute files.
1731 */
1732 static struct sensor_device_attribute sda_sf3_max_step_arrays[] = {
1733 SENSOR_ATTR(pwm1_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1734 store_fan_max_output, 0),
1735 SENSOR_ATTR(pwm1_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1736 store_fan_step_output, 0),
1737 SENSOR_ATTR(pwm2_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1738 store_fan_max_output, 1),
1739 SENSOR_ATTR(pwm2_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1740 store_fan_step_output, 1),
1741 SENSOR_ATTR(pwm3_max_output, S_IWUSR | S_IRUGO, show_fan_max_output,
1742 store_fan_max_output, 2),
1743 SENSOR_ATTR(pwm3_step_output, S_IWUSR | S_IRUGO, show_fan_step_output,
1744 store_fan_step_output, 2),
1745 };
1746
1747 static ssize_t
1748 show_vid(struct device *dev, struct device_attribute *attr, char *buf)
1749 {
1750 struct w83627ehf_data *data = dev_get_drvdata(dev);
1751 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1752 }
1753 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
1754
1755
1756 /* Case open detection */
1757
1758 static ssize_t
1759 show_caseopen(struct device *dev, struct device_attribute *attr, char *buf)
1760 {
1761 struct w83627ehf_data *data = w83627ehf_update_device(dev);
1762
1763 return sprintf(buf, "%d\n",
1764 !!(data->caseopen & to_sensor_dev_attr_2(attr)->index));
1765 }
1766
1767 static ssize_t
1768 clear_caseopen(struct device *dev, struct device_attribute *attr,
1769 const char *buf, size_t count)
1770 {
1771 struct w83627ehf_data *data = dev_get_drvdata(dev);
1772 unsigned long val;
1773 u16 reg, mask;
1774
1775 if (kstrtoul(buf, 10, &val) || val != 0)
1776 return -EINVAL;
1777
1778 mask = to_sensor_dev_attr_2(attr)->nr;
1779
1780 mutex_lock(&data->update_lock);
1781 reg = w83627ehf_read_value(data, W83627EHF_REG_CASEOPEN_CLR);
1782 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1783 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1784 data->valid = 0; /* Force cache refresh */
1785 mutex_unlock(&data->update_lock);
1786
1787 return count;
1788 }
1789
1790 static struct sensor_device_attribute_2 sda_caseopen[] = {
1791 SENSOR_ATTR_2(intrusion0_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1792 clear_caseopen, 0x80, 0x10),
1793 SENSOR_ATTR_2(intrusion1_alarm, S_IWUSR | S_IRUGO, show_caseopen,
1794 clear_caseopen, 0x40, 0x40),
1795 };
1796
1797 /*
1798 * Driver and device management
1799 */
1800
1801 static void w83627ehf_device_remove_files(struct device *dev)
1802 {
1803 /*
1804 * some entries in the following arrays may not have been used in
1805 * device_create_file(), but device_remove_file() will ignore them
1806 */
1807 int i;
1808 struct w83627ehf_data *data = dev_get_drvdata(dev);
1809
1810 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++)
1811 device_remove_file(dev, &sda_sf3_arrays[i].dev_attr);
1812 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
1813 struct sensor_device_attribute *attr =
1814 &sda_sf3_max_step_arrays[i];
1815 if (data->REG_FAN_STEP_OUTPUT &&
1816 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff)
1817 device_remove_file(dev, &attr->dev_attr);
1818 }
1819 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++)
1820 device_remove_file(dev, &sda_sf3_arrays_fan3[i].dev_attr);
1821 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++)
1822 device_remove_file(dev, &sda_sf3_arrays_fan4[i].dev_attr);
1823 for (i = 0; i < data->in_num; i++) {
1824 if ((i == 6) && data->in6_skip)
1825 continue;
1826 device_remove_file(dev, &sda_in_input[i].dev_attr);
1827 device_remove_file(dev, &sda_in_alarm[i].dev_attr);
1828 device_remove_file(dev, &sda_in_min[i].dev_attr);
1829 device_remove_file(dev, &sda_in_max[i].dev_attr);
1830 }
1831 for (i = 0; i < 5; i++) {
1832 device_remove_file(dev, &sda_fan_input[i].dev_attr);
1833 device_remove_file(dev, &sda_fan_alarm[i].dev_attr);
1834 device_remove_file(dev, &sda_fan_div[i].dev_attr);
1835 device_remove_file(dev, &sda_fan_min[i].dev_attr);
1836 }
1837 for (i = 0; i < data->pwm_num; i++) {
1838 device_remove_file(dev, &sda_pwm[i].dev_attr);
1839 device_remove_file(dev, &sda_pwm_mode[i].dev_attr);
1840 device_remove_file(dev, &sda_pwm_enable[i].dev_attr);
1841 device_remove_file(dev, &sda_target_temp[i].dev_attr);
1842 device_remove_file(dev, &sda_tolerance[i].dev_attr);
1843 }
1844 for (i = 0; i < NUM_REG_TEMP; i++) {
1845 if (!(data->have_temp & (1 << i)))
1846 continue;
1847 device_remove_file(dev, &sda_temp_input[i].dev_attr);
1848 device_remove_file(dev, &sda_temp_label[i].dev_attr);
1849 if (i == 2 && data->temp3_val_only)
1850 continue;
1851 device_remove_file(dev, &sda_temp_max[i].dev_attr);
1852 device_remove_file(dev, &sda_temp_max_hyst[i].dev_attr);
1853 if (i > 2)
1854 continue;
1855 device_remove_file(dev, &sda_temp_alarm[i].dev_attr);
1856 device_remove_file(dev, &sda_temp_type[i].dev_attr);
1857 device_remove_file(dev, &sda_temp_offset[i].dev_attr);
1858 }
1859
1860 device_remove_file(dev, &sda_caseopen[0].dev_attr);
1861 device_remove_file(dev, &sda_caseopen[1].dev_attr);
1862
1863 device_remove_file(dev, &dev_attr_name);
1864 device_remove_file(dev, &dev_attr_cpu0_vid);
1865 }
1866
1867 /* Get the monitoring functions started */
1868 static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data,
1869 enum kinds kind)
1870 {
1871 int i;
1872 u8 tmp, diode;
1873
1874 /* Start monitoring is needed */
1875 tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
1876 if (!(tmp & 0x01))
1877 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
1878 tmp | 0x01);
1879
1880 /* Enable temperature sensors if needed */
1881 for (i = 0; i < NUM_REG_TEMP; i++) {
1882 if (!(data->have_temp & (1 << i)))
1883 continue;
1884 if (!data->reg_temp_config[i])
1885 continue;
1886 tmp = w83627ehf_read_value(data,
1887 data->reg_temp_config[i]);
1888 if (tmp & 0x01)
1889 w83627ehf_write_value(data,
1890 data->reg_temp_config[i],
1891 tmp & 0xfe);
1892 }
1893
1894 /* Enable VBAT monitoring if needed */
1895 tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
1896 if (!(tmp & 0x01))
1897 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
1898
1899 /* Get thermal sensor types */
1900 switch (kind) {
1901 case w83627ehf:
1902 diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
1903 break;
1904 case w83627uhg:
1905 diode = 0x00;
1906 break;
1907 default:
1908 diode = 0x70;
1909 }
1910 for (i = 0; i < 3; i++) {
1911 const char *label = NULL;
1912
1913 if (data->temp_label)
1914 label = data->temp_label[data->temp_src[i]];
1915
1916 /* Digital source overrides analog type */
1917 if (label && strncmp(label, "PECI", 4) == 0)
1918 data->temp_type[i] = 6;
1919 else if (label && strncmp(label, "AMD", 3) == 0)
1920 data->temp_type[i] = 5;
1921 else if ((tmp & (0x02 << i)))
1922 data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 3;
1923 else
1924 data->temp_type[i] = 4; /* thermistor */
1925 }
1926 }
1927
1928 static void w82627ehf_swap_tempreg(struct w83627ehf_data *data,
1929 int r1, int r2)
1930 {
1931 u16 tmp;
1932
1933 tmp = data->temp_src[r1];
1934 data->temp_src[r1] = data->temp_src[r2];
1935 data->temp_src[r2] = tmp;
1936
1937 tmp = data->reg_temp[r1];
1938 data->reg_temp[r1] = data->reg_temp[r2];
1939 data->reg_temp[r2] = tmp;
1940
1941 tmp = data->reg_temp_over[r1];
1942 data->reg_temp_over[r1] = data->reg_temp_over[r2];
1943 data->reg_temp_over[r2] = tmp;
1944
1945 tmp = data->reg_temp_hyst[r1];
1946 data->reg_temp_hyst[r1] = data->reg_temp_hyst[r2];
1947 data->reg_temp_hyst[r2] = tmp;
1948
1949 tmp = data->reg_temp_config[r1];
1950 data->reg_temp_config[r1] = data->reg_temp_config[r2];
1951 data->reg_temp_config[r2] = tmp;
1952 }
1953
1954 static void __devinit
1955 w83627ehf_set_temp_reg_ehf(struct w83627ehf_data *data, int n_temp)
1956 {
1957 int i;
1958
1959 for (i = 0; i < n_temp; i++) {
1960 data->reg_temp[i] = W83627EHF_REG_TEMP[i];
1961 data->reg_temp_over[i] = W83627EHF_REG_TEMP_OVER[i];
1962 data->reg_temp_hyst[i] = W83627EHF_REG_TEMP_HYST[i];
1963 data->reg_temp_config[i] = W83627EHF_REG_TEMP_CONFIG[i];
1964 }
1965 }
1966
1967 static void __devinit
1968 w83627ehf_check_fan_inputs(const struct w83627ehf_sio_data *sio_data,
1969 struct w83627ehf_data *data)
1970 {
1971 int fan3pin, fan4pin, fan4min, fan5pin, regval;
1972
1973 /* The W83627UHG is simple, only two fan inputs, no config */
1974 if (sio_data->kind == w83627uhg) {
1975 data->has_fan = 0x03; /* fan1 and fan2 */
1976 data->has_fan_min = 0x03;
1977 return;
1978 }
1979
1980 superio_enter(sio_data->sioreg);
1981
1982 /* fan4 and fan5 share some pins with the GPIO and serial flash */
1983 if (sio_data->kind == nct6775) {
1984 /* On NCT6775, fan4 shares pins with the fdc interface */
1985 fan3pin = 1;
1986 fan4pin = !(superio_inb(sio_data->sioreg, 0x2A) & 0x80);
1987 fan4min = 0;
1988 fan5pin = 0;
1989 } else if (sio_data->kind == nct6776) {
1990 bool gpok = superio_inb(sio_data->sioreg, 0x27) & 0x80;
1991
1992 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
1993 regval = superio_inb(sio_data->sioreg, SIO_REG_ENABLE);
1994
1995 if (regval & 0x80)
1996 fan3pin = gpok;
1997 else
1998 fan3pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x40);
1999
2000 if (regval & 0x40)
2001 fan4pin = gpok;
2002 else
2003 fan4pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x01);
2004
2005 if (regval & 0x20)
2006 fan5pin = gpok;
2007 else
2008 fan5pin = !!(superio_inb(sio_data->sioreg, 0x1C) & 0x02);
2009
2010 fan4min = fan4pin;
2011 } else if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b) {
2012 fan3pin = 1;
2013 fan4pin = superio_inb(sio_data->sioreg, 0x27) & 0x40;
2014 fan5pin = superio_inb(sio_data->sioreg, 0x27) & 0x20;
2015 fan4min = fan4pin;
2016 } else {
2017 fan3pin = 1;
2018 fan4pin = !(superio_inb(sio_data->sioreg, 0x29) & 0x06);
2019 fan5pin = !(superio_inb(sio_data->sioreg, 0x24) & 0x02);
2020 fan4min = fan4pin;
2021 }
2022
2023 superio_exit(sio_data->sioreg);
2024
2025 data->has_fan = data->has_fan_min = 0x03; /* fan1 and fan2 */
2026 data->has_fan |= (fan3pin << 2);
2027 data->has_fan_min |= (fan3pin << 2);
2028
2029 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2030 /*
2031 * NCT6775F and NCT6776F don't have the W83627EHF_REG_FANDIV1
2032 * register
2033 */
2034 data->has_fan |= (fan4pin << 3) | (fan5pin << 4);
2035 data->has_fan_min |= (fan4min << 3) | (fan5pin << 4);
2036 } else {
2037 /*
2038 * It looks like fan4 and fan5 pins can be alternatively used
2039 * as fan on/off switches, but fan5 control is write only :/
2040 * We assume that if the serial interface is disabled, designers
2041 * connected fan5 as input unless they are emitting log 1, which
2042 * is not the default.
2043 */
2044 regval = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
2045 if ((regval & (1 << 2)) && fan4pin) {
2046 data->has_fan |= (1 << 3);
2047 data->has_fan_min |= (1 << 3);
2048 }
2049 if (!(regval & (1 << 1)) && fan5pin) {
2050 data->has_fan |= (1 << 4);
2051 data->has_fan_min |= (1 << 4);
2052 }
2053 }
2054 }
2055
2056 static int __devinit w83627ehf_probe(struct platform_device *pdev)
2057 {
2058 struct device *dev = &pdev->dev;
2059 struct w83627ehf_sio_data *sio_data = dev->platform_data;
2060 struct w83627ehf_data *data;
2061 struct resource *res;
2062 u8 en_vrm10;
2063 int i, err = 0;
2064
2065 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
2066 if (!request_region(res->start, IOREGION_LENGTH, DRVNAME)) {
2067 err = -EBUSY;
2068 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
2069 (unsigned long)res->start,
2070 (unsigned long)res->start + IOREGION_LENGTH - 1);
2071 goto exit;
2072 }
2073
2074 data = devm_kzalloc(&pdev->dev, sizeof(struct w83627ehf_data),
2075 GFP_KERNEL);
2076 if (!data) {
2077 err = -ENOMEM;
2078 goto exit_release;
2079 }
2080
2081 data->addr = res->start;
2082 mutex_init(&data->lock);
2083 mutex_init(&data->update_lock);
2084 data->name = w83627ehf_device_names[sio_data->kind];
2085 data->bank = 0xff; /* Force initial bank selection */
2086 platform_set_drvdata(pdev, data);
2087
2088 /* 627EHG and 627EHF have 10 voltage inputs; 627DHG and 667HG have 9 */
2089 data->in_num = (sio_data->kind == w83627ehf) ? 10 : 9;
2090 /* 667HG, NCT6775F, and NCT6776F have 3 pwms, and 627UHG has only 2 */
2091 switch (sio_data->kind) {
2092 default:
2093 data->pwm_num = 4;
2094 break;
2095 case w83667hg:
2096 case w83667hg_b:
2097 case nct6775:
2098 case nct6776:
2099 data->pwm_num = 3;
2100 break;
2101 case w83627uhg:
2102 data->pwm_num = 2;
2103 break;
2104 }
2105
2106 /* Default to 3 temperature inputs, code below will adjust as needed */
2107 data->have_temp = 0x07;
2108
2109 /* Deal with temperature register setup first. */
2110 if (sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2111 int mask = 0;
2112
2113 /*
2114 * Display temperature sensor output only if it monitors
2115 * a source other than one already reported. Always display
2116 * first three temperature registers, though.
2117 */
2118 for (i = 0; i < NUM_REG_TEMP; i++) {
2119 u8 src;
2120
2121 data->reg_temp[i] = NCT6775_REG_TEMP[i];
2122 data->reg_temp_over[i] = NCT6775_REG_TEMP_OVER[i];
2123 data->reg_temp_hyst[i] = NCT6775_REG_TEMP_HYST[i];
2124 data->reg_temp_config[i] = NCT6775_REG_TEMP_CONFIG[i];
2125
2126 src = w83627ehf_read_value(data,
2127 NCT6775_REG_TEMP_SOURCE[i]);
2128 src &= 0x1f;
2129 if (src && !(mask & (1 << src))) {
2130 data->have_temp |= 1 << i;
2131 mask |= 1 << src;
2132 }
2133
2134 data->temp_src[i] = src;
2135
2136 /*
2137 * Now do some register swapping if index 0..2 don't
2138 * point to SYSTIN(1), CPUIN(2), and AUXIN(3).
2139 * Idea is to have the first three attributes
2140 * report SYSTIN, CPUIN, and AUXIN if possible
2141 * without overriding the basic system configuration.
2142 */
2143 if (i > 0 && data->temp_src[0] != 1
2144 && data->temp_src[i] == 1)
2145 w82627ehf_swap_tempreg(data, 0, i);
2146 if (i > 1 && data->temp_src[1] != 2
2147 && data->temp_src[i] == 2)
2148 w82627ehf_swap_tempreg(data, 1, i);
2149 if (i > 2 && data->temp_src[2] != 3
2150 && data->temp_src[i] == 3)
2151 w82627ehf_swap_tempreg(data, 2, i);
2152 }
2153 if (sio_data->kind == nct6776) {
2154 /*
2155 * On NCT6776, AUXTIN and VIN3 pins are shared.
2156 * Only way to detect it is to check if AUXTIN is used
2157 * as a temperature source, and if that source is
2158 * enabled.
2159 *
2160 * If that is the case, disable in6, which reports VIN3.
2161 * Otherwise disable temp3.
2162 */
2163 if (data->temp_src[2] == 3) {
2164 u8 reg;
2165
2166 if (data->reg_temp_config[2])
2167 reg = w83627ehf_read_value(data,
2168 data->reg_temp_config[2]);
2169 else
2170 reg = 0; /* Assume AUXTIN is used */
2171
2172 if (reg & 0x01)
2173 data->have_temp &= ~(1 << 2);
2174 else
2175 data->in6_skip = 1;
2176 }
2177 data->temp_label = nct6776_temp_label;
2178 } else {
2179 data->temp_label = nct6775_temp_label;
2180 }
2181 data->have_temp_offset = data->have_temp & 0x07;
2182 for (i = 0; i < 3; i++) {
2183 if (data->temp_src[i] > 3)
2184 data->have_temp_offset &= ~(1 << i);
2185 }
2186 } else if (sio_data->kind == w83667hg_b) {
2187 u8 reg;
2188
2189 w83627ehf_set_temp_reg_ehf(data, 4);
2190
2191 /*
2192 * Temperature sources are selected with bank 0, registers 0x49
2193 * and 0x4a.
2194 */
2195 reg = w83627ehf_read_value(data, 0x4a);
2196 data->temp_src[0] = reg >> 5;
2197 reg = w83627ehf_read_value(data, 0x49);
2198 data->temp_src[1] = reg & 0x07;
2199 data->temp_src[2] = (reg >> 4) & 0x07;
2200
2201 /*
2202 * W83667HG-B has another temperature register at 0x7e.
2203 * The temperature source is selected with register 0x7d.
2204 * Support it if the source differs from already reported
2205 * sources.
2206 */
2207 reg = w83627ehf_read_value(data, 0x7d);
2208 reg &= 0x07;
2209 if (reg != data->temp_src[0] && reg != data->temp_src[1]
2210 && reg != data->temp_src[2]) {
2211 data->temp_src[3] = reg;
2212 data->have_temp |= 1 << 3;
2213 }
2214
2215 /*
2216 * Chip supports either AUXTIN or VIN3. Try to find out which
2217 * one.
2218 */
2219 reg = w83627ehf_read_value(data, W83627EHF_REG_TEMP_CONFIG[2]);
2220 if (data->temp_src[2] == 2 && (reg & 0x01))
2221 data->have_temp &= ~(1 << 2);
2222
2223 if ((data->temp_src[2] == 2 && (data->have_temp & (1 << 2)))
2224 || (data->temp_src[3] == 2 && (data->have_temp & (1 << 3))))
2225 data->in6_skip = 1;
2226
2227 data->temp_label = w83667hg_b_temp_label;
2228 data->have_temp_offset = data->have_temp & 0x07;
2229 for (i = 0; i < 3; i++) {
2230 if (data->temp_src[i] > 2)
2231 data->have_temp_offset &= ~(1 << i);
2232 }
2233 } else if (sio_data->kind == w83627uhg) {
2234 u8 reg;
2235
2236 w83627ehf_set_temp_reg_ehf(data, 3);
2237
2238 /*
2239 * Temperature sources for temp2 and temp3 are selected with
2240 * bank 0, registers 0x49 and 0x4a.
2241 */
2242 data->temp_src[0] = 0; /* SYSTIN */
2243 reg = w83627ehf_read_value(data, 0x49) & 0x07;
2244 /* Adjust to have the same mapping as other source registers */
2245 if (reg == 0)
2246 data->temp_src[1] = 1;
2247 else if (reg >= 2 && reg <= 5)
2248 data->temp_src[1] = reg + 2;
2249 else /* should never happen */
2250 data->have_temp &= ~(1 << 1);
2251 reg = w83627ehf_read_value(data, 0x4a);
2252 data->temp_src[2] = reg >> 5;
2253
2254 /*
2255 * Skip temp3 if source is invalid or the same as temp1
2256 * or temp2.
2257 */
2258 if (data->temp_src[2] == 2 || data->temp_src[2] == 3 ||
2259 data->temp_src[2] == data->temp_src[0] ||
2260 ((data->have_temp & (1 << 1)) &&
2261 data->temp_src[2] == data->temp_src[1]))
2262 data->have_temp &= ~(1 << 2);
2263 else
2264 data->temp3_val_only = 1; /* No limit regs */
2265
2266 data->in6_skip = 1; /* No VIN3 */
2267
2268 data->temp_label = w83667hg_b_temp_label;
2269 data->have_temp_offset = data->have_temp & 0x03;
2270 for (i = 0; i < 3; i++) {
2271 if (data->temp_src[i] > 1)
2272 data->have_temp_offset &= ~(1 << i);
2273 }
2274 } else {
2275 w83627ehf_set_temp_reg_ehf(data, 3);
2276
2277 /* Temperature sources are fixed */
2278
2279 if (sio_data->kind == w83667hg) {
2280 u8 reg;
2281
2282 /*
2283 * Chip supports either AUXTIN or VIN3. Try to find
2284 * out which one.
2285 */
2286 reg = w83627ehf_read_value(data,
2287 W83627EHF_REG_TEMP_CONFIG[2]);
2288 if (reg & 0x01)
2289 data->have_temp &= ~(1 << 2);
2290 else
2291 data->in6_skip = 1;
2292 }
2293 data->have_temp_offset = data->have_temp & 0x07;
2294 }
2295
2296 if (sio_data->kind == nct6775) {
2297 data->has_fan_div = true;
2298 data->fan_from_reg = fan_from_reg16;
2299 data->fan_from_reg_min = fan_from_reg8;
2300 data->REG_PWM = NCT6775_REG_PWM;
2301 data->REG_TARGET = NCT6775_REG_TARGET;
2302 data->REG_FAN = NCT6775_REG_FAN;
2303 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2304 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2305 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2306 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2307 data->REG_FAN_MAX_OUTPUT = NCT6775_REG_FAN_MAX_OUTPUT;
2308 data->REG_FAN_STEP_OUTPUT = NCT6775_REG_FAN_STEP_OUTPUT;
2309 } else if (sio_data->kind == nct6776) {
2310 data->has_fan_div = false;
2311 data->fan_from_reg = fan_from_reg13;
2312 data->fan_from_reg_min = fan_from_reg13;
2313 data->REG_PWM = NCT6775_REG_PWM;
2314 data->REG_TARGET = NCT6775_REG_TARGET;
2315 data->REG_FAN = NCT6775_REG_FAN;
2316 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
2317 data->REG_FAN_START_OUTPUT = NCT6775_REG_FAN_START_OUTPUT;
2318 data->REG_FAN_STOP_OUTPUT = NCT6775_REG_FAN_STOP_OUTPUT;
2319 data->REG_FAN_STOP_TIME = NCT6775_REG_FAN_STOP_TIME;
2320 } else if (sio_data->kind == w83667hg_b) {
2321 data->has_fan_div = true;
2322 data->fan_from_reg = fan_from_reg8;
2323 data->fan_from_reg_min = fan_from_reg8;
2324 data->REG_PWM = W83627EHF_REG_PWM;
2325 data->REG_TARGET = W83627EHF_REG_TARGET;
2326 data->REG_FAN = W83627EHF_REG_FAN;
2327 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2328 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2329 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2330 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
2331 data->REG_FAN_MAX_OUTPUT =
2332 W83627EHF_REG_FAN_MAX_OUTPUT_W83667_B;
2333 data->REG_FAN_STEP_OUTPUT =
2334 W83627EHF_REG_FAN_STEP_OUTPUT_W83667_B;
2335 } else {
2336 data->has_fan_div = true;
2337 data->fan_from_reg = fan_from_reg8;
2338 data->fan_from_reg_min = fan_from_reg8;
2339 data->REG_PWM = W83627EHF_REG_PWM;
2340 data->REG_TARGET = W83627EHF_REG_TARGET;
2341 data->REG_FAN = W83627EHF_REG_FAN;
2342 data->REG_FAN_MIN = W83627EHF_REG_FAN_MIN;
2343 data->REG_FAN_START_OUTPUT = W83627EHF_REG_FAN_START_OUTPUT;
2344 data->REG_FAN_STOP_OUTPUT = W83627EHF_REG_FAN_STOP_OUTPUT;
2345 data->REG_FAN_STOP_TIME = W83627EHF_REG_FAN_STOP_TIME;
2346 data->REG_FAN_MAX_OUTPUT =
2347 W83627EHF_REG_FAN_MAX_OUTPUT_COMMON;
2348 data->REG_FAN_STEP_OUTPUT =
2349 W83627EHF_REG_FAN_STEP_OUTPUT_COMMON;
2350 }
2351
2352 /* Setup input voltage scaling factors */
2353 if (sio_data->kind == w83627uhg)
2354 data->scale_in = scale_in_w83627uhg;
2355 else
2356 data->scale_in = scale_in_common;
2357
2358 /* Initialize the chip */
2359 w83627ehf_init_device(data, sio_data->kind);
2360
2361 data->vrm = vid_which_vrm();
2362 superio_enter(sio_data->sioreg);
2363 /* Read VID value */
2364 if (sio_data->kind == w83667hg || sio_data->kind == w83667hg_b ||
2365 sio_data->kind == nct6775 || sio_data->kind == nct6776) {
2366 /*
2367 * W83667HG has different pins for VID input and output, so
2368 * we can get the VID input values directly at logical device D
2369 * 0xe3.
2370 */
2371 superio_select(sio_data->sioreg, W83667HG_LD_VID);
2372 data->vid = superio_inb(sio_data->sioreg, 0xe3);
2373 err = device_create_file(dev, &dev_attr_cpu0_vid);
2374 if (err)
2375 goto exit_release;
2376 } else if (sio_data->kind != w83627uhg) {
2377 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2378 if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {
2379 /*
2380 * Set VID input sensibility if needed. In theory the
2381 * BIOS should have set it, but in practice it's not
2382 * always the case. We only do it for the W83627EHF/EHG
2383 * because the W83627DHG is more complex in this
2384 * respect.
2385 */
2386 if (sio_data->kind == w83627ehf) {
2387 en_vrm10 = superio_inb(sio_data->sioreg,
2388 SIO_REG_EN_VRM10);
2389 if ((en_vrm10 & 0x08) && data->vrm == 90) {
2390 dev_warn(dev, "Setting VID input "
2391 "voltage to TTL\n");
2392 superio_outb(sio_data->sioreg,
2393 SIO_REG_EN_VRM10,
2394 en_vrm10 & ~0x08);
2395 } else if (!(en_vrm10 & 0x08)
2396 && data->vrm == 100) {
2397 dev_warn(dev, "Setting VID input "
2398 "voltage to VRM10\n");
2399 superio_outb(sio_data->sioreg,
2400 SIO_REG_EN_VRM10,
2401 en_vrm10 | 0x08);
2402 }
2403 }
2404
2405 data->vid = superio_inb(sio_data->sioreg,
2406 SIO_REG_VID_DATA);
2407 if (sio_data->kind == w83627ehf) /* 6 VID pins only */
2408 data->vid &= 0x3f;
2409
2410 err = device_create_file(dev, &dev_attr_cpu0_vid);
2411 if (err)
2412 goto exit_release;
2413 } else {
2414 dev_info(dev, "VID pins in output mode, CPU VID not "
2415 "available\n");
2416 }
2417 }
2418
2419 if (fan_debounce &&
2420 (sio_data->kind == nct6775 || sio_data->kind == nct6776)) {
2421 u8 tmp;
2422
2423 superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
2424 tmp = superio_inb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE);
2425 if (sio_data->kind == nct6776)
2426 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2427 0x3e | tmp);
2428 else
2429 superio_outb(sio_data->sioreg, NCT6775_REG_FAN_DEBOUNCE,
2430 0x1e | tmp);
2431 pr_info("Enabled fan debounce for chip %s\n", data->name);
2432 }
2433
2434 superio_exit(sio_data->sioreg);
2435
2436 w83627ehf_check_fan_inputs(sio_data, data);
2437
2438 /* Read fan clock dividers immediately */
2439 w83627ehf_update_fan_div_common(dev, data);
2440
2441 /* Read pwm data to save original values */
2442 w83627ehf_update_pwm_common(dev, data);
2443 for (i = 0; i < data->pwm_num; i++)
2444 data->pwm_enable_orig[i] = data->pwm_enable[i];
2445
2446 /* Register sysfs hooks */
2447 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays); i++) {
2448 err = device_create_file(dev, &sda_sf3_arrays[i].dev_attr);
2449 if (err)
2450 goto exit_remove;
2451 }
2452
2453 for (i = 0; i < ARRAY_SIZE(sda_sf3_max_step_arrays); i++) {
2454 struct sensor_device_attribute *attr =
2455 &sda_sf3_max_step_arrays[i];
2456 if (data->REG_FAN_STEP_OUTPUT &&
2457 data->REG_FAN_STEP_OUTPUT[attr->index] != 0xff) {
2458 err = device_create_file(dev, &attr->dev_attr);
2459 if (err)
2460 goto exit_remove;
2461 }
2462 }
2463 /* if fan3 and fan4 are enabled create the sf3 files for them */
2464 if ((data->has_fan & (1 << 2)) && data->pwm_num >= 3)
2465 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan3); i++) {
2466 err = device_create_file(dev,
2467 &sda_sf3_arrays_fan3[i].dev_attr);
2468 if (err)
2469 goto exit_remove;
2470 }
2471 if ((data->has_fan & (1 << 3)) && data->pwm_num >= 4)
2472 for (i = 0; i < ARRAY_SIZE(sda_sf3_arrays_fan4); i++) {
2473 err = device_create_file(dev,
2474 &sda_sf3_arrays_fan4[i].dev_attr);
2475 if (err)
2476 goto exit_remove;
2477 }
2478
2479 for (i = 0; i < data->in_num; i++) {
2480 if ((i == 6) && data->in6_skip)
2481 continue;
2482 if ((err = device_create_file(dev, &sda_in_input[i].dev_attr))
2483 || (err = device_create_file(dev,
2484 &sda_in_alarm[i].dev_attr))
2485 || (err = device_create_file(dev,
2486 &sda_in_min[i].dev_attr))
2487 || (err = device_create_file(dev,
2488 &sda_in_max[i].dev_attr)))
2489 goto exit_remove;
2490 }
2491
2492 for (i = 0; i < 5; i++) {
2493 if (data->has_fan & (1 << i)) {
2494 if ((err = device_create_file(dev,
2495 &sda_fan_input[i].dev_attr))
2496 || (err = device_create_file(dev,
2497 &sda_fan_alarm[i].dev_attr)))
2498 goto exit_remove;
2499 if (sio_data->kind != nct6776) {
2500 err = device_create_file(dev,
2501 &sda_fan_div[i].dev_attr);
2502 if (err)
2503 goto exit_remove;
2504 }
2505 if (data->has_fan_min & (1 << i)) {
2506 err = device_create_file(dev,
2507 &sda_fan_min[i].dev_attr);
2508 if (err)
2509 goto exit_remove;
2510 }
2511 if (i < data->pwm_num &&
2512 ((err = device_create_file(dev,
2513 &sda_pwm[i].dev_attr))
2514 || (err = device_create_file(dev,
2515 &sda_pwm_mode[i].dev_attr))
2516 || (err = device_create_file(dev,
2517 &sda_pwm_enable[i].dev_attr))
2518 || (err = device_create_file(dev,
2519 &sda_target_temp[i].dev_attr))
2520 || (err = device_create_file(dev,
2521 &sda_tolerance[i].dev_attr))))
2522 goto exit_remove;
2523 }
2524 }
2525
2526 for (i = 0; i < NUM_REG_TEMP; i++) {
2527 if (!(data->have_temp & (1 << i)))
2528 continue;
2529 err = device_create_file(dev, &sda_temp_input[i].dev_attr);
2530 if (err)
2531 goto exit_remove;
2532 if (data->temp_label) {
2533 err = device_create_file(dev,
2534 &sda_temp_label[i].dev_attr);
2535 if (err)
2536 goto exit_remove;
2537 }
2538 if (i == 2 && data->temp3_val_only)
2539 continue;
2540 if (data->reg_temp_over[i]) {
2541 err = device_create_file(dev,
2542 &sda_temp_max[i].dev_attr);
2543 if (err)
2544 goto exit_remove;
2545 }
2546 if (data->reg_temp_hyst[i]) {
2547 err = device_create_file(dev,
2548 &sda_temp_max_hyst[i].dev_attr);
2549 if (err)
2550 goto exit_remove;
2551 }
2552 if (i > 2)
2553 continue;
2554 if ((err = device_create_file(dev,
2555 &sda_temp_alarm[i].dev_attr))
2556 || (err = device_create_file(dev,
2557 &sda_temp_type[i].dev_attr)))
2558 goto exit_remove;
2559 if (data->have_temp_offset & (1 << i)) {
2560 err = device_create_file(dev,
2561 &sda_temp_offset[i].dev_attr);
2562 if (err)
2563 goto exit_remove;
2564 }
2565 }
2566
2567 err = device_create_file(dev, &sda_caseopen[0].dev_attr);
2568 if (err)
2569 goto exit_remove;
2570
2571 if (sio_data->kind == nct6776) {
2572 err = device_create_file(dev, &sda_caseopen[1].dev_attr);
2573 if (err)
2574 goto exit_remove;
2575 }
2576
2577 err = device_create_file(dev, &dev_attr_name);
2578 if (err)
2579 goto exit_remove;
2580
2581 data->hwmon_dev = hwmon_device_register(dev);
2582 if (IS_ERR(data->hwmon_dev)) {
2583 err = PTR_ERR(data->hwmon_dev);
2584 goto exit_remove;
2585 }
2586
2587 return 0;
2588
2589 exit_remove:
2590 w83627ehf_device_remove_files(dev);
2591 exit_release:
2592 platform_set_drvdata(pdev, NULL);
2593 release_region(res->start, IOREGION_LENGTH);
2594 exit:
2595 return err;
2596 }
2597
2598 static int __devexit w83627ehf_remove(struct platform_device *pdev)
2599 {
2600 struct w83627ehf_data *data = platform_get_drvdata(pdev);
2601
2602 hwmon_device_unregister(data->hwmon_dev);
2603 w83627ehf_device_remove_files(&pdev->dev);
2604 release_region(data->addr, IOREGION_LENGTH);
2605 platform_set_drvdata(pdev, NULL);
2606
2607 return 0;
2608 }
2609
2610 static struct platform_driver w83627ehf_driver = {
2611 .driver = {
2612 .owner = THIS_MODULE,
2613 .name = DRVNAME,
2614 },
2615 .probe = w83627ehf_probe,
2616 .remove = __devexit_p(w83627ehf_remove),
2617 };
2618
2619 /* w83627ehf_find() looks for a '627 in the Super-I/O config space */
2620 static int __init w83627ehf_find(int sioaddr, unsigned short *addr,
2621 struct w83627ehf_sio_data *sio_data)
2622 {
2623 static const char sio_name_W83627EHF[] __initconst = "W83627EHF";
2624 static const char sio_name_W83627EHG[] __initconst = "W83627EHG";
2625 static const char sio_name_W83627DHG[] __initconst = "W83627DHG";
2626 static const char sio_name_W83627DHG_P[] __initconst = "W83627DHG-P";
2627 static const char sio_name_W83627UHG[] __initconst = "W83627UHG";
2628 static const char sio_name_W83667HG[] __initconst = "W83667HG";
2629 static const char sio_name_W83667HG_B[] __initconst = "W83667HG-B";
2630 static const char sio_name_NCT6775[] __initconst = "NCT6775F";
2631 static const char sio_name_NCT6776[] __initconst = "NCT6776F";
2632
2633 u16 val;
2634 const char *sio_name;
2635
2636 superio_enter(sioaddr);
2637
2638 if (force_id)
2639 val = force_id;
2640 else
2641 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8)
2642 | superio_inb(sioaddr, SIO_REG_DEVID + 1);
2643 switch (val & SIO_ID_MASK) {
2644 case SIO_W83627EHF_ID:
2645 sio_data->kind = w83627ehf;
2646 sio_name = sio_name_W83627EHF;
2647 break;
2648 case SIO_W83627EHG_ID:
2649 sio_data->kind = w83627ehf;
2650 sio_name = sio_name_W83627EHG;
2651 break;
2652 case SIO_W83627DHG_ID:
2653 sio_data->kind = w83627dhg;
2654 sio_name = sio_name_W83627DHG;
2655 break;
2656 case SIO_W83627DHG_P_ID:
2657 sio_data->kind = w83627dhg_p;
2658 sio_name = sio_name_W83627DHG_P;
2659 break;
2660 case SIO_W83627UHG_ID:
2661 sio_data->kind = w83627uhg;
2662 sio_name = sio_name_W83627UHG;
2663 break;
2664 case SIO_W83667HG_ID:
2665 sio_data->kind = w83667hg;
2666 sio_name = sio_name_W83667HG;
2667 break;
2668 case SIO_W83667HG_B_ID:
2669 sio_data->kind = w83667hg_b;
2670 sio_name = sio_name_W83667HG_B;
2671 break;
2672 case SIO_NCT6775_ID:
2673 sio_data->kind = nct6775;
2674 sio_name = sio_name_NCT6775;
2675 break;
2676 case SIO_NCT6776_ID:
2677 sio_data->kind = nct6776;
2678 sio_name = sio_name_NCT6776;
2679 break;
2680 default:
2681 if (val != 0xffff)
2682 pr_debug("unsupported chip ID: 0x%04x\n", val);
2683 superio_exit(sioaddr);
2684 return -ENODEV;
2685 }
2686
2687 /* We have a known chip, find the HWM I/O address */
2688 superio_select(sioaddr, W83627EHF_LD_HWM);
2689 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
2690 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
2691 *addr = val & IOREGION_ALIGNMENT;
2692 if (*addr == 0) {
2693 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
2694 superio_exit(sioaddr);
2695 return -ENODEV;
2696 }
2697
2698 /* Activate logical device if needed */
2699 val = superio_inb(sioaddr, SIO_REG_ENABLE);
2700 if (!(val & 0x01)) {
2701 pr_warn("Forcibly enabling Super-I/O. "
2702 "Sensor is probably unusable.\n");
2703 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
2704 }
2705
2706 superio_exit(sioaddr);
2707 pr_info("Found %s chip at %#x\n", sio_name, *addr);
2708 sio_data->sioreg = sioaddr;
2709
2710 return 0;
2711 }
2712
2713 /*
2714 * when Super-I/O functions move to a separate file, the Super-I/O
2715 * bus will manage the lifetime of the device and this module will only keep
2716 * track of the w83627ehf driver. But since we platform_device_alloc(), we
2717 * must keep track of the device
2718 */
2719 static struct platform_device *pdev;
2720
2721 static int __init sensors_w83627ehf_init(void)
2722 {
2723 int err;
2724 unsigned short address;
2725 struct resource res;
2726 struct w83627ehf_sio_data sio_data;
2727
2728 /*
2729 * initialize sio_data->kind and sio_data->sioreg.
2730 *
2731 * when Super-I/O functions move to a separate file, the Super-I/O
2732 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
2733 * w83627ehf hardware monitor, and call probe()
2734 */
2735 if (w83627ehf_find(0x2e, &address, &sio_data) &&
2736 w83627ehf_find(0x4e, &address, &sio_data))
2737 return -ENODEV;
2738
2739 err = platform_driver_register(&w83627ehf_driver);
2740 if (err)
2741 goto exit;
2742
2743 pdev = platform_device_alloc(DRVNAME, address);
2744 if (!pdev) {
2745 err = -ENOMEM;
2746 pr_err("Device allocation failed\n");
2747 goto exit_unregister;
2748 }
2749
2750 err = platform_device_add_data(pdev, &sio_data,
2751 sizeof(struct w83627ehf_sio_data));
2752 if (err) {
2753 pr_err("Platform data allocation failed\n");
2754 goto exit_device_put;
2755 }
2756
2757 memset(&res, 0, sizeof(res));
2758 res.name = DRVNAME;
2759 res.start = address + IOREGION_OFFSET;
2760 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
2761 res.flags = IORESOURCE_IO;
2762
2763 err = acpi_check_resource_conflict(&res);
2764 if (err)
2765 goto exit_device_put;
2766
2767 err = platform_device_add_resources(pdev, &res, 1);
2768 if (err) {
2769 pr_err("Device resource addition failed (%d)\n", err);
2770 goto exit_device_put;
2771 }
2772
2773 /* platform_device_add calls probe() */
2774 err = platform_device_add(pdev);
2775 if (err) {
2776 pr_err("Device addition failed (%d)\n", err);
2777 goto exit_device_put;
2778 }
2779
2780 return 0;
2781
2782 exit_device_put:
2783 platform_device_put(pdev);
2784 exit_unregister:
2785 platform_driver_unregister(&w83627ehf_driver);
2786 exit:
2787 return err;
2788 }
2789
2790 static void __exit sensors_w83627ehf_exit(void)
2791 {
2792 platform_device_unregister(pdev);
2793 platform_driver_unregister(&w83627ehf_driver);
2794 }
2795
2796 MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
2797 MODULE_DESCRIPTION("W83627EHF driver");
2798 MODULE_LICENSE("GPL");
2799
2800 module_init(sensors_w83627ehf_init);
2801 module_exit(sensors_w83627ehf_exit);
Linux with added FPC-III support