arch/arm/boot/dts/dra72-evm-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5 /dts-v1/;
   6
   7 #include "dra72x.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/clock/ti-dra7-atl.h>
  10
  11 / {
  12         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  13
  14         aliases {
  15                 display0 = &hdmi0;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21
  22         evm_12v0: fixedregulator-evm12v0 {
  23                 /* main supply */
  24                 compatible = "regulator-fixed";
  25                 regulator-name = "evm_12v0";
  26                 regulator-min-microvolt = <12000000>;
  27                 regulator-max-microvolt = <12000000>;
  28                 regulator-always-on;
  29                 regulator-boot-on;
  30         };
  31
  32         evm_5v0: fixedregulator-evm5v0 {
  33                 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
  34                 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "evm_5v0";
  37                 regulator-min-microvolt = <5000000>;
  38                 regulator-max-microvolt = <5000000>;
  39                 vin-supply = <&evm_12v0>;
  40                 regulator-always-on;
  41                 regulator-boot-on;
  42         };
  43
  44         evm_3v6: fixedregulator-evm_3v6 {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "evm_3v6";
  47                 regulator-min-microvolt = <3600000>;
  48                 regulator-max-microvolt = <3600000>;
  49                 vin-supply = <&evm_5v0>;
  50                 regulator-always-on;
  51                 regulator-boot-on;
  52         };
  53
  54         vsys_3v3: fixedregulator-vsys3v3 {
  55                 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
  56                 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "vsys_3v3";
  59                 regulator-min-microvolt = <3300000>;
  60                 regulator-max-microvolt = <3300000>;
  61                 vin-supply = <&evm_12v0>;
  62                 regulator-always-on;
  63                 regulator-boot-on;
  64         };
  65
  66         evm_3v3_sw: fixedregulator-evm_3v3 {
  67                 /* TPS22965DSG */
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "evm_3v3";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72                 vin-supply = <&vsys_3v3>;
  73                 regulator-always-on;
  74                 regulator-boot-on;
  75         };
  76
  77         aic_dvdd: fixedregulator-aic_dvdd {
  78                 /* TPS77018DBVT */
  79                 compatible = "regulator-fixed";
  80                 regulator-name = "aic_dvdd";
  81                 vin-supply = <&evm_3v3_sw>;
  82                 regulator-min-microvolt = <1800000>;
  83                 regulator-max-microvolt = <1800000>;
  84         };
  85
  86         evm_3v3_sd: fixedregulator-sd {
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "evm_3v3_sd";
  89                 regulator-min-microvolt = <3300000>;
  90                 regulator-max-microvolt = <3300000>;
  91                 vin-supply = <&evm_3v3_sw>;
  92                 enable-active-high;
  93                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  94         };
  95
  96         extcon_usb1: extcon_usb1 {
  97                 compatible = "linux,extcon-usb-gpio";
  98                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  99         };
 100
 101         extcon_usb2: extcon_usb2 {
 102                 compatible = "linux,extcon-usb-gpio";
 103                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
 104         };
 105
 106         hdmi0: connector {
 107                 compatible = "hdmi-connector";
 108                 label = "hdmi";
 109
 110                 type = "a";
 111
 112                 port {
 113                         hdmi_connector_in: endpoint {
 114                                 remote-endpoint = <&tpd12s015_out>;
 115                         };
 116                 };
 117         };
 118
 119         tpd12s015: encoder {
 120                 compatible = "ti,tpd12s015";
 121
 122                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
 123                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
 124                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
 125
 126                 ports {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129
 130                         port@0 {
 131                                 reg = <0>;
 132
 133                                 tpd12s015_in: endpoint {
 134                                         remote-endpoint = <&hdmi_out>;
 135                                 };
 136                         };
 137
 138                         port@1 {
 139                                 reg = <1>;
 140
 141                                 tpd12s015_out: endpoint {
 142                                         remote-endpoint = <&hdmi_connector_in>;
 143                                 };
 144                         };
 145                 };
 146         };
 147
 148         sound0: sound0 {
 149                 compatible = "simple-audio-card";
 150                 simple-audio-card,name = "DRA7xx-EVM";
 151                 simple-audio-card,widgets =
 152                         "Headphone", "Headphone Jack",
 153                         "Line", "Line Out",
 154                         "Microphone", "Mic Jack",
 155                         "Line", "Line In";
 156                 simple-audio-card,routing =
 157                         "Headphone Jack",       "HPLOUT",
 158                         "Headphone Jack",       "HPROUT",
 159                         "Line Out",             "LLOUT",
 160                         "Line Out",             "RLOUT",
 161                         "MIC3L",                "Mic Jack",
 162                         "MIC3R",                "Mic Jack",
 163                         "Mic Jack",             "Mic Bias",
 164                         "LINE1L",               "Line In",
 165                         "LINE1R",               "Line In";
 166                 simple-audio-card,format = "dsp_b";
 167                 simple-audio-card,bitclock-master = <&sound0_master>;
 168                 simple-audio-card,frame-master = <&sound0_master>;
 169                 simple-audio-card,bitclock-inversion;
 170
 171                 sound0_master: simple-audio-card,cpu {
 172                         sound-dai = <&mcasp3>;
 173                         system-clock-frequency = <5644800>;
 174                 };
 175
 176                 simple-audio-card,codec {
 177                         sound-dai = <&tlv320aic3106>;
 178                         clocks = <&atl_clkin2_ck>;
 179                 };
 180         };
 181
 182         vmmcwl_fixed: fixedregulator-mmcwl {
 183                 compatible = "regulator-fixed";
 184                 regulator-name = "vmmcwl_fixed";
 185                 regulator-min-microvolt = <1800000>;
 186                 regulator-max-microvolt = <1800000>;
 187                 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 188                 enable-active-high;
 189         };
 190
 191         clk_ov5640_fixed: clock {
 192                 compatible = "fixed-clock";
 193                 #clock-cells = <0>;
 194                 clock-frequency = <24000000>;
 195         };
 196 };
 197
 198 &dra7_pmx_core {
 199         dcan1_pins_default: dcan1_pins_default {
 200                 pinctrl-single,pins = <
 201                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 202                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)  /* wakeup0.dcan1_rx */
 203                 >;
 204         };
 205
 206         dcan1_pins_sleep: dcan1_pins_sleep {
 207                 pinctrl-single,pins = <
 208                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 209                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 210                 >;
 211         };
 212 };
 213
 214 &i2c1 {
 215         status = "okay";
 216         clock-frequency = <400000>;
 217
 218         pcf_lcd: gpio@20 {
 219                 compatible = "nxp,pcf8575";
 220                 reg = <0x20>;
 221                 gpio-controller;
 222                 #gpio-cells = <2>;
 223                 interrupt-controller;
 224                 #interrupt-cells = <2>;
 225         };
 226
 227         pcf_gpio_21: gpio@21 {
 228                 compatible = "ti,pcf8575", "nxp,pcf8575";
 229                 reg = <0x21>;
 230                 lines-initial-states = <0x1408>;
 231                 gpio-controller;
 232                 #gpio-cells = <2>;
 233                 interrupt-controller;
 234                 #interrupt-cells = <2>;
 235         };
 236
 237         tlv320aic3106: tlv320aic3106@19 {
 238                 #sound-dai-cells = <0>;
 239                 compatible = "ti,tlv320aic3106";
 240                 reg = <0x19>;
 241                 adc-settle-ms = <40>;
 242                 ai3x-micbias-vg = <1>;          /* 2.0V */
 243                 status = "okay";
 244
 245                 /* Regulators */
 246                 AVDD-supply = <&evm_3v3_sw>;
 247                 IOVDD-supply = <&evm_3v3_sw>;
 248                 DRVDD-supply = <&evm_3v3_sw>;
 249                 DVDD-supply = <&aic_dvdd>;
 250         };
 251 };
 252
 253 &i2c5 {
 254         status = "okay";
 255         clock-frequency = <400000>;
 256
 257         pcf_hdmi: pcf8575@26 {
 258                 compatible = "ti,pcf8575", "nxp,pcf8575";
 259                 reg = <0x26>;
 260                 gpio-controller;
 261                 #gpio-cells = <2>;
 262                 /*
 263                  * initial state is used here to keep the mdio interface
 264                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 265                  * VIN2_S0 driven high otherwise Ethernet stops working
 266                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 267                  */
 268                 lines-initial-states = <0x0f2b>;
 269
 270                 p1 {
 271                         /* vin6_sel_s0: high: VIN6, low: audio */
 272                         gpio-hog;
 273                         gpios = <1 GPIO_ACTIVE_HIGH>;
 274                         output-low;
 275                         line-name = "vin6_sel_s0";
 276                 };
 277         };
 278
 279         ov5640@3c {
 280                 compatible = "ovti,ov5640";
 281                 reg = <0x3c>;
 282
 283                 clocks = <&clk_ov5640_fixed>;
 284                 clock-names = "xclk";
 285
 286                 port {
 287                         csi2_cam0: endpoint {
 288                                 remote-endpoint = <&csi2_phy0>;
 289                                 clock-lanes = <0>;
 290                                 data-lanes = <1 2>;
 291                         };
 292                 };
 293         };
 294
 295 };
 296
 297 &uart1 {
 298         status = "okay";
 299         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 300                               <&dra7_pmx_core 0x3e0>;
 301 };
 302
 303 &elm {
 304         status = "okay";
 305 };
 306
 307 &gpmc {
 308         /*
 309          * For the existing IOdelay configuration via U-Boot we don't
 310          * support NAND on dra72-evm. Keep it disabled. Enabling it
 311          * requires a different configuration by U-Boot.
 312          */
 313         status = "disabled";
 314         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 315         nand@0,0 {
 316                 /* To use NAND, DIP switch SW5 must be set like so:
 317                  * SW5.1 (NAND_SELn) = ON (LOW)
 318                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 319                  */
 320                 compatible = "ti,omap2-nand";
 321                 reg = <0 0 4>;          /* device IO registers */
 322                 interrupt-parent = <&gpmc>;
 323                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 324                              <1 IRQ_TYPE_NONE>; /* termcount */
 325                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
 326                 ti,nand-xfer-type = "prefetch-dma";
 327                 ti,nand-ecc-opt = "bch8";
 328                 ti,elm-id = <&elm>;
 329                 nand-bus-width = <16>;
 330                 gpmc,device-width = <2>;
 331                 gpmc,sync-clk-ps = <0>;
 332                 gpmc,cs-on-ns = <0>;
 333                 gpmc,cs-rd-off-ns = <80>;
 334                 gpmc,cs-wr-off-ns = <80>;
 335                 gpmc,adv-on-ns = <0>;
 336                 gpmc,adv-rd-off-ns = <60>;
 337                 gpmc,adv-wr-off-ns = <60>;
 338                 gpmc,we-on-ns = <10>;
 339                 gpmc,we-off-ns = <50>;
 340                 gpmc,oe-on-ns = <4>;
 341                 gpmc,oe-off-ns = <40>;
 342                 gpmc,access-ns = <40>;
 343                 gpmc,wr-access-ns = <80>;
 344                 gpmc,rd-cycle-ns = <80>;
 345                 gpmc,wr-cycle-ns = <80>;
 346                 gpmc,bus-turnaround-ns = <0>;
 347                 gpmc,cycle2cycle-delay-ns = <0>;
 348                 gpmc,clk-activation-ns = <0>;
 349                 gpmc,wr-data-mux-bus-ns = <0>;
 350                 /* MTD partition table */
 351                 /* All SPL-* partitions are sized to minimal length
 352                  * which can be independently programmable. For
 353                  * NAND flash this is equal to size of erase-block */
 354                 #address-cells = <1>;
 355                 #size-cells = <1>;
 356                 partition@0 {
 357                         label = "NAND.SPL";
 358                         reg = <0x00000000 0x000020000>;
 359                 };
 360                 partition@1 {
 361                         label = "NAND.SPL.backup1";
 362                         reg = <0x00020000 0x00020000>;
 363                 };
 364                 partition@2 {
 365                         label = "NAND.SPL.backup2";
 366                         reg = <0x00040000 0x00020000>;
 367                 };
 368                 partition@3 {
 369                         label = "NAND.SPL.backup3";
 370                         reg = <0x00060000 0x00020000>;
 371                 };
 372                 partition@4 {
 373                         label = "NAND.u-boot-spl-os";
 374                         reg = <0x00080000 0x00040000>;
 375                 };
 376                 partition@5 {
 377                         label = "NAND.u-boot";
 378                         reg = <0x000c0000 0x00100000>;
 379                 };
 380                 partition@6 {
 381                         label = "NAND.u-boot-env";
 382                         reg = <0x001c0000 0x00020000>;
 383                 };
 384                 partition@7 {
 385                         label = "NAND.u-boot-env.backup1";
 386                         reg = <0x001e0000 0x00020000>;
 387                 };
 388                 partition@8 {
 389                         label = "NAND.kernel";
 390                         reg = <0x00200000 0x00800000>;
 391                 };
 392                 partition@9 {
 393                         label = "NAND.file-system";
 394                         reg = <0x00a00000 0x0f600000>;
 395                 };
 396         };
 397 };
 398
 399 &omap_dwc3_1 {
 400         extcon = <&extcon_usb1>;
 401 };
 402
 403 &omap_dwc3_2 {
 404         extcon = <&extcon_usb2>;
 405 };
 406
 407 &usb1 {
 408         dr_mode = "otg";
 409         extcon = <&extcon_usb1>;
 410 };
 411
 412 &usb2 {
 413         dr_mode = "host";
 414         extcon = <&extcon_usb2>;
 415 };
 416
 417 &mmc1 {
 418         status = "okay";
 419         pinctrl-names = "default";
 420         pinctrl-0 = <&mmc1_pins_default>;
 421         vmmc-supply = <&evm_3v3_sd>;
 422         bus-width = <4>;
 423         /*
 424          * SDCD signal is not being used here - using the fact that GPIO mode
 425          * is a viable alternative
 426          */
 427         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 428         max-frequency = <192000000>;
 429 };
 430
 431 &mmc2 {
 432         /* SW5-3 in ON position */
 433         status = "okay";
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&mmc2_pins_default>;
 436         bus-width = <8>;
 437         non-removable;
 438         max-frequency = <192000000>;
 439 };
 440
 441 &mmc4 {
 442         status = "okay";
 443         vmmc-supply = <&evm_3v6>;
 444         vqmmc-supply = <&vmmcwl_fixed>;
 445         bus-width = <4>;
 446         cap-power-off-card;
 447         keep-power-in-suspend;
 448         non-removable;
 449         pinctrl-names = "default", "hs", "sdr12", "sdr25";
 450         pinctrl-0 = <&mmc4_pins_default>;
 451         pinctrl-1 = <&mmc4_pins_default>;
 452         pinctrl-2 = <&mmc4_pins_default>;
 453         pinctrl-3 = <&mmc4_pins_default>;
 454         #address-cells = <1>;
 455         #size-cells = <0>;
 456         wifi@2 {
 457                 compatible = "ti,wl1835";
 458                 reg = <2>;
 459                 interrupt-parent = <&gpio5>;
 460                 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
 461         };
 462 };
 463
 464 &mac {
 465         status = "okay";
 466 };
 467
 468 &dcan1 {
 469         status = "ok";
 470         pinctrl-names = "default", "sleep", "active";
 471         pinctrl-0 = <&dcan1_pins_sleep>;
 472         pinctrl-1 = <&dcan1_pins_sleep>;
 473         pinctrl-2 = <&dcan1_pins_default>;
 474 };
 475
 476 &qspi {
 477         status = "okay";
 478
 479         spi-max-frequency = <76800000>;
 480         m25p80@0 {
 481                 compatible = "s25fl256s1";
 482                 spi-max-frequency = <76800000>;
 483                 reg = <0>;
 484                 spi-tx-bus-width = <1>;
 485                 spi-rx-bus-width = <4>;
 486                 #address-cells = <1>;
 487                 #size-cells = <1>;
 488
 489                 /* MTD partition table.
 490                  * The ROM checks the first four physical blocks
 491                  * for a valid file to boot and the flash here is
 492                  * 64KiB block size.
 493                  */
 494                 partition@0 {
 495                         label = "QSPI.SPL";
 496                         reg = <0x00000000 0x000010000>;
 497                 };
 498                 partition@1 {
 499                         label = "QSPI.SPL.backup1";
 500                         reg = <0x00010000 0x00010000>;
 501                 };
 502                 partition@2 {
 503                         label = "QSPI.SPL.backup2";
 504                         reg = <0x00020000 0x00010000>;
 505                 };
 506                 partition@3 {
 507                         label = "QSPI.SPL.backup3";
 508                         reg = <0x00030000 0x00010000>;
 509                 };
 510                 partition@4 {
 511                         label = "QSPI.u-boot";
 512                         reg = <0x00040000 0x00100000>;
 513                 };
 514                 partition@5 {
 515                         label = "QSPI.u-boot-spl-os";
 516                         reg = <0x00140000 0x00080000>;
 517                 };
 518                 partition@6 {
 519                         label = "QSPI.u-boot-env";
 520                         reg = <0x001c0000 0x00010000>;
 521                 };
 522                 partition@7 {
 523                         label = "QSPI.u-boot-env.backup1";
 524                         reg = <0x001d0000 0x0010000>;
 525                 };
 526                 partition@8 {
 527                         label = "QSPI.kernel";
 528                         reg = <0x001e0000 0x0800000>;
 529                 };
 530                 partition@9 {
 531                         label = "QSPI.file-system";
 532                         reg = <0x009e0000 0x01620000>;
 533                 };
 534         };
 535 };
 536
 537 &dss {
 538         status = "ok";
 539 };
 540
 541 &hdmi {
 542         status = "ok";
 543
 544         port {
 545                 hdmi_out: endpoint {
 546                         remote-endpoint = <&tpd12s015_in>;
 547                 };
 548         };
 549 };
 550
 551 &atl {
 552         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 553                           <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>,
 554                           <&dpll_abe_ck>,
 555                           <&dpll_abe_m2x2_ck>,
 556                           <&atl_clkin2_ck>;
 557         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 558         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 559
 560         status = "okay";
 561
 562         atl2 {
 563                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 564                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 565         };
 566 };
 567
 568 &mcasp3 {
 569         #sound-dai-cells = <0>;
 570
 571         assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
 572         assigned-clock-parents = <&atl_clkin2_ck>;
 573
 574         status = "okay";
 575
 576         op-mode = <0>;          /* MCASP_IIS_MODE */
 577         tdm-slots = <2>;
 578         /* 4 serializer */
 579         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 580                 1 2 0 0
 581         >;
 582         tx-num-evt = <32>;
 583         rx-num-evt = <32>;
 584 };
 585
 586 &mailbox5 {
 587         status = "okay";
 588         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 589                 status = "okay";
 590         };
 591         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 592                 status = "okay";
 593         };
 594 };
 595
 596 &mailbox6 {
 597         status = "okay";
 598         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 599                 status = "okay";
 600         };
 601 };
 602
 603 &pcie1_rc {
 604         status = "okay";
 605 };
 606
 607 &csi2_0 {
 608         csi2_phy0: endpoint {
 609                 remote-endpoint = <&csi2_cam0>;
 610                 clock-lanes = <0>;
 611                 data-lanes = <1 2>;
 612         };
 613 };