| blob | edd3abb9a9f19f8ff3fa531a9422ce22d47cda7c |
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP.
5 *
6 */
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
13 / {
14 #address-cells = <1>;
15 #size-cells = <1>;
17 aliases {
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 gpio5 = &gpio6;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 mmc0 = &usdhc1;
28 mmc1 = &usdhc2;
29 mmc2 = &usdhc3;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 spi0 = &ecspi1;
36 spi1 = &ecspi2;
37 spi3 = &ecspi3;
38 spi4 = &ecspi4;
39 usbphy0 = &usbphy1;
40 usbphy1 = &usbphy2;
41 };
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
48 compatible = "arm,cortex-a9";
49 device_type = "cpu";
50 reg = <0>;
51 next-level-cache = <&L2>;
52 operating-points = <
53 /* kHz uV */
54 996000 1275000
55 792000 1175000
56 396000 1075000
57 198000 975000
58 >;
59 fsl,soc-operating-points = <
60 /* ARM kHz SOC-PU uV */
61 996000 1175000
62 792000 1175000
63 396000 1175000
64 198000 1175000
65 >;
66 clock-latency = <61036>; /* two CLK32 periods */
67 #cooling-cells = <2>;
68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
73 clock-names = "arm", "pll2_pfd2_396m", "step",
74 "pll1_sw", "pll1_sys";
75 nvmem-cells = <&cpu_speed_grade>;
76 nvmem-cell-names = "speed_grade";
77 };
78 };
80 ckil: clock-ckil {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 clock-output-names = "ckil";
85 };
87 osc: clock-osc-24m {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
91 clock-output-names = "osc";
92 };
94 ipp_di0: clock-ipp-di0 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <0>;
98 clock-output-names = "ipp_di0";
99 };
101 ipp_di1: clock-ipp-di1 {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <0>;
105 clock-output-names = "ipp_di1";
106 };
108 tempmon: temperature-sensor {
109 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
110 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
111 interrupt-parent = <&gpc>;
112 fsl,tempmon = <&anatop>;
113 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
114 nvmem-cell-names = "calib", "temp_grade";
115 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
116 };
118 soc {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "simple-bus";
122 interrupt-parent = <&gpc>;
123 ranges;
125 ocram: sram@900000 {
126 compatible = "mmio-sram";
127 reg = <0x00900000 0x20000>;
128 };
130 intc: interrupt-controller@a01000 {
131 compatible = "arm,cortex-a9-gic";
132 #interrupt-cells = <3>;
133 interrupt-controller;
134 reg = <0x00a01000 0x1000>,
135 <0x00a00100 0x100>;
136 interrupt-parent = <&intc>;
137 };
139 L2: l2-cache@a02000 {
140 compatible = "arm,pl310-cache";
141 reg = <0x00a02000 0x1000>;
142 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
143 cache-unified;
144 cache-level = <2>;
145 arm,tag-latency = <4 2 3>;
146 arm,data-latency = <4 2 3>;
147 };
149 aips1: bus@2000000 {
150 compatible = "fsl,aips-bus", "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
153 reg = <0x02000000 0x100000>;
154 ranges;
156 spba: spba-bus@2000000 {
157 compatible = "fsl,spba-bus", "simple-bus";
158 #address-cells = <1>;
159 #size-cells = <1>;
160 reg = <0x02000000 0x40000>;
161 ranges;
163 spdif: spdif@2004000 {
164 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
165 reg = <0x02004000 0x4000>;
166 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
167 dmas = <&sdma 14 18 0>, <&sdma 15 18 0>;
168 dma-names = "rx", "tx";
169 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
170 <&clks IMX6SLL_CLK_OSC>,
171 <&clks IMX6SLL_CLK_SPDIF>,
172 <&clks IMX6SLL_CLK_DUMMY>,
173 <&clks IMX6SLL_CLK_DUMMY>,
174 <&clks IMX6SLL_CLK_DUMMY>,
175 <&clks IMX6SLL_CLK_IPG>,
176 <&clks IMX6SLL_CLK_DUMMY>,
177 <&clks IMX6SLL_CLK_DUMMY>,
178 <&clks IMX6SLL_CLK_SPBA>;
179 clock-names = "core", "rxtx0",
180 "rxtx1", "rxtx2",
181 "rxtx3", "rxtx4",
182 "rxtx5", "rxtx6",
183 "rxtx7", "dma";
184 status = "disabled";
185 };
187 ecspi1: spi@2008000 {
188 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
189 reg = <0x02008000 0x4000>;
190 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
191 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
192 dma-names = "rx", "tx";
193 clocks = <&clks IMX6SLL_CLK_ECSPI1>,
194 <&clks IMX6SLL_CLK_ECSPI1>;
195 clock-names = "ipg", "per";
196 status = "disabled";
197 };
199 ecspi2: spi@200c000 {
200 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
201 reg = <0x0200c000 0x4000>;
202 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
203 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
204 dma-names = "rx", "tx";
205 clocks = <&clks IMX6SLL_CLK_ECSPI2>,
206 <&clks IMX6SLL_CLK_ECSPI2>;
207 clock-names = "ipg", "per";
208 status = "disabled";
209 };
211 ecspi3: spi@2010000 {
212 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
213 reg = <0x02010000 0x4000>;
214 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
215 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
216 dma-names = "rx", "tx";
217 clocks = <&clks IMX6SLL_CLK_ECSPI3>,
218 <&clks IMX6SLL_CLK_ECSPI3>;
219 clock-names = "ipg", "per";
220 status = "disabled";
221 };
223 ecspi4: spi@2014000 {
224 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
225 reg = <0x02014000 0x4000>;
226 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
227 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
228 dma-names = "rx", "tx";
229 clocks = <&clks IMX6SLL_CLK_ECSPI4>,
230 <&clks IMX6SLL_CLK_ECSPI4>;
231 clock-names = "ipg", "per";
232 status = "disabled";
233 };
235 uart4: serial@2018000 {
236 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
237 "fsl,imx21-uart";
238 reg = <0x02018000 0x4000>;
239 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
240 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
241 dma-names = "rx", "tx";
242 clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
243 <&clks IMX6SLL_CLK_UART4_SERIAL>;
244 clock-names = "ipg", "per";
245 status = "disabled";
246 };
248 uart1: serial@2020000 {
249 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
250 "fsl,imx21-uart";
251 reg = <0x02020000 0x4000>;
252 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
253 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
254 dma-names = "rx", "tx";
255 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
256 <&clks IMX6SLL_CLK_UART1_SERIAL>;
257 clock-names = "ipg", "per";
258 status = "disabled";
259 };
261 uart2: serial@2024000 {
262 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
263 "fsl,imx21-uart";
264 reg = <0x02024000 0x4000>;
265 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
266 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
267 dma-names = "rx", "tx";
268 clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
269 <&clks IMX6SLL_CLK_UART2_SERIAL>;
270 clock-names = "ipg", "per";
271 status = "disabled";
272 };
274 ssi1: ssi-controller@2028000 {
275 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
276 reg = <0x02028000 0x4000>;
277 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
278 dmas = <&sdma 37 22 0>, <&sdma 38 22 0>;
279 dma-names = "rx", "tx";
280 fsl,fifo-depth = <15>;
281 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
282 <&clks IMX6SLL_CLK_SSI1>;
283 clock-names = "ipg", "baud";
284 status = "disabled";
285 };
287 ssi2: ssi-controller@202c000 {
288 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
289 reg = <0x0202c000 0x4000>;
290 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
291 dmas = <&sdma 41 22 0>, <&sdma 42 22 0>;
292 dma-names = "rx", "tx";
293 fsl,fifo-depth = <15>;
294 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
295 <&clks IMX6SLL_CLK_SSI2>;
296 clock-names = "ipg", "baud";
297 status = "disabled";
298 };
300 ssi3: ssi-controller@2030000 {
301 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
302 reg = <0x02030000 0x4000>;
303 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
304 dmas = <&sdma 45 22 0>, <&sdma 46 22 0>;
305 dma-names = "rx", "tx";
306 fsl,fifo-depth = <15>;
307 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
308 <&clks IMX6SLL_CLK_SSI3>;
309 clock-names = "ipg", "baud";
310 status = "disabled";
311 };
313 uart3: serial@2034000 {
314 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
315 "fsl,imx21-uart";
316 reg = <0x02034000 0x4000>;
317 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
318 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
319 dma-name = "rx", "tx";
320 clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
321 <&clks IMX6SLL_CLK_UART3_SERIAL>;
322 clock-names = "ipg", "per";
323 status = "disabled";
324 };
325 };
327 pwm1: pwm@2080000 {
328 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
329 reg = <0x02080000 0x4000>;
330 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clks IMX6SLL_CLK_PWM1>,
332 <&clks IMX6SLL_CLK_PWM1>;
333 clock-names = "ipg", "per";
334 #pwm-cells = <2>;
335 };
337 pwm2: pwm@2084000 {
338 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
339 reg = <0x02084000 0x4000>;
340 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clks IMX6SLL_CLK_PWM2>,
342 <&clks IMX6SLL_CLK_PWM2>;
343 clock-names = "ipg", "per";
344 #pwm-cells = <2>;
345 };
347 pwm3: pwm@2088000 {
348 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
349 reg = <0x02088000 0x4000>;
350 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clks IMX6SLL_CLK_PWM3>,
352 <&clks IMX6SLL_CLK_PWM3>;
353 clock-names = "ipg", "per";
354 #pwm-cells = <2>;
355 };
357 pwm4: pwm@208c000 {
358 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
359 reg = <0x0208c000 0x4000>;
360 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6SLL_CLK_PWM4>,
362 <&clks IMX6SLL_CLK_PWM4>;
363 clock-names = "ipg", "per";
364 #pwm-cells = <2>;
365 };
367 gpt1: timer@2098000 {
368 compatible = "fsl,imx6sl-gpt";
369 reg = <0x02098000 0x4000>;
370 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
372 <&clks IMX6SLL_CLK_GPT_SERIAL>;
373 clock-names = "ipg", "per";
374 };
376 gpio1: gpio@209c000 {
377 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
378 reg = <0x0209c000 0x4000>;
379 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clks IMX6SLL_CLK_GPIO1>;
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
387 };
389 gpio2: gpio@20a0000 {
390 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
391 reg = <0x020a0000 0x4000>;
392 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks IMX6SLL_CLK_GPIO2>;
395 gpio-controller;
396 #gpio-cells = <2>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
399 gpio-ranges = <&iomuxc 0 50 32>;
400 };
402 gpio3: gpio@20a4000 {
403 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
404 reg = <0x020a4000 0x4000>;
405 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clks IMX6SLL_CLK_GPIO3>;
408 gpio-controller;
409 #gpio-cells = <2>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
412 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
413 <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
414 <&iomuxc 21 6 11>;
415 };
417 gpio4: gpio@20a8000 {
418 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
419 reg = <0x020a8000 0x4000>;
420 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&clks IMX6SLL_CLK_GPIO4>;
423 gpio-controller;
424 #gpio-cells = <2>;
425 interrupt-controller;
426 #interrupt-cells = <2>;
427 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
428 <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
429 <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
430 <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
431 <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
432 <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
433 <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
434 <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
435 <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
436 };
438 gpio5: gpio@20ac000 {
439 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
440 reg = <0x020ac000 0x4000>;
441 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX6SLL_CLK_GPIO5>;
444 gpio-controller;
445 #gpio-cells = <2>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
449 <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
450 <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
451 <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
452 <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
453 <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
454 <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
455 <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
456 <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
457 <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
458 <&iomuxc 21 137 1>;
459 };
461 gpio6: gpio@20b0000 {
462 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
463 reg = <0x020b0000 0x4000>;
464 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clks IMX6SLL_CLK_GPIO6>;
467 gpio-controller;
468 #gpio-cells = <2>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 };
473 kpp: keypad@20b8000 {
474 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
475 reg = <0x020b8000 0x4000>;
476 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clks IMX6SLL_CLK_KPP>;
478 status = "disabled";
479 };
481 wdog1: watchdog@20bc000 {
482 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
483 reg = <0x020bc000 0x4000>;
484 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clks IMX6SLL_CLK_WDOG1>;
486 };
488 wdog2: watchdog@20c0000 {
489 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
490 reg = <0x020c0000 0x4000>;
491 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&clks IMX6SLL_CLK_WDOG2>;
493 status = "disabled";
494 };
496 clks: clock-controller@20c4000 {
497 compatible = "fsl,imx6sll-ccm";
498 reg = <0x020c4000 0x4000>;
499 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
501 #clock-cells = <1>;
502 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
503 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
505 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
506 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
507 };
509 anatop: anatop@20c8000 {
510 compatible = "fsl,imx6sll-anatop",
511 "fsl,imx6q-anatop",
512 "syscon", "simple-mfd";
513 reg = <0x020c8000 0x4000>;
514 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
518 #size-cells = <0>;
520 reg_3p0: regulator-3p0@20c8120 {
521 compatible = "fsl,anatop-regulator";
522 reg = <0x20c8120>;
523 regulator-name = "vdd3p0";
524 regulator-min-microvolt = <2625000>;
525 regulator-max-microvolt = <3400000>;
526 anatop-reg-offset = <0x120>;
527 anatop-vol-bit-shift = <8>;
528 anatop-vol-bit-width = <5>;
529 anatop-min-bit-val = <0>;
530 anatop-min-voltage = <2625000>;
531 anatop-max-voltage = <3400000>;
532 anatop-enable-bit = <0>;
533 };
534 };
536 usbphy1: usb-phy@20c9000 {
537 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
538 "fsl,imx23-usbphy";
539 reg = <0x020c9000 0x1000>;
540 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
542 phy-3p0-supply = <®_3p0>;
543 fsl,anatop = <&anatop>;
544 };
546 usbphy2: usb-phy@20ca000 {
547 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
548 "fsl,imx23-usbphy";
549 reg = <0x020ca000 0x1000>;
550 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
552 phy-reg_3p0-supply = <®_3p0>;
553 fsl,anatop = <&anatop>;
554 };
556 snvs: snvs@20cc000 {
557 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
558 reg = <0x020cc000 0x4000>;
560 snvs_rtc: snvs-rtc-lp {
561 compatible = "fsl,sec-v4.0-mon-rtc-lp";
562 regmap = <&snvs>;
563 offset = <0x34>;
564 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
566 };
568 snvs_poweroff: snvs-poweroff {
569 compatible = "syscon-poweroff";
570 regmap = <&snvs>;
571 offset = <0x38>;
572 mask = <0x61>;
573 status = "disabled";
574 };
576 snvs_pwrkey: snvs-powerkey {
577 compatible = "fsl,sec-v4.0-pwrkey";
578 regmap = <&snvs>;
579 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
580 linux,keycode = <KEY_POWER>;
581 wakeup-source;
582 status = "disabled";
583 };
584 };
586 src: reset-controller@20d8000 {
587 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
588 reg = <0x020d8000 0x4000>;
589 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
591 #reset-cells = <1>;
592 };
594 gpc: interrupt-controller@20dc000 {
595 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
596 reg = <0x020dc000 0x4000>;
597 interrupt-controller;
598 #interrupt-cells = <3>;
599 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
600 interrupt-parent = <&intc>;
601 };
603 iomuxc: pinctrl@20e0000 {
604 compatible = "fsl,imx6sll-iomuxc";
605 reg = <0x020e0000 0x4000>;
606 };
608 gpr: iomuxc-gpr@20e4000 {
609 compatible = "fsl,imx6sll-iomuxc-gpr",
610 "fsl,imx6q-iomuxc-gpr", "syscon";
611 reg = <0x020e4000 0x4000>;
612 };
614 csi: csi@20e8000 {
615 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
616 reg = <0x020e8000 0x4000>;
617 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&clks IMX6SLL_CLK_DUMMY>,
619 <&clks IMX6SLL_CLK_CSI>,
620 <&clks IMX6SLL_CLK_DUMMY>;
621 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
622 status = "disabled";
623 };
625 sdma: dma-controller@20ec000 {
626 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
627 reg = <0x020ec000 0x4000>;
628 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clks IMX6SLL_CLK_IPG>,
630 <&clks IMX6SLL_CLK_SDMA>;
631 clock-names = "ipg", "ahb";
632 #dma-cells = <3>;
633 iram = <&ocram>;
634 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
635 };
637 pxp: pxp@20f0000 {
638 compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
639 reg = <0x20f0000 0x4000>;
640 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&clks IMX6SLL_CLK_PXP>;
643 clock-names = "axi";
644 };
646 lcdif: lcd-controller@20f8000 {
647 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
648 reg = <0x020f8000 0x4000>;
649 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
651 <&clks IMX6SLL_CLK_LCDIF_APB>,
652 <&clks IMX6SLL_CLK_DUMMY>;
653 clock-names = "pix", "axi", "disp_axi";
654 status = "disabled";
655 };
657 dcp: crypto@20fc000 {
658 compatible = "fsl,imx28-dcp";
659 reg = <0x020fc000 0x4000>;
660 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&clks IMX6SLL_CLK_DCP>;
664 clock-names = "dcp";
665 };
666 };
668 aips2: bus@2100000 {
669 compatible = "fsl,aips-bus", "simple-bus";
670 #address-cells = <1>;
671 #size-cells = <1>;
672 reg = <0x02100000 0x100000>;
673 ranges;
675 usbotg1: usb@2184000 {
676 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
677 "fsl,imx27-usb";
678 reg = <0x02184000 0x200>;
679 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clks IMX6SLL_CLK_USBOH3>;
681 fsl,usbphy = <&usbphy1>;
682 fsl,usbmisc = <&usbmisc 0>;
683 fsl,anatop = <&anatop>;
684 ahb-burst-config = <0x0>;
685 tx-burst-size-dword = <0x10>;
686 rx-burst-size-dword = <0x10>;
687 status = "disabled";
688 };
690 usbotg2: usb@2184200 {
691 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
692 "fsl,imx27-usb";
693 reg = <0x02184200 0x200>;
694 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&clks IMX6SLL_CLK_USBOH3>;
696 fsl,usbphy = <&usbphy2>;
697 fsl,usbmisc = <&usbmisc 1>;
698 ahb-burst-config = <0x0>;
699 tx-burst-size-dword = <0x10>;
700 rx-burst-size-dword = <0x10>;
701 status = "disabled";
702 };
704 usbmisc: usbmisc@2184800 {
705 #index-cells = <1>;
706 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
707 "fsl,imx6q-usbmisc";
708 reg = <0x02184800 0x200>;
709 };
711 usdhc1: mmc@2190000 {
712 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
713 reg = <0x02190000 0x4000>;
714 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clks IMX6SLL_CLK_USDHC1>,
716 <&clks IMX6SLL_CLK_USDHC1>,
717 <&clks IMX6SLL_CLK_USDHC1>;
718 clock-names = "ipg", "ahb", "per";
719 bus-width = <4>;
720 fsl,tuning-step = <2>;
721 fsl,tuning-start-tap = <20>;
722 status = "disabled";
723 };
725 usdhc2: mmc@2194000 {
726 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
727 reg = <0x02194000 0x4000>;
728 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clks IMX6SLL_CLK_USDHC2>,
730 <&clks IMX6SLL_CLK_USDHC2>,
731 <&clks IMX6SLL_CLK_USDHC2>;
732 clock-names = "ipg", "ahb", "per";
733 bus-width = <4>;
734 fsl,tuning-step = <2>;
735 fsl,tuning-start-tap = <20>;
736 status = "disabled";
737 };
739 usdhc3: mmc@2198000 {
740 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
741 reg = <0x02198000 0x4000>;
742 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clks IMX6SLL_CLK_USDHC3>,
744 <&clks IMX6SLL_CLK_USDHC3>,
745 <&clks IMX6SLL_CLK_USDHC3>;
746 clock-names = "ipg", "ahb", "per";
747 bus-width = <4>;
748 fsl,tuning-step = <2>;
749 fsl,tuning-start-tap = <20>;
750 status = "disabled";
751 };
753 i2c1: i2c@21a0000 {
754 #address-cells = <1>;
755 #size-cells = <0>;
756 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
757 reg = <0x021a0000 0x4000>;
758 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clks IMX6SLL_CLK_I2C1>;
760 status = "disabled";
761 };
763 i2c2: i2c@21a4000 {
764 #address-cells = <1>;
765 #size-cells = <0>;
766 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
767 reg = <0x021a4000 0x4000>;
768 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&clks IMX6SLL_CLK_I2C2>;
770 status = "disabled";
771 };
773 i2c3: i2c@21a8000 {
774 #address-cells = <1>;
775 #size-cells = <0>;
776 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
777 reg = <0x021a8000 0x4000>;
778 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clks IMX6SLL_CLK_I2C3>;
780 status = "disabled";
781 };
783 mmdc: memory-controller@21b0000 {
784 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
785 reg = <0x021b0000 0x4000>;
786 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
787 };
789 ocotp: ocotp-ctrl@21bc000 {
790 #address-cells = <1>;
791 #size-cells = <1>;
792 compatible = "fsl,imx6sll-ocotp", "syscon";
793 reg = <0x021bc000 0x4000>;
794 clocks = <&clks IMX6SLL_CLK_OCOTP>;
796 cpu_speed_grade: speed-grade@10 {
797 reg = <0x10 4>;
798 };
800 tempmon_calib: calib@38 {
801 reg = <0x38 4>;
802 };
804 tempmon_temp_grade: temp-grade@20 {
805 reg = <0x20 4>;
806 };
807 };
809 audmux: audmux@21d8000 {
810 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
811 reg = <0x021d8000 0x4000>;
812 status = "disabled";
813 };
815 uart5: serial@21f4000 {
816 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
817 "fsl,imx21-uart";
818 reg = <0x021f4000 0x4000>;
819 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
820 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
821 dma-names = "rx", "tx";
822 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
823 <&clks IMX6SLL_CLK_UART5_SERIAL>;
824 clock-names = "ipg", "per";
825 status = "disabled";
826 };
827 };
828 };
829 };