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Linux 5.7.6
[linux/fpc-iii.git] / arch / arm / mach-davinci / board-dm644x-evm.c
bloba5d3708fedf68c35a545cdfb6acffb9466de45cb
1 /*
2 * TI DaVinci EVM board support
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
16 #include <linux/gpio/machine.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_data/pcf857x.h>
19 #include <linux/platform_data/gpio-davinci.h>
20 #include <linux/property.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/rawnand.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/mtd/physmap.h>
25 #include <linux/nvmem-provider.h>
26 #include <linux/phy.h>
27 #include <linux/clk.h>
28 #include <linux/videodev2.h>
29 #include <linux/v4l2-dv-timings.h>
30 #include <linux/export.h>
31 #include <linux/leds.h>
32 #include <linux/regulator/fixed.h>
33 #include <linux/regulator/machine.h>
34
35 #include <media/i2c/tvp514x.h>
36
37 #include <asm/mach-types.h>
38 #include <asm/mach/arch.h>
39
40 #include <mach/common.h>
41 #include <mach/mux.h>
42 #include <mach/serial.h>
43
44 #include <linux/platform_data/i2c-davinci.h>
45 #include <linux/platform_data/mtd-davinci.h>
46 #include <linux/platform_data/mmc-davinci.h>
47 #include <linux/platform_data/usb-davinci.h>
48 #include <linux/platform_data/mtd-davinci-aemif.h>
49 #include <linux/platform_data/ti-aemif.h>
50
51 #include "davinci.h"
52 #include "irqs.h"
53
54 #define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
55 #define LXT971_PHY_ID (0x001378e2)
56 #define LXT971_PHY_MASK (0xfffffff0)
57
58 static struct mtd_partition davinci_evm_norflash_partitions[] = {
59 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
60 {
61 .name = "bootloader",
62 .offset = 0,
63 .size = 5 * SZ_64K,
64 .mask_flags = MTD_WRITEABLE, /* force read-only */
65 },
66 /* bootloader params in the next 1 sectors */
67 {
68 .name = "params",
69 .offset = MTDPART_OFS_APPEND,
70 .size = SZ_64K,
71 .mask_flags = 0,
72 },
73 /* kernel */
74 {
75 .name = "kernel",
76 .offset = MTDPART_OFS_APPEND,
77 .size = SZ_2M,
78 .mask_flags = 0
79 },
80 /* file system */
81 {
82 .name = "filesystem",
83 .offset = MTDPART_OFS_APPEND,
84 .size = MTDPART_SIZ_FULL,
85 .mask_flags = 0
86 }
87 };
88
89 static struct physmap_flash_data davinci_evm_norflash_data = {
90 .width = 2,
91 .parts = davinci_evm_norflash_partitions,
92 .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
93 };
94
95 /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
96 * limits addresses to 16M, so using addresses past 16M will wrap */
97 static struct resource davinci_evm_norflash_resource = {
98 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
99 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
100 .flags = IORESOURCE_MEM,
101 };
102
103 static struct platform_device davinci_evm_norflash_device = {
104 .name = "physmap-flash",
105 .id = 0,
106 .dev = {
107 .platform_data = &davinci_evm_norflash_data,
108 },
109 .num_resources = 1,
110 .resource = &davinci_evm_norflash_resource,
111 };
112
113 /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
114 * It may used instead of the (default) NOR chip to boot, using TI's
115 * tools to install the secondary boot loader (UBL) and U-Boot.
116 */
117 static struct mtd_partition davinci_evm_nandflash_partition[] = {
118 /* Bootloader layout depends on whose u-boot is installed, but we
119 * can hide all the details.
120 * - block 0 for u-boot environment ... in mainline u-boot
121 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
122 * - blocks 6...? for u-boot
123 * - blocks 16..23 for u-boot environment ... in TI's u-boot
124 */
125 {
126 .name = "bootloader",
127 .offset = 0,
128 .size = SZ_256K + SZ_128K,
129 .mask_flags = MTD_WRITEABLE, /* force read-only */
130 },
131 /* Kernel */
132 {
133 .name = "kernel",
134 .offset = MTDPART_OFS_APPEND,
135 .size = SZ_4M,
136 .mask_flags = 0,
137 },
138 /* File system (older GIT kernels started this on the 5MB mark) */
139 {
140 .name = "filesystem",
141 .offset = MTDPART_OFS_APPEND,
142 .size = MTDPART_SIZ_FULL,
143 .mask_flags = 0,
144 }
145 /* A few blocks at end hold a flash BBT ... created by TI's CCS
146 * using flashwriter_nand.out, but ignored by TI's versions of
147 * Linux and u-boot. We boot faster by using them.
148 */
149 };
150
151 static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
152 .wsetup = 20,
153 .wstrobe = 40,
154 .whold = 20,
155 .rsetup = 10,
156 .rstrobe = 40,
157 .rhold = 10,
158 .ta = 40,
159 };
160
161 static struct davinci_nand_pdata davinci_evm_nandflash_data = {
162 .core_chipsel = 0,
163 .parts = davinci_evm_nandflash_partition,
164 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
165 .ecc_mode = NAND_ECC_HW,
166 .ecc_bits = 1,
167 .bbt_options = NAND_BBT_USE_FLASH,
168 .timing = &davinci_evm_nandflash_timing,
169 };
170
171 static struct resource davinci_evm_nandflash_resource[] = {
172 {
173 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
174 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
175 .flags = IORESOURCE_MEM,
176 }, {
177 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
178 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
179 .flags = IORESOURCE_MEM,
180 },
181 };
182
183 static struct resource davinci_evm_aemif_resource[] = {
184 {
185 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
186 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
187 .flags = IORESOURCE_MEM,
188 },
189 };
190
191 static struct aemif_abus_data davinci_evm_aemif_abus_data[] = {
192 {
193 .cs = 1,
194 },
195 };
196
197 static struct platform_device davinci_evm_nandflash_devices[] = {
198 {
199 .name = "davinci_nand",
200 .id = 0,
201 .dev = {
202 .platform_data = &davinci_evm_nandflash_data,
203 },
204 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
205 .resource = davinci_evm_nandflash_resource,
206 },
207 };
208
209 static struct aemif_platform_data davinci_evm_aemif_pdata = {
210 .abus_data = davinci_evm_aemif_abus_data,
211 .num_abus_data = ARRAY_SIZE(davinci_evm_aemif_abus_data),
212 .sub_devices = davinci_evm_nandflash_devices,
213 .num_sub_devices = ARRAY_SIZE(davinci_evm_nandflash_devices),
214 };
215
216 static struct platform_device davinci_evm_aemif_device = {
217 .name = "ti-aemif",
218 .id = -1,
219 .dev = {
220 .platform_data = &davinci_evm_aemif_pdata,
221 },
222 .resource = davinci_evm_aemif_resource,
223 .num_resources = ARRAY_SIZE(davinci_evm_aemif_resource),
224 };
225
226 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
227
228 static struct platform_device davinci_fb_device = {
229 .name = "davincifb",
230 .id = -1,
231 .dev = {
232 .dma_mask = &davinci_fb_dma_mask,
233 .coherent_dma_mask = DMA_BIT_MASK(32),
234 },
235 .num_resources = 0,
236 };
237
238 static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
239 .clk_polarity = 0,
240 .hs_polarity = 1,
241 .vs_polarity = 1
242 };
243
244 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
245 /* Inputs available at the TVP5146 */
246 static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
247 {
248 .index = 0,
249 .name = "Composite",
250 .type = V4L2_INPUT_TYPE_CAMERA,
251 .std = TVP514X_STD_ALL,
252 },
253 {
254 .index = 1,
255 .name = "S-Video",
256 .type = V4L2_INPUT_TYPE_CAMERA,
257 .std = TVP514X_STD_ALL,
258 },
259 };
260
261 /*
262 * this is the route info for connecting each input to decoder
263 * ouput that goes to vpfe. There is a one to one correspondence
264 * with tvp5146_inputs
265 */
266 static struct vpfe_route dm644xevm_tvp5146_routes[] = {
267 {
268 .input = INPUT_CVBS_VI2B,
269 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
270 },
271 {
272 .input = INPUT_SVIDEO_VI2C_VI1C,
273 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
274 },
275 };
276
277 static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
278 {
279 .name = "tvp5146",
280 .grp_id = 0,
281 .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
282 .inputs = dm644xevm_tvp5146_inputs,
283 .routes = dm644xevm_tvp5146_routes,
284 .can_route = 1,
285 .ccdc_if_params = {
286 .if_type = VPFE_BT656,
287 .hdpol = VPFE_PINPOL_POSITIVE,
288 .vdpol = VPFE_PINPOL_POSITIVE,
289 },
290 .board_info = {
291 I2C_BOARD_INFO("tvp5146", 0x5d),
292 .platform_data = &dm644xevm_tvp5146_pdata,
293 },
294 },
295 };
296
297 static struct vpfe_config dm644xevm_capture_cfg = {
298 .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
299 .i2c_adapter_id = 1,
300 .sub_devs = dm644xevm_vpfe_sub_devs,
301 .card_name = "DM6446 EVM",
302 .ccdc = "DM6446 CCDC",
303 };
304
305 static struct platform_device rtc_dev = {
306 .name = "rtc_davinci_evm",
307 .id = -1,
308 };
309
310 /*----------------------------------------------------------------------*/
311 #ifdef CONFIG_I2C
312 /*
313 * I2C GPIO expanders
314 */
315
316 #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
317
318
319 /* U2 -- LEDs */
320
321 static struct gpio_led evm_leds[] = {
322 { .name = "DS8", .active_low = 1,
323 .default_trigger = "heartbeat", },
324 { .name = "DS7", .active_low = 1, },
325 { .name = "DS6", .active_low = 1, },
326 { .name = "DS5", .active_low = 1, },
327 { .name = "DS4", .active_low = 1, },
328 { .name = "DS3", .active_low = 1, },
329 { .name = "DS2", .active_low = 1,
330 .default_trigger = "mmc0", },
331 { .name = "DS1", .active_low = 1,
332 .default_trigger = "disk-activity", },
333 };
334
335 static const struct gpio_led_platform_data evm_led_data = {
336 .num_leds = ARRAY_SIZE(evm_leds),
337 .leds = evm_leds,
338 };
339
340 static struct platform_device *evm_led_dev;
341
342 static int
343 evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
344 {
345 struct gpio_led *leds = evm_leds;
346 int status;
347
348 while (ngpio--) {
349 leds->gpio = gpio++;
350 leds++;
351 }
352
353 /* what an extremely annoying way to be forced to handle
354 * device unregistration ...
355 */
356 evm_led_dev = platform_device_alloc("leds-gpio", 0);
357 platform_device_add_data(evm_led_dev,
358 &evm_led_data, sizeof evm_led_data);
359
360 evm_led_dev->dev.parent = &client->dev;
361 status = platform_device_add(evm_led_dev);
362 if (status < 0) {
363 platform_device_put(evm_led_dev);
364 evm_led_dev = NULL;
365 }
366 return status;
367 }
368
369 static int
370 evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
371 {
372 if (evm_led_dev) {
373 platform_device_unregister(evm_led_dev);
374 evm_led_dev = NULL;
375 }
376 return 0;
377 }
378
379 static struct pcf857x_platform_data pcf_data_u2 = {
380 .gpio_base = PCF_Uxx_BASE(0),
381 .setup = evm_led_setup,
382 .teardown = evm_led_teardown,
383 };
384
385
386 /* U18 - A/V clock generator and user switch */
387
388 static int sw_gpio;
389
390 static ssize_t
391 sw_show(struct device *d, struct device_attribute *a, char *buf)
392 {
393 char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
394
395 strcpy(buf, s);
396 return strlen(s);
397 }
398
399 static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
400
401 static int
402 evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
403 {
404 int status;
405
406 /* export dip switch option */
407 sw_gpio = gpio + 7;
408 status = gpio_request(sw_gpio, "user_sw");
409 if (status == 0)
410 status = gpio_direction_input(sw_gpio);
411 if (status == 0)
412 status = device_create_file(&client->dev, &dev_attr_user_sw);
413 else
414 gpio_free(sw_gpio);
415 if (status != 0)
416 sw_gpio = -EINVAL;
417
418 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
419 gpio_request(gpio + 3, "pll_fs2");
420 gpio_direction_output(gpio + 3, 0);
421
422 gpio_request(gpio + 2, "pll_fs1");
423 gpio_direction_output(gpio + 2, 0);
424
425 gpio_request(gpio + 1, "pll_sr");
426 gpio_direction_output(gpio + 1, 0);
427
428 return 0;
429 }
430
431 static int
432 evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
433 {
434 gpio_free(gpio + 1);
435 gpio_free(gpio + 2);
436 gpio_free(gpio + 3);
437
438 if (sw_gpio > 0) {
439 device_remove_file(&client->dev, &dev_attr_user_sw);
440 gpio_free(sw_gpio);
441 }
442 return 0;
443 }
444
445 static struct pcf857x_platform_data pcf_data_u18 = {
446 .gpio_base = PCF_Uxx_BASE(1),
447 .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
448 .setup = evm_u18_setup,
449 .teardown = evm_u18_teardown,
450 };
451
452
453 /* U35 - various I/O signals used to manage USB, CF, ATA, etc */
454
455 static int
456 evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
457 {
458 /* p0 = nDRV_VBUS (initial: don't supply it) */
459 gpio_request(gpio + 0, "nDRV_VBUS");
460 gpio_direction_output(gpio + 0, 1);
461
462 /* p1 = VDDIMX_EN */
463 gpio_request(gpio + 1, "VDDIMX_EN");
464 gpio_direction_output(gpio + 1, 1);
465
466 /* p2 = VLYNQ_EN */
467 gpio_request(gpio + 2, "VLYNQ_EN");
468 gpio_direction_output(gpio + 2, 1);
469
470 /* p3 = n3V3_CF_RESET (initial: stay in reset) */
471 gpio_request(gpio + 3, "nCF_RESET");
472 gpio_direction_output(gpio + 3, 0);
473
474 /* (p4 unused) */
475
476 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
477 gpio_request(gpio + 5, "WLAN_RESET");
478 gpio_direction_output(gpio + 5, 1);
479
480 /* p6 = nATA_SEL (initial: select) */
481 gpio_request(gpio + 6, "nATA_SEL");
482 gpio_direction_output(gpio + 6, 0);
483
484 /* p7 = nCF_SEL (initial: deselect) */
485 gpio_request(gpio + 7, "nCF_SEL");
486 gpio_direction_output(gpio + 7, 1);
487
488 return 0;
489 }
490
491 static int
492 evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
493 {
494 gpio_free(gpio + 7);
495 gpio_free(gpio + 6);
496 gpio_free(gpio + 5);
497 gpio_free(gpio + 3);
498 gpio_free(gpio + 2);
499 gpio_free(gpio + 1);
500 gpio_free(gpio + 0);
501 return 0;
502 }
503
504 static struct pcf857x_platform_data pcf_data_u35 = {
505 .gpio_base = PCF_Uxx_BASE(2),
506 .setup = evm_u35_setup,
507 .teardown = evm_u35_teardown,
508 };
509
510 /*----------------------------------------------------------------------*/
511
512 /* Most of this EEPROM is unused, but U-Boot uses some data:
513 * - 0x7f00, 6 bytes Ethernet Address
514 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
515 * - ... newer boards may have more
516 */
517
518 static struct nvmem_cell_info dm644evm_nvmem_cells[] = {
519 {
520 .name = "macaddr",
521 .offset = 0x7f00,
522 .bytes = ETH_ALEN,
523 }
524 };
525
526 static struct nvmem_cell_table dm644evm_nvmem_cell_table = {
527 .nvmem_name = "1-00500",
528 .cells = dm644evm_nvmem_cells,
529 .ncells = ARRAY_SIZE(dm644evm_nvmem_cells),
530 };
531
532 static struct nvmem_cell_lookup dm644evm_nvmem_cell_lookup = {
533 .nvmem_name = "1-00500",
534 .cell_name = "macaddr",
535 .dev_id = "davinci_emac.1",
536 .con_id = "mac-address",
537 };
538
539 static const struct property_entry eeprom_properties[] = {
540 PROPERTY_ENTRY_U32("pagesize", 64),
541 { }
542 };
543
544 /*
545 * MSP430 supports RTC, card detection, input from IR remote, and
546 * a bit more. It triggers interrupts on GPIO(7) from pressing
547 * buttons on the IR remote, and for card detect switches.
548 */
549 static struct i2c_client *dm6446evm_msp;
550
551 static int dm6446evm_msp_probe(struct i2c_client *client,
552 const struct i2c_device_id *id)
553 {
554 dm6446evm_msp = client;
555 return 0;
556 }
557
558 static int dm6446evm_msp_remove(struct i2c_client *client)
559 {
560 dm6446evm_msp = NULL;
561 return 0;
562 }
563
564 static const struct i2c_device_id dm6446evm_msp_ids[] = {
565 { "dm6446evm_msp", 0, },
566 { /* end of list */ },
567 };
568
569 static struct i2c_driver dm6446evm_msp_driver = {
570 .driver.name = "dm6446evm_msp",
571 .id_table = dm6446evm_msp_ids,
572 .probe = dm6446evm_msp_probe,
573 .remove = dm6446evm_msp_remove,
574 };
575
576 static int dm6444evm_msp430_get_pins(void)
577 {
578 static const char txbuf[2] = { 2, 4, };
579 char buf[4];
580 struct i2c_msg msg[2] = {
581 {
582 .flags = 0,
583 .len = 2,
584 .buf = (void __force *)txbuf,
585 },
586 {
587 .flags = I2C_M_RD,
588 .len = 4,
589 .buf = buf,
590 },
591 };
592 int status;
593
594 if (!dm6446evm_msp)
595 return -ENXIO;
596
597 msg[0].addr = dm6446evm_msp->addr;
598 msg[1].addr = dm6446evm_msp->addr;
599
600 /* Command 4 == get input state, returns port 2 and port3 data
601 * S Addr W [A] len=2 [A] cmd=4 [A]
602 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
603 */
604 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
605 if (status < 0)
606 return status;
607
608 dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
609
610 return (buf[3] << 8) | buf[2];
611 }
612
613 static int dm6444evm_mmc_get_cd(int module)
614 {
615 int status = dm6444evm_msp430_get_pins();
616
617 return (status < 0) ? status : !(status & BIT(1));
618 }
619
620 static int dm6444evm_mmc_get_ro(int module)
621 {
622 int status = dm6444evm_msp430_get_pins();
623
624 return (status < 0) ? status : status & BIT(6 + 8);
625 }
626
627 static struct davinci_mmc_config dm6446evm_mmc_config = {
628 .get_cd = dm6444evm_mmc_get_cd,
629 .get_ro = dm6444evm_mmc_get_ro,
630 .wires = 4,
631 };
632
633 static struct i2c_board_info __initdata i2c_info[] = {
634 {
635 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
636 },
637 {
638 I2C_BOARD_INFO("pcf8574", 0x38),
639 .platform_data = &pcf_data_u2,
640 },
641 {
642 I2C_BOARD_INFO("pcf8574", 0x39),
643 .platform_data = &pcf_data_u18,
644 },
645 {
646 I2C_BOARD_INFO("pcf8574", 0x3a),
647 .platform_data = &pcf_data_u35,
648 },
649 {
650 I2C_BOARD_INFO("24c256", 0x50),
651 .properties = eeprom_properties,
652 },
653 {
654 I2C_BOARD_INFO("tlv320aic33", 0x1b),
655 },
656 };
657
658 #define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
659 #define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
660
661 static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
662 .dev_id = "i2c_davinci.1",
663 .table = {
664 GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SDA_PIN, "sda",
665 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
666 GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
667 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
668 { }
669 },
670 };
671
672 /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
673 * which requires 100 usec of idle bus after i2c writes sent to it.
674 */
675 static struct davinci_i2c_platform_data i2c_pdata = {
676 .bus_freq = 20 /* kHz */,
677 .bus_delay = 100 /* usec */,
678 .gpio_recovery = true,
679 };
680
681 static void __init evm_init_i2c(void)
682 {
683 gpiod_add_lookup_table(&i2c_recovery_gpiod_table);
684 davinci_init_i2c(&i2c_pdata);
685 i2c_add_driver(&dm6446evm_msp_driver);
686 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
687 }
688 #endif
689
690 /* Fixed regulator support */
691 static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
692 /* Baseboard 3.3V: 5V -> TPS54310PWP -> 3.3V */
693 REGULATOR_SUPPLY("AVDD", "1-001b"),
694 REGULATOR_SUPPLY("DRVDD", "1-001b"),
695 };
696
697 static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
698 /* Baseboard 1.8V: 5V -> TPS54310PWP -> 1.8V */
699 REGULATOR_SUPPLY("IOVDD", "1-001b"),
700 REGULATOR_SUPPLY("DVDD", "1-001b"),
701 };
702
703 #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
704
705 /* venc standard timings */
706 static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
707 {
708 .name = "ntsc",
709 .timings_type = VPBE_ENC_STD,
710 .std_id = V4L2_STD_NTSC,
711 .interlaced = 1,
712 .xres = 720,
713 .yres = 480,
714 .aspect = {11, 10},
715 .fps = {30000, 1001},
716 .left_margin = 0x79,
717 .upper_margin = 0x10,
718 },
719 {
720 .name = "pal",
721 .timings_type = VPBE_ENC_STD,
722 .std_id = V4L2_STD_PAL,
723 .interlaced = 1,
724 .xres = 720,
725 .yres = 576,
726 .aspect = {54, 59},
727 .fps = {25, 1},
728 .left_margin = 0x7e,
729 .upper_margin = 0x16,
730 },
731 };
732
733 /* venc dv preset timings */
734 static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
735 {
736 .name = "480p59_94",
737 .timings_type = VPBE_ENC_DV_TIMINGS,
738 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
739 .interlaced = 0,
740 .xres = 720,
741 .yres = 480,
742 .aspect = {1, 1},
743 .fps = {5994, 100},
744 .left_margin = 0x80,
745 .upper_margin = 0x20,
746 },
747 {
748 .name = "576p50",
749 .timings_type = VPBE_ENC_DV_TIMINGS,
750 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
751 .interlaced = 0,
752 .xres = 720,
753 .yres = 576,
754 .aspect = {1, 1},
755 .fps = {50, 1},
756 .left_margin = 0x7e,
757 .upper_margin = 0x30,
758 },
759 };
760
761 /*
762 * The outputs available from VPBE + encoders. Keep the order same
763 * as that of encoders. First those from venc followed by that from
764 * encoders. Index in the output refers to index on a particular encoder.
765 * Driver uses this index to pass it to encoder when it supports more
766 * than one output. Userspace applications use index of the array to
767 * set an output.
768 */
769 static struct vpbe_output dm644xevm_vpbe_outputs[] = {
770 {
771 .output = {
772 .index = 0,
773 .name = "Composite",
774 .type = V4L2_OUTPUT_TYPE_ANALOG,
775 .std = VENC_STD_ALL,
776 .capabilities = V4L2_OUT_CAP_STD,
777 },
778 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
779 .default_mode = "ntsc",
780 .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
781 .modes = dm644xevm_enc_std_timing,
782 },
783 {
784 .output = {
785 .index = 1,
786 .name = "Component",
787 .type = V4L2_OUTPUT_TYPE_ANALOG,
788 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
789 },
790 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
791 .default_mode = "480p59_94",
792 .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
793 .modes = dm644xevm_enc_preset_timing,
794 },
795 };
796
797 static struct vpbe_config dm644xevm_display_cfg = {
798 .module_name = "dm644x-vpbe-display",
799 .i2c_adapter_id = 1,
800 .osd = {
801 .module_name = DM644X_VPBE_OSD_SUBDEV_NAME,
802 },
803 .venc = {
804 .module_name = DM644X_VPBE_VENC_SUBDEV_NAME,
805 },
806 .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
807 .outputs = dm644xevm_vpbe_outputs,
808 };
809
810 static struct platform_device *davinci_evm_devices[] __initdata = {
811 &davinci_fb_device,
812 &rtc_dev,
813 };
814
815 static void __init
816 davinci_evm_map_io(void)
817 {
818 dm644x_init();
819 }
820
821 static int davinci_phy_fixup(struct phy_device *phydev)
822 {
823 unsigned int control;
824 /* CRITICAL: Fix for increasing PHY signal drive strength for
825 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
826 * signal strength was low causing TX to fail randomly. The
827 * fix is to Set bit 11 (Increased MII drive strength) of PHY
828 * register 26 (Digital Config register) on this phy. */
829 control = phy_read(phydev, 26);
830 phy_write(phydev, 26, (control | 0x800));
831 return 0;
832 }
833
834 #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
835 IS_ENABLED(CONFIG_PATA_BK3710))
836
837 #define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
838
839 #define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
840
841 #define GPIO_nVBUS_DRV 160
842
843 static struct gpiod_lookup_table dm644evm_usb_gpio_table = {
844 .dev_id = "musb-davinci",
845 .table = {
846 GPIO_LOOKUP("davinci_gpio", GPIO_nVBUS_DRV, NULL,
847 GPIO_ACTIVE_HIGH),
848 { }
849 },
850 };
851
852 static __init void davinci_evm_init(void)
853 {
854 int ret;
855 struct clk *aemif_clk;
856 struct davinci_soc_info *soc_info = &davinci_soc_info;
857
858 dm644x_register_clocks();
859
860 regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
861 ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
862 regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
863 ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
864
865 dm644x_init_devices();
866
867 ret = dm644x_gpio_register();
868 if (ret)
869 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
870
871 aemif_clk = clk_get(NULL, "aemif");
872 clk_prepare_enable(aemif_clk);
873
874 if (HAS_ATA) {
875 if (HAS_NAND || HAS_NOR)
876 pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
877 "\tDisable IDE for NAND/NOR support\n");
878 davinci_init_ide();
879 } else if (HAS_NAND || HAS_NOR) {
880 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
881 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
882
883 /* only one device will be jumpered and detected */
884 if (HAS_NAND) {
885 platform_device_register(&davinci_evm_aemif_device);
886 #ifdef CONFIG_I2C
887 evm_leds[7].default_trigger = "nand-disk";
888 #endif
889 if (HAS_NOR)
890 pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
891 } else if (HAS_NOR)
892 platform_device_register(&davinci_evm_norflash_device);
893 }
894
895 platform_add_devices(davinci_evm_devices,
896 ARRAY_SIZE(davinci_evm_devices));
897 #ifdef CONFIG_I2C
898 nvmem_add_cell_table(&dm644evm_nvmem_cell_table);
899 nvmem_add_cell_lookups(&dm644evm_nvmem_cell_lookup, 1);
900 evm_init_i2c();
901 davinci_setup_mmc(0, &dm6446evm_mmc_config);
902 #endif
903 dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
904
905 davinci_serial_init(dm644x_serial_device);
906 dm644x_init_asp();
907
908 /* irlml6401 switches over 1A, in under 8 msec */
909 gpiod_add_lookup_table(&dm644evm_usb_gpio_table);
910 davinci_setup_usb(1000, 8);
911
912 if (IS_BUILTIN(CONFIG_PHYLIB)) {
913 soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
914 /* Register the fixup for PHY on DaVinci */
915 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
916 davinci_phy_fixup);
917 }
918 }
919
920 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
921 /* Maintainer: MontaVista Software <source@mvista.com> */
922 .atag_offset = 0x100,
923 .map_io = davinci_evm_map_io,
924 .init_irq = dm644x_init_irq,
925 .init_time = dm644x_init_time,
926 .init_machine = davinci_evm_init,
927 .init_late = davinci_init_late,
928 .dma_zone_size = SZ_128M,
929 MACHINE_END
Linux with added FPC-III support