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Linux 5.7.6
[linux/fpc-iii.git] / arch / arm / mach-davinci / dm644x.c
blob24988939ae462430617384b035175ef15d8a213b
1 /*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dmaengine.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/irqchip/irq-davinci-aintc.h>
19 #include <linux/platform_data/edma.h>
20 #include <linux/platform_data/gpio-davinci.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_8250.h>
23
24 #include <asm/mach/map.h>
25
26 #include <mach/common.h>
27 #include <mach/cputype.h>
28 #include <mach/mux.h>
29 #include <mach/serial.h>
30
31 #include <clocksource/timer-davinci.h>
32
33 #include "asp.h"
34 #include "davinci.h"
35 #include "irqs.h"
36 #include "mux.h"
37
38 /*
39 * Device specific clocks
40 */
41 #define DM644X_REF_FREQ 27000000
42
43 #define DM644X_EMAC_BASE 0x01c80000
44 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
45 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
46 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
47 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
48 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
49
50 static struct emac_platform_data dm644x_emac_pdata = {
51 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
52 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
53 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
54 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
55 .version = EMAC_VERSION_1,
56 };
57
58 static struct resource dm644x_emac_resources[] = {
59 {
60 .start = DM644X_EMAC_BASE,
61 .end = DM644X_EMAC_BASE + SZ_16K - 1,
62 .flags = IORESOURCE_MEM,
63 },
64 {
65 .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
66 .end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
67 .flags = IORESOURCE_IRQ,
68 },
69 };
70
71 static struct platform_device dm644x_emac_device = {
72 .name = "davinci_emac",
73 .id = 1,
74 .dev = {
75 .platform_data = &dm644x_emac_pdata,
76 },
77 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
78 .resource = dm644x_emac_resources,
79 };
80
81 static struct resource dm644x_mdio_resources[] = {
82 {
83 .start = DM644X_EMAC_MDIO_BASE,
84 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 };
88
89 static struct platform_device dm644x_mdio_device = {
90 .name = "davinci_mdio",
91 .id = 0,
92 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
93 .resource = dm644x_mdio_resources,
94 };
95
96 /*
97 * Device specific mux setup
98 *
99 * soc description mux mode mode mux dbg
100 * reg offset mask mode
101 */
102 static const struct mux_config dm644x_pins[] = {
103 #ifdef CONFIG_DAVINCI_MUX
104 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
105 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
106 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
107
108 MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
109
110 MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
111 MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
112 MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
113 MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
114 MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
115 MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
116
117 MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
118
119 MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
120
121 MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
122
123 MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
124 MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
125
126 MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
127
128 MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
129
130 MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
131
132 MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
133 MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
134 MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
135
136 MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
137
138 MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
139
140 MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
141 MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
142 MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
143 MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
144
145 MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
146
147 MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
148 MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
149 #endif
150 };
151
152 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
153 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
154 [IRQ_VDINT0] = 2,
155 [IRQ_VDINT1] = 6,
156 [IRQ_VDINT2] = 6,
157 [IRQ_HISTINT] = 6,
158 [IRQ_H3AINT] = 6,
159 [IRQ_PRVUINT] = 6,
160 [IRQ_RSZINT] = 6,
161 [7] = 7,
162 [IRQ_VENCINT] = 6,
163 [IRQ_ASQINT] = 6,
164 [IRQ_IMXINT] = 6,
165 [IRQ_VLCDINT] = 6,
166 [IRQ_USBINT] = 4,
167 [IRQ_EMACINT] = 4,
168 [14] = 7,
169 [15] = 7,
170 [IRQ_CCINT0] = 5, /* dma */
171 [IRQ_CCERRINT] = 5, /* dma */
172 [IRQ_TCERRINT0] = 5, /* dma */
173 [IRQ_TCERRINT] = 5, /* dma */
174 [IRQ_PSCIN] = 7,
175 [21] = 7,
176 [IRQ_IDE] = 4,
177 [23] = 7,
178 [IRQ_MBXINT] = 7,
179 [IRQ_MBRINT] = 7,
180 [IRQ_MMCINT] = 7,
181 [IRQ_SDIOINT] = 7,
182 [28] = 7,
183 [IRQ_DDRINT] = 7,
184 [IRQ_AEMIFINT] = 7,
185 [IRQ_VLQINT] = 4,
186 [IRQ_TINT0_TINT12] = 2, /* clockevent */
187 [IRQ_TINT0_TINT34] = 2, /* clocksource */
188 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
189 [IRQ_TINT1_TINT34] = 7, /* system tick */
190 [IRQ_PWMINT0] = 7,
191 [IRQ_PWMINT1] = 7,
192 [IRQ_PWMINT2] = 7,
193 [IRQ_I2C] = 3,
194 [IRQ_UARTINT0] = 3,
195 [IRQ_UARTINT1] = 3,
196 [IRQ_UARTINT2] = 3,
197 [IRQ_SPINT0] = 3,
198 [IRQ_SPINT1] = 3,
199 [45] = 7,
200 [IRQ_DSP2ARM0] = 4,
201 [IRQ_DSP2ARM1] = 4,
202 [IRQ_GPIO0] = 7,
203 [IRQ_GPIO1] = 7,
204 [IRQ_GPIO2] = 7,
205 [IRQ_GPIO3] = 7,
206 [IRQ_GPIO4] = 7,
207 [IRQ_GPIO5] = 7,
208 [IRQ_GPIO6] = 7,
209 [IRQ_GPIO7] = 7,
210 [IRQ_GPIOBNK0] = 7,
211 [IRQ_GPIOBNK1] = 7,
212 [IRQ_GPIOBNK2] = 7,
213 [IRQ_GPIOBNK3] = 7,
214 [IRQ_GPIOBNK4] = 7,
215 [IRQ_COMMTX] = 7,
216 [IRQ_COMMRX] = 7,
217 [IRQ_EMUINT] = 7,
218 };
219
220 /*----------------------------------------------------------------------*/
221
222 static s8 queue_priority_mapping[][2] = {
223 /* {event queue no, Priority} */
224 {0, 3},
225 {1, 7},
226 {-1, -1},
227 };
228
229 static const struct dma_slave_map dm644x_edma_map[] = {
230 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
231 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
232 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
233 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
234 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
235 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
236 };
237
238 static struct edma_soc_info dm644x_edma_pdata = {
239 .queue_priority_mapping = queue_priority_mapping,
240 .default_queue = EVENTQ_1,
241 .slave_map = dm644x_edma_map,
242 .slavecnt = ARRAY_SIZE(dm644x_edma_map),
243 };
244
245 static struct resource edma_resources[] = {
246 {
247 .name = "edma3_cc",
248 .start = 0x01c00000,
249 .end = 0x01c00000 + SZ_64K - 1,
250 .flags = IORESOURCE_MEM,
251 },
252 {
253 .name = "edma3_tc0",
254 .start = 0x01c10000,
255 .end = 0x01c10000 + SZ_1K - 1,
256 .flags = IORESOURCE_MEM,
257 },
258 {
259 .name = "edma3_tc1",
260 .start = 0x01c10400,
261 .end = 0x01c10400 + SZ_1K - 1,
262 .flags = IORESOURCE_MEM,
263 },
264 {
265 .name = "edma3_ccint",
266 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
267 .flags = IORESOURCE_IRQ,
268 },
269 {
270 .name = "edma3_ccerrint",
271 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
272 .flags = IORESOURCE_IRQ,
273 },
274 /* not using TC*_ERR */
275 };
276
277 static const struct platform_device_info dm644x_edma_device __initconst = {
278 .name = "edma",
279 .id = 0,
280 .dma_mask = DMA_BIT_MASK(32),
281 .res = edma_resources,
282 .num_res = ARRAY_SIZE(edma_resources),
283 .data = &dm644x_edma_pdata,
284 .size_data = sizeof(dm644x_edma_pdata),
285 };
286
287 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
288 static struct resource dm644x_asp_resources[] = {
289 {
290 .name = "mpu",
291 .start = DAVINCI_ASP0_BASE,
292 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
293 .flags = IORESOURCE_MEM,
294 },
295 {
296 .start = DAVINCI_DMA_ASP0_TX,
297 .end = DAVINCI_DMA_ASP0_TX,
298 .flags = IORESOURCE_DMA,
299 },
300 {
301 .start = DAVINCI_DMA_ASP0_RX,
302 .end = DAVINCI_DMA_ASP0_RX,
303 .flags = IORESOURCE_DMA,
304 },
305 };
306
307 static struct platform_device dm644x_asp_device = {
308 .name = "davinci-mcbsp",
309 .id = -1,
310 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
311 .resource = dm644x_asp_resources,
312 };
313
314 #define DM644X_VPSS_BASE 0x01c73400
315
316 static struct resource dm644x_vpss_resources[] = {
317 {
318 /* VPSS Base address */
319 .name = "vpss",
320 .start = DM644X_VPSS_BASE,
321 .end = DM644X_VPSS_BASE + 0xff,
322 .flags = IORESOURCE_MEM,
323 },
324 };
325
326 static struct platform_device dm644x_vpss_device = {
327 .name = "vpss",
328 .id = -1,
329 .dev.platform_data = "dm644x_vpss",
330 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
331 .resource = dm644x_vpss_resources,
332 };
333
334 static struct resource dm644x_vpfe_resources[] = {
335 {
336 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
337 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
338 .flags = IORESOURCE_IRQ,
339 },
340 {
341 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
342 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
343 .flags = IORESOURCE_IRQ,
344 },
345 };
346
347 static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
348 static struct resource dm644x_ccdc_resource[] = {
349 /* CCDC Base address */
350 {
351 .start = 0x01c70400,
352 .end = 0x01c70400 + 0xff,
353 .flags = IORESOURCE_MEM,
354 },
355 };
356
357 static struct platform_device dm644x_ccdc_dev = {
358 .name = "dm644x_ccdc",
359 .id = -1,
360 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
361 .resource = dm644x_ccdc_resource,
362 .dev = {
363 .dma_mask = &dm644x_video_dma_mask,
364 .coherent_dma_mask = DMA_BIT_MASK(32),
365 },
366 };
367
368 static struct platform_device dm644x_vpfe_dev = {
369 .name = CAPTURE_DRV_NAME,
370 .id = -1,
371 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
372 .resource = dm644x_vpfe_resources,
373 .dev = {
374 .dma_mask = &dm644x_video_dma_mask,
375 .coherent_dma_mask = DMA_BIT_MASK(32),
376 },
377 };
378
379 #define DM644X_OSD_BASE 0x01c72600
380
381 static struct resource dm644x_osd_resources[] = {
382 {
383 .start = DM644X_OSD_BASE,
384 .end = DM644X_OSD_BASE + 0x1ff,
385 .flags = IORESOURCE_MEM,
386 },
387 };
388
389 static struct platform_device dm644x_osd_dev = {
390 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
391 .id = -1,
392 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
393 .resource = dm644x_osd_resources,
394 .dev = {
395 .dma_mask = &dm644x_video_dma_mask,
396 .coherent_dma_mask = DMA_BIT_MASK(32),
397 },
398 };
399
400 #define DM644X_VENC_BASE 0x01c72400
401
402 static struct resource dm644x_venc_resources[] = {
403 {
404 .start = DM644X_VENC_BASE,
405 .end = DM644X_VENC_BASE + 0x17f,
406 .flags = IORESOURCE_MEM,
407 },
408 };
409
410 #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
411 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
412 #define DM644X_VPSS_VENCLKEN BIT(3)
413 #define DM644X_VPSS_DACCLKEN BIT(4)
414
415 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
416 unsigned int pclock)
417 {
418 int ret = 0;
419 u32 v = DM644X_VPSS_VENCLKEN;
420
421 switch (type) {
422 case VPBE_ENC_STD:
423 v |= DM644X_VPSS_DACCLKEN;
424 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
425 break;
426 case VPBE_ENC_DV_TIMINGS:
427 if (pclock <= 27000000) {
428 v |= DM644X_VPSS_DACCLKEN;
429 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
430 } else {
431 /*
432 * For HD, use external clock source since
433 * HD requires higher clock rate
434 */
435 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
436 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
437 }
438 break;
439 default:
440 ret = -EINVAL;
441 }
442
443 return ret;
444 }
445
446 static struct resource dm644x_v4l2_disp_resources[] = {
447 {
448 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
449 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
450 .flags = IORESOURCE_IRQ,
451 },
452 };
453
454 static struct platform_device dm644x_vpbe_display = {
455 .name = "vpbe-v4l2",
456 .id = -1,
457 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
458 .resource = dm644x_v4l2_disp_resources,
459 .dev = {
460 .dma_mask = &dm644x_video_dma_mask,
461 .coherent_dma_mask = DMA_BIT_MASK(32),
462 },
463 };
464
465 static struct venc_platform_data dm644x_venc_pdata = {
466 .setup_clock = dm644x_venc_setup_clock,
467 };
468
469 static struct platform_device dm644x_venc_dev = {
470 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
471 .id = -1,
472 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
473 .resource = dm644x_venc_resources,
474 .dev = {
475 .dma_mask = &dm644x_video_dma_mask,
476 .coherent_dma_mask = DMA_BIT_MASK(32),
477 .platform_data = &dm644x_venc_pdata,
478 },
479 };
480
481 static struct platform_device dm644x_vpbe_dev = {
482 .name = "vpbe_controller",
483 .id = -1,
484 .dev = {
485 .dma_mask = &dm644x_video_dma_mask,
486 .coherent_dma_mask = DMA_BIT_MASK(32),
487 },
488 };
489
490 static struct resource dm644_gpio_resources[] = {
491 { /* registers */
492 .start = DAVINCI_GPIO_BASE,
493 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
494 .flags = IORESOURCE_MEM,
495 },
496 { /* interrupt */
497 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
498 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
499 .flags = IORESOURCE_IRQ,
500 },
501 {
502 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
503 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
504 .flags = IORESOURCE_IRQ,
505 },
506 {
507 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
508 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
509 .flags = IORESOURCE_IRQ,
510 },
511 {
512 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
513 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
514 .flags = IORESOURCE_IRQ,
515 },
516 {
517 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
518 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
519 .flags = IORESOURCE_IRQ,
520 },
521 };
522
523 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
524 .no_auto_base = true,
525 .base = 0,
526 .ngpio = 71,
527 };
528
529 int __init dm644x_gpio_register(void)
530 {
531 return davinci_gpio_register(dm644_gpio_resources,
532 ARRAY_SIZE(dm644_gpio_resources),
533 &dm644_gpio_platform_data);
534 }
535 /*----------------------------------------------------------------------*/
536
537 static struct map_desc dm644x_io_desc[] = {
538 {
539 .virtual = IO_VIRT,
540 .pfn = __phys_to_pfn(IO_PHYS),
541 .length = IO_SIZE,
542 .type = MT_DEVICE
543 },
544 };
545
546 /* Contents of JTAG ID register used to identify exact cpu type */
547 static struct davinci_id dm644x_ids[] = {
548 {
549 .variant = 0x0,
550 .part_no = 0xb700,
551 .manufacturer = 0x017,
552 .cpu_id = DAVINCI_CPU_ID_DM6446,
553 .name = "dm6446",
554 },
555 {
556 .variant = 0x1,
557 .part_no = 0xb700,
558 .manufacturer = 0x017,
559 .cpu_id = DAVINCI_CPU_ID_DM6446,
560 .name = "dm6446a",
561 },
562 };
563
564 /*
565 * Bottom half of timer0 is used for clockevent, top half is used for
566 * clocksource.
567 */
568 static const struct davinci_timer_cfg dm644x_timer_cfg = {
569 .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
570 .irq = {
571 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
572 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
573 },
574 };
575
576 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
577 {
578 .mapbase = DAVINCI_UART0_BASE,
579 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
580 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
581 UPF_IOREMAP,
582 .iotype = UPIO_MEM,
583 .regshift = 2,
584 },
585 {
586 .flags = 0,
587 }
588 };
589 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
590 {
591 .mapbase = DAVINCI_UART1_BASE,
592 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
593 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
594 UPF_IOREMAP,
595 .iotype = UPIO_MEM,
596 .regshift = 2,
597 },
598 {
599 .flags = 0,
600 }
601 };
602 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
603 {
604 .mapbase = DAVINCI_UART2_BASE,
605 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
606 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
607 UPF_IOREMAP,
608 .iotype = UPIO_MEM,
609 .regshift = 2,
610 },
611 {
612 .flags = 0,
613 }
614 };
615
616 struct platform_device dm644x_serial_device[] = {
617 {
618 .name = "serial8250",
619 .id = PLAT8250_DEV_PLATFORM,
620 .dev = {
621 .platform_data = dm644x_serial0_platform_data,
622 }
623 },
624 {
625 .name = "serial8250",
626 .id = PLAT8250_DEV_PLATFORM1,
627 .dev = {
628 .platform_data = dm644x_serial1_platform_data,
629 }
630 },
631 {
632 .name = "serial8250",
633 .id = PLAT8250_DEV_PLATFORM2,
634 .dev = {
635 .platform_data = dm644x_serial2_platform_data,
636 }
637 },
638 {
639 }
640 };
641
642 static const struct davinci_soc_info davinci_soc_info_dm644x = {
643 .io_desc = dm644x_io_desc,
644 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
645 .jtag_id_reg = 0x01c40028,
646 .ids = dm644x_ids,
647 .ids_num = ARRAY_SIZE(dm644x_ids),
648 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
649 .pinmux_pins = dm644x_pins,
650 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
651 .emac_pdata = &dm644x_emac_pdata,
652 .sram_dma = 0x00008000,
653 .sram_len = SZ_16K,
654 };
655
656 void __init dm644x_init_asp(void)
657 {
658 davinci_cfg_reg(DM644X_MCBSP);
659 platform_device_register(&dm644x_asp_device);
660 }
661
662 void __init dm644x_init(void)
663 {
664 davinci_common_init(&davinci_soc_info_dm644x);
665 davinci_map_sysmod();
666 }
667
668 void __init dm644x_init_time(void)
669 {
670 void __iomem *pll1, *psc;
671 struct clk *clk;
672 int rv;
673
674 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
675
676 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
677 dm644x_pll1_init(NULL, pll1, NULL);
678
679 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
680 dm644x_psc_init(NULL, psc);
681
682 clk = clk_get(NULL, "timer0");
683 if (WARN_ON(IS_ERR(clk))) {
684 pr_err("Unable to get the timer clock\n");
685 return;
686 }
687
688 rv = davinci_timer_register(clk, &dm644x_timer_cfg);
689 WARN(rv, "Unable to register the timer: %d\n", rv);
690 }
691
692 static struct resource dm644x_pll2_resources[] = {
693 {
694 .start = DAVINCI_PLL2_BASE,
695 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
696 .flags = IORESOURCE_MEM,
697 },
698 };
699
700 static struct platform_device dm644x_pll2_device = {
701 .name = "dm644x-pll2",
702 .id = -1,
703 .resource = dm644x_pll2_resources,
704 .num_resources = ARRAY_SIZE(dm644x_pll2_resources),
705 };
706
707 void __init dm644x_register_clocks(void)
708 {
709 /* PLL1 and PSC are registered in dm644x_init_time() */
710 platform_device_register(&dm644x_pll2_device);
711 }
712
713 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
714 struct vpbe_config *vpbe_cfg)
715 {
716 if (vpfe_cfg || vpbe_cfg)
717 platform_device_register(&dm644x_vpss_device);
718
719 if (vpfe_cfg) {
720 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
721 platform_device_register(&dm644x_ccdc_dev);
722 platform_device_register(&dm644x_vpfe_dev);
723 }
724
725 if (vpbe_cfg) {
726 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
727 platform_device_register(&dm644x_osd_dev);
728 platform_device_register(&dm644x_venc_dev);
729 platform_device_register(&dm644x_vpbe_dev);
730 platform_device_register(&dm644x_vpbe_display);
731 }
732
733 return 0;
734 }
735
736 static const struct davinci_aintc_config dm644x_aintc_config = {
737 .reg = {
738 .start = DAVINCI_ARM_INTC_BASE,
739 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
740 .flags = IORESOURCE_MEM,
741 },
742 .num_irqs = 64,
743 .prios = dm644x_default_priorities,
744 };
745
746 void __init dm644x_init_irq(void)
747 {
748 davinci_aintc_init(&dm644x_aintc_config);
749 }
750
751 void __init dm644x_init_devices(void)
752 {
753 struct platform_device *edma_pdev;
754 int ret;
755
756 edma_pdev = platform_device_register_full(&dm644x_edma_device);
757 if (IS_ERR(edma_pdev))
758 pr_warn("%s: Failed to register eDMA\n", __func__);
759
760 platform_device_register(&dm644x_mdio_device);
761 platform_device_register(&dm644x_emac_device);
762
763 ret = davinci_init_wdt();
764 if (ret)
765 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
766
767 }
Linux with added FPC-III support