arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/types.h>
  18
  19 #include "omap_hwmod.h"
  20 #include "cm33xx.h"
  21 #include "prm33xx.h"
  22 #include "omap_hwmod_33xx_43xx_common_data.h"
  23 #include "prcm43xx.h"
  24 #include "common.h"
  25
  26 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  27 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  28 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  29 #define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
  30
  31 /*
  32  * 'l3' class
  33  * instance(s): l3_main, l3_s, l3_instr
  34  */
  35 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  36         .name           = "l3",
  37 };
  38
  39 struct omap_hwmod am33xx_l3_main_hwmod = {
  40         .name           = "l3_main",
  41         .class          = &am33xx_l3_hwmod_class,
  42         .clkdm_name     = "l3_clkdm",
  43         .flags          = HWMOD_INIT_NO_IDLE,
  44         .main_clk       = "l3_gclk",
  45         .prcm           = {
  46                 .omap4  = {
  47                         .modulemode     = MODULEMODE_SWCTRL,
  48                 },
  49         },
  50 };
  51
  52 /* l3_s */
  53 struct omap_hwmod am33xx_l3_s_hwmod = {
  54         .name           = "l3_s",
  55         .class          = &am33xx_l3_hwmod_class,
  56         .clkdm_name     = "l3s_clkdm",
  57 };
  58
  59 /* l3_instr */
  60 struct omap_hwmod am33xx_l3_instr_hwmod = {
  61         .name           = "l3_instr",
  62         .class          = &am33xx_l3_hwmod_class,
  63         .clkdm_name     = "l3_clkdm",
  64         .flags          = HWMOD_INIT_NO_IDLE,
  65         .main_clk       = "l3_gclk",
  66         .prcm           = {
  67                 .omap4  = {
  68                         .modulemode     = MODULEMODE_SWCTRL,
  69                 },
  70         },
  71 };
  72
  73 /*
  74  * 'l4' class
  75  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  76  */
  77 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  78         .name           = "l4",
  79 };
  80
  81 /* l4_ls */
  82 struct omap_hwmod am33xx_l4_ls_hwmod = {
  83         .name           = "l4_ls",
  84         .class          = &am33xx_l4_hwmod_class,
  85         .clkdm_name     = "l4ls_clkdm",
  86         .flags          = HWMOD_INIT_NO_IDLE,
  87         .main_clk       = "l4ls_gclk",
  88         .prcm           = {
  89                 .omap4  = {
  90                         .modulemode     = MODULEMODE_SWCTRL,
  91                 },
  92         },
  93 };
  94
  95 /* l4_wkup */
  96 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  97         .name           = "l4_wkup",
  98         .class          = &am33xx_l4_hwmod_class,
  99         .clkdm_name     = "l4_wkup_clkdm",
 100         .flags          = HWMOD_INIT_NO_IDLE,
 101         .prcm           = {
 102                 .omap4  = {
 103                         .modulemode     = MODULEMODE_SWCTRL,
 104                 },
 105         },
 106 };
 107
 108 /*
 109  * 'mpu' class
 110  */
 111 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 112         .name   = "mpu",
 113 };
 114
 115 struct omap_hwmod am33xx_mpu_hwmod = {
 116         .name           = "mpu",
 117         .class          = &am33xx_mpu_hwmod_class,
 118         .clkdm_name     = "mpu_clkdm",
 119         .flags          = HWMOD_INIT_NO_IDLE,
 120         .main_clk       = "dpll_mpu_m2_ck",
 121         .prcm           = {
 122                 .omap4  = {
 123                         .modulemode     = MODULEMODE_SWCTRL,
 124                 },
 125         },
 126 };
 127
 128 /*
 129  * 'wakeup m3' class
 130  * Wakeup controller sub-system under wakeup domain
 131  */
 132 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 133         .name           = "wkup_m3",
 134 };
 135
 136 /* gfx */
 137 /* Pseudo hwmod for reset control purpose only */
 138 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 139         .name   = "gfx",
 140 };
 141
 142 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 143         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 144 };
 145
 146 struct omap_hwmod am33xx_gfx_hwmod = {
 147         .name           = "gfx",
 148         .class          = &am33xx_gfx_hwmod_class,
 149         .clkdm_name     = "gfx_l3_clkdm",
 150         .main_clk       = "gfx_fck_div_ck",
 151         .prcm           = {
 152                 .omap4  = {
 153                         .modulemode     = MODULEMODE_SWCTRL,
 154                 },
 155         },
 156         .rst_lines      = am33xx_gfx_resets,
 157         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 158 };
 159
 160 /*
 161  * 'prcm' class
 162  * power and reset manager (whole prcm infrastructure)
 163  */
 164 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 165         .name   = "prcm",
 166 };
 167
 168 /* prcm */
 169 struct omap_hwmod am33xx_prcm_hwmod = {
 170         .name           = "prcm",
 171         .class          = &am33xx_prcm_hwmod_class,
 172         .clkdm_name     = "l4_wkup_clkdm",
 173 };
 174
 175 /*
 176  * 'emif' class
 177  * instance(s): emif
 178  */
 179 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 180         .rev_offs       = 0x0000,
 181 };
 182
 183 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 184         .name           = "emif",
 185         .sysc           = &am33xx_emif_sysc,
 186 };
 187
 188
 189
 190 /* ocmcram */
 191 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 192         .name = "ocmcram",
 193 };
 194
 195 struct omap_hwmod am33xx_ocmcram_hwmod = {
 196         .name           = "ocmcram",
 197         .class          = &am33xx_ocmcram_hwmod_class,
 198         .clkdm_name     = "l3_clkdm",
 199         .flags          = HWMOD_INIT_NO_IDLE,
 200         .main_clk       = "l3_gclk",
 201         .prcm           = {
 202                 .omap4  = {
 203                         .modulemode     = MODULEMODE_SWCTRL,
 204                 },
 205         },
 206 };
 207
 208 /* 'smartreflex' class */
 209 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 210         .name           = "smartreflex",
 211 };
 212
 213 /* smartreflex0 */
 214 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 215         .name           = "smartreflex0",
 216         .class          = &am33xx_smartreflex_hwmod_class,
 217         .clkdm_name     = "l4_wkup_clkdm",
 218         .main_clk       = "smartreflex0_fck",
 219         .prcm           = {
 220                 .omap4  = {
 221                         .modulemode     = MODULEMODE_SWCTRL,
 222                 },
 223         },
 224 };
 225
 226 /* smartreflex1 */
 227 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 228         .name           = "smartreflex1",
 229         .class          = &am33xx_smartreflex_hwmod_class,
 230         .clkdm_name     = "l4_wkup_clkdm",
 231         .main_clk       = "smartreflex1_fck",
 232         .prcm           = {
 233                 .omap4  = {
 234                         .modulemode     = MODULEMODE_SWCTRL,
 235                 },
 236         },
 237 };
 238
 239 /*
 240  * 'control' module class
 241  */
 242 struct omap_hwmod_class am33xx_control_hwmod_class = {
 243         .name           = "control",
 244 };
 245
 246
 247 /* gpmc */
 248 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 249         .rev_offs       = 0x0,
 250         .sysc_offs      = 0x10,
 251         .syss_offs      = 0x14,
 252         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 253                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 254         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 255         .sysc_fields    = &omap_hwmod_sysc_type1,
 256 };
 257
 258 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 259         .name           = "gpmc",
 260         .sysc           = &gpmc_sysc,
 261 };
 262
 263 struct omap_hwmod am33xx_gpmc_hwmod = {
 264         .name           = "gpmc",
 265         .class          = &am33xx_gpmc_hwmod_class,
 266         .clkdm_name     = "l3s_clkdm",
 267         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 268         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 269         .main_clk       = "l3s_gclk",
 270         .prcm           = {
 271                 .omap4  = {
 272                         .modulemode     = MODULEMODE_SWCTRL,
 273                 },
 274         },
 275 };
 276
 277
 278 /*
 279  * 'rtc' class
 280  * rtc subsystem
 281  */
 282 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 283         .rev_offs       = 0x0074,
 284         .sysc_offs      = 0x0078,
 285         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 287                           SIDLE_SMART | SIDLE_SMART_WKUP),
 288         .sysc_fields    = &omap_hwmod_sysc_type3,
 289 };
 290
 291 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 292         .name           = "rtc",
 293         .sysc           = &am33xx_rtc_sysc,
 294         .unlock         = &omap_hwmod_rtc_unlock,
 295         .lock           = &omap_hwmod_rtc_lock,
 296 };
 297
 298 struct omap_hwmod am33xx_rtc_hwmod = {
 299         .name           = "rtc",
 300         .class          = &am33xx_rtc_hwmod_class,
 301         .clkdm_name     = "l4_rtc_clkdm",
 302         .main_clk       = "clk_32768_ck",
 303         .prcm           = {
 304                 .omap4  = {
 305                         .modulemode     = MODULEMODE_SWCTRL,
 306                 },
 307         },
 308 };
 309
 310 /* 'timer 2-7' class */
 311 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
 312         .rev_offs       = 0x0000,
 313         .sysc_offs      = 0x0010,
 314         .syss_offs      = 0x0014,
 315         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 316                           SYSC_HAS_RESET_STATUS,
 317         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 318                           SIDLE_SMART_WKUP),
 319         .sysc_fields    = &omap_hwmod_sysc_type2,
 320 };
 321
 322 struct omap_hwmod_class am33xx_timer_hwmod_class = {
 323         .name           = "timer",
 324         .sysc           = &am33xx_timer_sysc,
 325 };
 326
 327 /* timer1 1ms */
 328 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
 329         .rev_offs       = 0x0000,
 330         .sysc_offs      = 0x0010,
 331         .syss_offs      = 0x0014,
 332         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 333                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 334                         SYSS_HAS_RESET_STATUS),
 335         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 336         .sysc_fields    = &omap_hwmod_sysc_type1,
 337 };
 338
 339 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
 340         .name           = "timer",
 341         .sysc           = &am33xx_timer1ms_sysc,
 342 };
 343
 344 struct omap_hwmod am33xx_timer1_hwmod = {
 345         .name           = "timer1",
 346         .class          = &am33xx_timer1ms_hwmod_class,
 347         .clkdm_name     = "l4_wkup_clkdm",
 348         .main_clk       = "timer1_fck",
 349         .prcm           = {
 350                 .omap4  = {
 351                         .modulemode     = MODULEMODE_SWCTRL,
 352                 },
 353         },
 354 };
 355
 356 struct omap_hwmod am33xx_timer2_hwmod = {
 357         .name           = "timer2",
 358         .class          = &am33xx_timer_hwmod_class,
 359         .clkdm_name     = "l4ls_clkdm",
 360         .main_clk       = "timer2_fck",
 361         .prcm           = {
 362                 .omap4  = {
 363                         .modulemode     = MODULEMODE_SWCTRL,
 364                 },
 365         },
 366 };
 367
 368 static void omap_hwmod_am33xx_clkctrl(void)
 369 {
 370         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
 371         CLKCTRL(am33xx_smartreflex0_hwmod,
 372                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
 373         CLKCTRL(am33xx_smartreflex1_hwmod,
 374                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
 375         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
 376         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
 377         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
 378         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 379         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
 380         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
 381         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
 382         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
 383         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
 384         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
 385         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
 386 }
 387
 388 static void omap_hwmod_am33xx_rst(void)
 389 {
 390         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
 391         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
 392 }
 393
 394 void omap_hwmod_am33xx_reg(void)
 395 {
 396         omap_hwmod_am33xx_clkctrl();
 397         omap_hwmod_am33xx_rst();
 398 }
 399
 400 static void omap_hwmod_am43xx_clkctrl(void)
 401 {
 402         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
 403         CLKCTRL(am33xx_smartreflex0_hwmod,
 404                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
 405         CLKCTRL(am33xx_smartreflex1_hwmod,
 406                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
 407         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
 408         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
 409         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
 410         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
 411         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
 412         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
 413         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
 414         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
 415         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
 416         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
 417 }
 418
 419 static void omap_hwmod_am43xx_rst(void)
 420 {
 421         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
 422         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
 423 }
 424
 425 void omap_hwmod_am43xx_reg(void)
 426 {
 427         omap_hwmod_am43xx_clkctrl();
 428         omap_hwmod_am43xx_rst();
 429 }