| blob | e7bcf7dc46755ef9061669149b84241cf394de52 |
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 */
6 #include <linux/linkage.h>
8 #include <soc/tegra/flowctrl.h>
9 #include <soc/tegra/fuse.h>
11 #include <asm/asm-offsets.h>
12 #include <asm/assembler.h>
13 #include <asm/cache.h>
15 #include "irammap.h"
16 #include "sleep.h"
18 #define EMC_CFG 0xc
19 #define EMC_ADR_CFG 0x10
20 #define EMC_TIMING_CONTROL 0x28
21 #define EMC_NOP 0xdc
22 #define EMC_SELF_REF 0xe0
23 #define EMC_MRW 0xe8
24 #define EMC_FBIO_CFG5 0x104
25 #define EMC_AUTO_CAL_CONFIG 0x2a4
26 #define EMC_AUTO_CAL_INTERVAL 0x2a8
27 #define EMC_AUTO_CAL_STATUS 0x2ac
28 #define EMC_REQ_CTRL 0x2b0
29 #define EMC_CFG_DIG_DLL 0x2bc
30 #define EMC_EMC_STATUS 0x2b4
31 #define EMC_ZCAL_INTERVAL 0x2e0
32 #define EMC_ZQ_CAL 0x2ec
33 #define EMC_XM2VTTGENPADCTRL 0x310
34 #define EMC_XM2VTTGENPADCTRL2 0x314
36 #define PMC_CTRL 0x0
37 #define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
39 #define PMC_PLLP_WB0_OVERRIDE 0xf8
40 #define PMC_IO_DPD_REQ 0x1b8
41 #define PMC_IO_DPD_STATUS 0x1bc
43 #define CLK_RESET_CCLK_BURST 0x20
44 #define CLK_RESET_CCLK_DIVIDER 0x24
45 #define CLK_RESET_SCLK_BURST 0x28
46 #define CLK_RESET_SCLK_DIVIDER 0x2c
48 #define CLK_RESET_PLLC_BASE 0x80
49 #define CLK_RESET_PLLC_MISC 0x8c
50 #define CLK_RESET_PLLM_BASE 0x90
51 #define CLK_RESET_PLLM_MISC 0x9c
52 #define CLK_RESET_PLLP_BASE 0xa0
53 #define CLK_RESET_PLLP_MISC 0xac
54 #define CLK_RESET_PLLA_BASE 0xb0
55 #define CLK_RESET_PLLA_MISC 0xbc
56 #define CLK_RESET_PLLX_BASE 0xe0
57 #define CLK_RESET_PLLX_MISC 0xe4
58 #define CLK_RESET_PLLX_MISC3 0x518
59 #define CLK_RESET_PLLX_MISC3_IDDQ 3
60 #define CLK_RESET_PLLM_MISC_IDDQ 5
61 #define CLK_RESET_PLLC_MISC_IDDQ 26
62 #define CLK_RESET_PLLP_RESHIFT 0x528
63 #define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
64 #define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3
66 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
68 #define MSELECT_CLKM (0x3 << 30)
70 #define LOCK_DELAY 50 /* safety delay after lock is detected */
72 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
74 .macro emc_device_mask, rd, base
75 ldr \rd, [\base, #EMC_ADR_CFG]
76 tst \rd, #0x1
77 moveq \rd, #(0x1 << 8) @ just 1 device
78 movne \rd, #(0x3 << 8) @ 2 devices
79 .endm
81 .macro emc_timing_update, rd, base
82 mov \rd, #1
83 str \rd, [\base, #EMC_TIMING_CONTROL]
84 1001:
85 ldr \rd, [\base, #EMC_EMC_STATUS]
86 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
87 bne 1001b
88 .endm
90 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
91 ldr \rd, [\r_car_base, #\pll_base]
92 tst \rd, #(1 << 30)
93 orreq \rd, \rd, #(1 << 30)
94 streq \rd, [\r_car_base, #\pll_base]
95 /* Enable lock detector */
96 .if \pll_misc
97 ldr \rd, [\r_car_base, #\pll_misc]
98 bic \rd, \rd, #(1 << 18)
99 str \rd, [\r_car_base, #\pll_misc]
100 ldr \rd, [\r_car_base, #\pll_misc]
101 ldr \rd, [\r_car_base, #\pll_misc]
102 orr \rd, \rd, #(1 << 18)
103 str \rd, [\r_car_base, #\pll_misc]
104 .endif
105 .endm
107 .macro pll_locked, rd, r_car_base, pll_base
108 1:
109 ldr \rd, [\r_car_base, #\pll_base]
110 tst \rd, #(1 << 27)
111 beq 1b
112 .endm
114 .macro pll_iddq_exit, rd, car, iddq, iddq_bit
115 ldr \rd, [\car, #\iddq]
116 bic \rd, \rd, #(1<<\iddq_bit)
117 str \rd, [\car, #\iddq]
118 .endm
120 .macro pll_iddq_entry, rd, car, iddq, iddq_bit
121 ldr \rd, [\car, #\iddq]
122 orr \rd, \rd, #(1<<\iddq_bit)
123 str \rd, [\car, #\iddq]
124 .endm
126 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
127 /*
128 * tegra30_hotplug_shutdown(void)
129 *
130 * Powergates the current CPU.
131 * Should never return.
132 */
133 ENTRY(tegra30_hotplug_shutdown)
134 /* Powergate this CPU */
135 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
136 bl tegra30_cpu_shutdown
137 ret lr @ should never get here
138 ENDPROC(tegra30_hotplug_shutdown)
140 /*
141 * tegra30_cpu_shutdown(unsigned long flags)
142 *
143 * Puts the current CPU in wait-for-event mode on the flow controller
144 * and powergates it -- flags (in R0) indicate the request type.
145 *
146 * r10 = SoC ID
147 * corrupts r0-r4, r10-r12
148 */
149 ENTRY(tegra30_cpu_shutdown)
150 cpu_id r3
151 tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
152 cmp r10, #TEGRA30
153 bne _no_cpu0_chk @ It's not Tegra30
155 cmp r3, #0
156 reteq lr @ Must never be called for CPU 0
157 _no_cpu0_chk:
159 ldr r12, =TEGRA_FLOW_CTRL_VIRT
160 cpu_to_csr_reg r1, r3
161 add r1, r1, r12 @ virtual CSR address for this CPU
162 cpu_to_halt_reg r2, r3
163 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
165 /*
166 * Clear this CPU's "event" and "interrupt" flags and power gate
167 * it when halting but not before it is in the "WFE" state.
168 */
169 movw r12, \
170 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
171 FLOW_CTRL_CSR_ENABLE
172 cmp r10, #TEGRA30
173 moveq r4, #(1 << 4) @ wfe bitmap
174 movne r4, #(1 << 8) @ wfi bitmap
175 ARM( orr r12, r12, r4, lsl r3 )
176 THUMB( lsl r4, r4, r3 )
177 THUMB( orr r12, r12, r4 )
178 str r12, [r1]
180 /* Halt this CPU. */
181 mov r3, #0x400
182 delay_1:
183 subs r3, r3, #1 @ delay as a part of wfe war.
184 bge delay_1;
185 cpsid a @ disable imprecise aborts.
186 ldr r3, [r1] @ read CSR
187 str r3, [r1] @ clear CSR
189 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
190 beq flow_ctrl_setting_for_lp2
192 /* flow controller set up for hotplug */
193 mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
194 b flow_ctrl_done
195 flow_ctrl_setting_for_lp2:
196 /* flow controller set up for LP2 */
197 cmp r10, #TEGRA30
198 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
199 movne r3, #FLOW_CTRL_WAITEVENT
200 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
201 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
202 flow_ctrl_done:
203 cmp r10, #TEGRA30
204 str r3, [r2]
205 ldr r0, [r2]
206 b wfe_war
208 __cpu_reset_again:
209 dsb
210 .align 5
211 wfeeq @ CPU should be power gated here
212 wfine
213 wfe_war:
214 b __cpu_reset_again
216 /*
217 * 38 nop's, which fills rest of wfe cache line and
218 * 4 more cachelines with nop
219 */
220 .rept 38
221 nop
222 .endr
223 b . @ should never get here
225 ENDPROC(tegra30_cpu_shutdown)
226 #endif
228 #ifdef CONFIG_PM_SLEEP
229 /*
230 * tegra30_sleep_core_finish(unsigned long v2p)
231 *
232 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
233 * tegra30_tear_down_core in IRAM
234 */
235 ENTRY(tegra30_sleep_core_finish)
236 mov r4, r0
237 /* Flush, disable the L1 data cache and exit SMP */
238 mov r0, #TEGRA_FLUSH_CACHE_ALL
239 bl tegra_disable_clean_inv_dcache
240 mov r0, r4
242 /*
243 * Preload all the address literals that are needed for the
244 * CPU power-gating process, to avoid loading from SDRAM which
245 * are not supported once SDRAM is put into self-refresh.
246 * LP0 / LP1 use physical address, since the MMU needs to be
247 * disabled before putting SDRAM into self-refresh to avoid
248 * memory access due to page table walks.
249 */
250 mov32 r4, TEGRA_PMC_BASE
251 mov32 r5, TEGRA_CLK_RESET_BASE
252 mov32 r6, TEGRA_FLOW_CTRL_BASE
253 mov32 r7, TEGRA_TMRUS_BASE
255 mov32 r3, tegra_shut_off_mmu
256 add r3, r3, r0
258 mov32 r0, tegra30_tear_down_core
259 mov32 r1, tegra30_iram_start
260 sub r0, r0, r1
261 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
262 add r0, r0, r1
264 ret r3
265 ENDPROC(tegra30_sleep_core_finish)
267 /*
268 * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg)
269 *
270 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
271 */
272 ENTRY(tegra30_pm_secondary_cpu_suspend)
273 mov r7, lr
275 /* Flush and disable the L1 data cache */
276 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
277 bl tegra_disable_clean_inv_dcache
279 /* Powergate this CPU. */
280 mov r0, #0 @ power mode flags (!hotplug)
281 bl tegra30_cpu_shutdown
282 mov r0, #1 @ never return here
283 ret r7
284 ENDPROC(tegra30_pm_secondary_cpu_suspend)
286 /*
287 * tegra30_tear_down_cpu
288 *
289 * Switches the CPU to enter sleep.
290 */
291 ENTRY(tegra30_tear_down_cpu)
292 mov32 r6, TEGRA_FLOW_CTRL_BASE
294 b tegra30_enter_sleep
295 ENDPROC(tegra30_tear_down_cpu)
297 /* START OF ROUTINES COPIED TO IRAM */
298 .align L1_CACHE_SHIFT
299 .globl tegra30_iram_start
300 tegra30_iram_start:
302 /*
303 * tegra30_lp1_reset
304 *
305 * reset vector for LP1 restore; copied into IRAM during suspend.
306 * Brings the system back up to a safe staring point (SDRAM out of
307 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
308 * system clock running on the same PLL that it suspended at), and
309 * jumps to tegra_resume to restore virtual addressing.
310 * The physical address of tegra_resume expected to be stored in
311 * PMC_SCRATCH41.
312 *
313 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
314 */
315 ENTRY(tegra30_lp1_reset)
316 /*
317 * The CPU and system bus are running at 32KHz and executing from
318 * IRAM when this code is executed; immediately switch to CLKM and
319 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
320 */
321 mov32 r0, TEGRA_CLK_RESET_BASE
323 mov r1, #(1 << 28)
324 str r1, [r0, #CLK_RESET_SCLK_BURST]
325 str r1, [r0, #CLK_RESET_CCLK_BURST]
326 mov r1, #0
327 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
328 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
330 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
331 cmp r10, #TEGRA30
332 beq _no_pll_iddq_exit
334 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
335 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
336 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
338 mov32 r7, TEGRA_TMRUS_BASE
339 ldr r1, [r7]
340 add r1, r1, #2
341 wait_until r1, r7, r3
343 /* enable PLLM via PMC */
344 mov32 r2, TEGRA_PMC_BASE
345 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
346 orr r1, r1, #(1 << 12)
347 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
349 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
350 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
351 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
353 b _pll_m_c_x_done
355 _no_pll_iddq_exit:
356 /* enable PLLM via PMC */
357 mov32 r2, TEGRA_PMC_BASE
358 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
359 orr r1, r1, #(1 << 12)
360 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
362 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
363 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
364 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
366 _pll_m_c_x_done:
367 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
368 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
370 pll_locked r1, r0, CLK_RESET_PLLM_BASE
371 pll_locked r1, r0, CLK_RESET_PLLP_BASE
372 pll_locked r1, r0, CLK_RESET_PLLA_BASE
373 pll_locked r1, r0, CLK_RESET_PLLC_BASE
374 pll_locked r1, r0, CLK_RESET_PLLX_BASE
376 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
377 cmp r1, #TEGRA30
378 beq 1f
380 ldr r1, [r0, #CLK_RESET_PLLP_BASE]
381 bic r1, r1, #(1<<31) @ disable PllP bypass
382 str r1, [r0, #CLK_RESET_PLLP_BASE]
384 mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
385 str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
386 1:
388 mov32 r7, TEGRA_TMRUS_BASE
389 ldr r1, [r7]
390 add r1, r1, #LOCK_DELAY
391 wait_until r1, r7, r3
393 adr r5, tegra_sdram_pad_save
395 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
396 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
398 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
399 str r4, [r0, #CLK_RESET_SCLK_BURST]
401 cmp r10, #TEGRA30
402 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
403 movteq r4, #:upper16:((1 << 28) | (0x8))
404 movwne r4, #:lower16:((1 << 28) | (0xe))
405 movtne r4, #:upper16:((1 << 28) | (0xe))
406 str r4, [r0, #CLK_RESET_CCLK_BURST]
408 /* Restore pad power state to normal */
409 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
410 mvn r1, r1
411 bic r1, r1, #(1 << 31)
412 orr r1, r1, #(1 << 30)
413 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
415 cmp r10, #TEGRA30
416 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
417 movteq r0, #:upper16:TEGRA_EMC_BASE
418 cmp r10, #TEGRA114
419 movweq r0, #:lower16:TEGRA_EMC0_BASE
420 movteq r0, #:upper16:TEGRA_EMC0_BASE
421 cmp r10, #TEGRA124
422 movweq r0, #:lower16:TEGRA124_EMC_BASE
423 movteq r0, #:upper16:TEGRA124_EMC_BASE
425 exit_self_refresh:
426 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
427 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
428 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
429 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
430 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
431 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
433 /* Relock DLL */
434 ldr r1, [r0, #EMC_CFG_DIG_DLL]
435 orr r1, r1, #(1 << 30) @ set DLL_RESET
436 str r1, [r0, #EMC_CFG_DIG_DLL]
438 emc_timing_update r1, r0
440 cmp r10, #TEGRA114
441 movweq r1, #:lower16:TEGRA_EMC1_BASE
442 movteq r1, #:upper16:TEGRA_EMC1_BASE
443 cmpeq r0, r1
445 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
446 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
447 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
448 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
450 emc_wait_auto_cal_onetime:
451 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
452 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
453 bne emc_wait_auto_cal_onetime
455 ldr r1, [r0, #EMC_CFG]
456 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
457 str r1, [r0, #EMC_CFG]
459 mov r1, #0
460 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
461 mov r1, #1
462 cmp r10, #TEGRA30
463 streq r1, [r0, #EMC_NOP]
464 streq r1, [r0, #EMC_NOP]
466 emc_device_mask r1, r0
468 exit_selfrefresh_loop:
469 ldr r2, [r0, #EMC_EMC_STATUS]
470 ands r2, r2, r1
471 bne exit_selfrefresh_loop
473 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
475 mov32 r7, TEGRA_TMRUS_BASE
476 ldr r2, [r0, #EMC_FBIO_CFG5]
478 and r2, r2, #3 @ check DRAM_TYPE
479 cmp r2, #2
480 beq emc_lpddr2
482 /* Issue a ZQ_CAL for dev0 - DDR3 */
483 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
484 str r2, [r0, #EMC_ZQ_CAL]
485 ldr r2, [r7]
486 add r2, r2, #10
487 wait_until r2, r7, r3
489 tst r1, #2
490 beq zcal_done
492 /* Issue a ZQ_CAL for dev1 - DDR3 */
493 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
494 str r2, [r0, #EMC_ZQ_CAL]
495 ldr r2, [r7]
496 add r2, r2, #10
497 wait_until r2, r7, r3
498 b zcal_done
500 emc_lpddr2:
501 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
502 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
503 str r2, [r0, #EMC_MRW]
504 ldr r2, [r7]
505 add r2, r2, #1
506 wait_until r2, r7, r3
508 tst r1, #2
509 beq zcal_done
511 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
512 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
513 str r2, [r0, #EMC_MRW]
514 ldr r2, [r7]
515 add r2, r2, #1
516 wait_until r2, r7, r3
518 zcal_done:
519 mov r1, #0 @ unstall all transactions
520 str r1, [r0, #EMC_REQ_CTRL]
521 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
522 str r1, [r0, #EMC_ZCAL_INTERVAL]
523 ldr r1, [r5, #0x0] @ restore EMC_CFG
524 str r1, [r0, #EMC_CFG]
526 emc_timing_update r1, r0
528 /* Tegra114 had dual EMC channel, now config the other one */
529 cmp r10, #TEGRA114
530 bne __no_dual_emc_chanl
531 mov32 r1, TEGRA_EMC1_BASE
532 cmp r0, r1
533 movne r0, r1
534 addne r5, r5, #0x20
535 bne exit_self_refresh
536 __no_dual_emc_chanl:
538 mov32 r0, TEGRA_PMC_BASE
539 ldr r0, [r0, #PMC_SCRATCH41]
540 ret r0 @ jump to tegra_resume
541 ENDPROC(tegra30_lp1_reset)
543 .align L1_CACHE_SHIFT
544 tegra30_sdram_pad_address:
545 .word TEGRA_EMC_BASE + EMC_CFG @0x0
546 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
547 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
548 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
549 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
550 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
551 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
552 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
553 tegra30_sdram_pad_address_end:
555 tegra114_sdram_pad_address:
556 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
557 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
558 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
559 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
560 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
561 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
562 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
563 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
564 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
565 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
566 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
567 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
568 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
569 tegra114_sdram_pad_adress_end:
571 tegra124_sdram_pad_address:
572 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
573 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
574 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
575 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
576 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
577 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
578 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
579 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
580 tegra124_sdram_pad_address_end:
582 tegra30_sdram_pad_size:
583 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
585 tegra114_sdram_pad_size:
586 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
588 .type tegra_sdram_pad_save, %object
589 tegra_sdram_pad_save:
590 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
591 .long 0
592 .endr
594 /*
595 * tegra30_tear_down_core
596 *
597 * copied into and executed from IRAM
598 * puts memory in self-refresh for LP0 and LP1
599 */
600 tegra30_tear_down_core:
601 bl tegra30_sdram_self_refresh
602 bl tegra30_switch_cpu_to_clk32k
603 b tegra30_enter_sleep
605 /*
606 * tegra30_switch_cpu_to_clk32k
607 *
608 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
609 * to the 32KHz clock.
610 * r4 = TEGRA_PMC_BASE
611 * r5 = TEGRA_CLK_RESET_BASE
612 * r6 = TEGRA_FLOW_CTRL_BASE
613 * r7 = TEGRA_TMRUS_BASE
614 * r10= SoC ID
615 */
616 tegra30_switch_cpu_to_clk32k:
617 /*
618 * start by jumping to CLKM to safely disable PLLs, then jump to
619 * CLKS.
620 */
621 mov r0, #(1 << 28)
622 str r0, [r5, #CLK_RESET_SCLK_BURST]
623 /* 2uS delay delay between changing SCLK and CCLK */
624 ldr r1, [r7]
625 add r1, r1, #2
626 wait_until r1, r7, r9
627 str r0, [r5, #CLK_RESET_CCLK_BURST]
628 mov r0, #0
629 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
630 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
632 /* switch the clock source of mselect to be CLK_M */
633 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
634 orr r0, r0, #MSELECT_CLKM
635 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
637 /* 2uS delay delay between changing SCLK and disabling PLLs */
638 ldr r1, [r7]
639 add r1, r1, #2
640 wait_until r1, r7, r9
642 /* disable PLLM via PMC in LP1 */
643 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
644 bic r0, r0, #(1 << 12)
645 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
647 /* disable PLLP, PLLA, PLLC and PLLX */
648 tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
649 cmp r1, #TEGRA30
650 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
651 orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
652 bic r0, r0, #(1 << 30)
653 str r0, [r5, #CLK_RESET_PLLP_BASE]
654 beq 1f
655 mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
656 str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
657 1:
658 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
659 bic r0, r0, #(1 << 30)
660 str r0, [r5, #CLK_RESET_PLLA_BASE]
661 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
662 bic r0, r0, #(1 << 30)
663 str r0, [r5, #CLK_RESET_PLLC_BASE]
664 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
665 bic r0, r0, #(1 << 30)
666 str r0, [r5, #CLK_RESET_PLLX_BASE]
668 cmp r10, #TEGRA30
669 beq _no_pll_in_iddq
670 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
671 _no_pll_in_iddq:
673 /*
674 * Switch to clk_s (32KHz); bits 28:31=0
675 * Enable burst on CPU IRQ; bit 24=1
676 * Set IRQ burst clock source to clk_m; bits 10:8=0
677 */
678 mov r0, #(1 << 24)
679 str r0, [r5, #CLK_RESET_SCLK_BURST]
681 ret lr
683 /*
684 * tegra30_enter_sleep
685 *
686 * uses flow controller to enter sleep state
687 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
688 * executes from SDRAM with target state is LP2
689 * r6 = TEGRA_FLOW_CTRL_BASE
690 */
691 tegra30_enter_sleep:
692 cpu_id r1
694 cpu_to_csr_reg r2, r1
695 ldr r0, [r6, r2]
696 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
697 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
698 str r0, [r6, r2]
700 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
701 cmp r10, #TEGRA30
702 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
703 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
704 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
706 cpu_to_halt_reg r2, r1
707 str r0, [r6, r2]
708 dsb
709 ldr r0, [r6, r2] /* memory barrier */
711 cmp r10, #TEGRA30
712 halted:
713 isb
714 dsb
715 wfine /* CPU should be power gated here */
716 wfeeq
718 /* !!!FIXME!!! Implement halt failure handler */
719 b halted
721 /*
722 * tegra30_sdram_self_refresh
723 *
724 * called with MMU off and caches disabled
725 * must be executed from IRAM
726 * r4 = TEGRA_PMC_BASE
727 * r5 = TEGRA_CLK_RESET_BASE
728 * r6 = TEGRA_FLOW_CTRL_BASE
729 * r7 = TEGRA_TMRUS_BASE
730 * r10= SoC ID
731 */
732 tegra30_sdram_self_refresh:
734 adr r8, tegra_sdram_pad_save
735 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
736 cmp r10, #TEGRA30
737 adreq r2, tegra30_sdram_pad_address
738 ldreq r3, tegra30_sdram_pad_size
739 cmp r10, #TEGRA114
740 adreq r2, tegra114_sdram_pad_address
741 ldreq r3, tegra114_sdram_pad_size
742 cmp r10, #TEGRA124
743 adreq r2, tegra124_sdram_pad_address
744 ldreq r3, tegra30_sdram_pad_size
746 mov r9, #0
748 padsave:
749 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
751 ldr r1, [r0]
752 str r1, [r8, r9] @ save the content of the addr
754 add r9, r9, #4
755 cmp r3, r9
756 bne padsave
757 padsave_done:
759 dsb
761 cmp r10, #TEGRA30
762 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
763 cmp r10, #TEGRA114
764 ldreq r0, =TEGRA_EMC0_BASE
765 cmp r10, #TEGRA124
766 ldreq r0, =TEGRA124_EMC_BASE
768 enter_self_refresh:
769 cmp r10, #TEGRA30
770 mov r1, #0
771 str r1, [r0, #EMC_ZCAL_INTERVAL]
772 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
773 ldr r1, [r0, #EMC_CFG]
774 bic r1, r1, #(1 << 28)
775 bicne r1, r1, #(1 << 29)
776 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
778 emc_timing_update r1, r0
780 ldr r1, [r7]
781 add r1, r1, #5
782 wait_until r1, r7, r2
784 emc_wait_auto_cal:
785 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
786 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
787 bne emc_wait_auto_cal
789 mov r1, #3
790 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
792 emcidle:
793 ldr r1, [r0, #EMC_EMC_STATUS]
794 tst r1, #4
795 beq emcidle
797 mov r1, #1
798 str r1, [r0, #EMC_SELF_REF]
800 emc_device_mask r1, r0
802 emcself:
803 ldr r2, [r0, #EMC_EMC_STATUS]
804 and r2, r2, r1
805 cmp r2, r1
806 bne emcself @ loop until DDR in self-refresh
808 /* Put VTTGEN in the lowest power mode */
809 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
810 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
811 and r1, r1, r2
812 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
813 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
814 cmp r10, #TEGRA30
815 orreq r1, r1, #7 @ set E_NO_VTTGEN
816 orrne r1, r1, #0x3f
817 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
819 emc_timing_update r1, r0
821 /* Tegra114 had dual EMC channel, now config the other one */
822 cmp r10, #TEGRA114
823 bne no_dual_emc_chanl
824 mov32 r1, TEGRA_EMC1_BASE
825 cmp r0, r1
826 movne r0, r1
827 bne enter_self_refresh
828 no_dual_emc_chanl:
830 ldr r1, [r4, #PMC_CTRL]
831 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
832 bne pmc_io_dpd_skip
833 /*
834 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
835 * and COMP in the lowest power mode when LP1.
836 */
837 mov32 r1, 0x8EC00000
838 str r1, [r4, #PMC_IO_DPD_REQ]
839 pmc_io_dpd_skip:
841 dsb
843 ret lr
845 .ltorg
846 /* dummy symbol for end of IRAM */
847 .align L1_CACHE_SHIFT
848 .global tegra30_iram_end
849 tegra30_iram_end:
850 b .
851 #endif