1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * xchg/cmpxchg operations for the Hexagon architecture
5 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
12 * __xchg - atomically exchange a register and a memory location
14 * @ptr: pointer to memory
15 * @size: size of the value
17 * Only 4 bytes supported currently.
19 * Note: there was an errata for V2 about .new's and memw_locked.
22 static inline unsigned long __xchg(unsigned long x
, volatile void *ptr
,
27 /* Can't seem to use printk or panic here, so just stop */
28 if (size
!= 4) do { asm volatile("brkpt;\n"); } while (1);
30 __asm__
__volatile__ (
31 "1: %0 = memw_locked(%1);\n" /* load into retval */
32 " memw_locked(%1,P0) = %2;\n" /* store into memory */
33 " if (!P0) jump 1b;\n"
42 * Atomically swap the contents of a register with memory. Should be atomic
43 * between multiple CPU's and within interrupts on the same CPU.
45 #define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
49 * see rt-mutex-design.txt; cmpxchg supposedly checks if *ptr == A and swaps.
50 * looks just like atomic_cmpxchg on our arch currently with a bunch of
54 #define cmpxchg(ptr, old, new) \
56 __typeof__(ptr) __ptr = (ptr); \
57 __typeof__(*(ptr)) __old = (old); \
58 __typeof__(*(ptr)) __new = (new); \
59 __typeof__(*(ptr)) __oldval = 0; \
62 "1: %0 = memw_locked(%1);\n" \
63 " { P0 = cmp.eq(%0,%2);\n" \
64 " if (!P0.new) jump:nt 2f; }\n" \
65 " memw_locked(%1,p0) = %3;\n" \
66 " if (!P0) jump 1b;\n" \
69 : "r" (__ptr), "r" (__old), "r" (__new) \
75 #endif /* _ASM_CMPXCHG_H */