2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2007 MIPS Technologies, Inc.
7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
9 #include <linux/clockchips.h>
10 #include <linux/interrupt.h>
11 #include <linux/percpu.h>
12 #include <linux/smp.h>
13 #include <linux/irq.h>
16 #include <asm/cevt-r4k.h>
18 static int mips_next_event(unsigned long delta
,
19 struct clock_event_device
*evt
)
24 cnt
= read_c0_count();
26 write_c0_compare(cnt
);
27 res
= ((int)(read_c0_count() - cnt
) >= 0) ? -ETIME
: 0;
32 * calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
34 * Running under virtualisation can introduce overhead into mips_next_event() in
35 * the form of hypervisor emulation of CP0_Count/CP0_Compare registers,
36 * potentially with an unnatural frequency, which makes a fixed min_delta_ns
37 * value inappropriate as it may be too small.
39 * It can also introduce occasional latency from the guest being descheduled.
41 * This function calculates a good minimum delta based roughly on the 75th
42 * percentile of the time taken to do the mips_next_event() sequence, in order
43 * to handle potentially higher overhead while also eliminating outliers due to
44 * unpredictable hypervisor latency (which can be handled by retries).
46 * Return: An appropriate minimum delta for the clock event device.
48 static unsigned int calculate_min_delta(void)
50 unsigned int cnt
, i
, j
, k
, l
;
51 unsigned int buf1
[4], buf2
[3];
52 unsigned int min_delta
;
55 * Calculate the median of 5 75th percentiles of 5 samples of how long
56 * it takes to set CP0_Compare = CP0_Count + delta.
58 for (i
= 0; i
< 5; ++i
) {
59 for (j
= 0; j
< 5; ++j
) {
61 * This is like the code in mips_next_event(), and
62 * directly measures the borderline "safe" delta.
64 cnt
= read_c0_count();
65 write_c0_compare(cnt
);
66 cnt
= read_c0_count() - cnt
;
68 /* Sorted insert into buf1 */
69 for (k
= 0; k
< j
; ++k
) {
71 l
= min_t(unsigned int,
72 j
, ARRAY_SIZE(buf1
) - 1);
74 buf1
[l
] = buf1
[l
- 1];
78 if (k
< ARRAY_SIZE(buf1
))
82 /* Sorted insert of 75th percentile into buf2 */
83 for (k
= 0; k
< i
&& k
< ARRAY_SIZE(buf2
); ++k
) {
84 if (buf1
[ARRAY_SIZE(buf1
) - 1] < buf2
[k
]) {
85 l
= min_t(unsigned int,
86 i
, ARRAY_SIZE(buf2
) - 1);
88 buf2
[l
] = buf2
[l
- 1];
92 if (k
< ARRAY_SIZE(buf2
))
93 buf2
[k
] = buf1
[ARRAY_SIZE(buf1
) - 1];
96 /* Use 2 * median of 75th percentiles */
97 min_delta
= buf2
[ARRAY_SIZE(buf2
) - 1] * 2;
99 /* Don't go too low */
100 if (min_delta
< 0x300)
103 pr_debug("%s: median 75th percentile=%#x, min_delta=%#x\n",
104 __func__
, buf2
[ARRAY_SIZE(buf2
) - 1], min_delta
);
108 DEFINE_PER_CPU(struct clock_event_device
, mips_clockevent_device
);
109 int cp0_timer_irq_installed
;
112 * Possibly handle a performance counter interrupt.
113 * Return true if the timer interrupt should not be checked
115 static inline int handle_perf_irq(int r2
)
118 * The performance counter overflow interrupt may be shared with the
119 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
120 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
121 * and we can't reliably determine if a counter interrupt has also
122 * happened (!r2) then don't check for a timer interrupt.
124 return (cp0_perfcount_irq
< 0) &&
125 perf_irq() == IRQ_HANDLED
&&
129 irqreturn_t
c0_compare_interrupt(int irq
, void *dev_id
)
131 const int r2
= cpu_has_mips_r2_r6
;
132 struct clock_event_device
*cd
;
133 int cpu
= smp_processor_id();
137 * Before R2 of the architecture there was no way to see if a
138 * performance counter interrupt was pending, so we have to run
139 * the performance counter interrupt handler anyway.
141 if (handle_perf_irq(r2
))
145 * The same applies to performance counter interrupts. But with the
146 * above we now know that the reason we got here must be a timer
147 * interrupt. Being the paranoiacs we are we check anyway.
149 if (!r2
|| (read_c0_cause() & CAUSEF_TI
)) {
150 /* Clear Count/Compare Interrupt */
151 write_c0_compare(read_c0_compare());
152 cd
= &per_cpu(mips_clockevent_device
, cpu
);
153 cd
->event_handler(cd
);
161 struct irqaction c0_compare_irqaction
= {
162 .handler
= c0_compare_interrupt
,
164 * IRQF_SHARED: The timer interrupt may be shared with other interrupts
165 * such as perf counter and FDC interrupts.
167 .flags
= IRQF_PERCPU
| IRQF_TIMER
| IRQF_SHARED
,
172 void mips_event_handler(struct clock_event_device
*dev
)
177 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
179 static int c0_compare_int_pending(void)
181 /* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */
182 return (read_c0_cause() >> cp0_compare_irq_shift
) & (1ul << CAUSEB_IP
);
186 * Compare interrupt can be routed and latched outside the core,
187 * so wait up to worst case number of cycle counter ticks for timer interrupt
188 * changes to propagate to the cause register.
190 #define COMPARE_INT_SEEN_TICKS 50
192 int c0_compare_int_usable(void)
197 #ifdef CONFIG_KVM_GUEST
202 * IP7 already pending? Try to clear it by acking the timer.
204 if (c0_compare_int_pending()) {
205 cnt
= read_c0_count();
206 write_c0_compare(cnt
);
207 back_to_back_c0_hazard();
208 while (read_c0_count() < (cnt
+ COMPARE_INT_SEEN_TICKS
))
209 if (!c0_compare_int_pending())
211 if (c0_compare_int_pending())
215 for (delta
= 0x10; delta
<= 0x400000; delta
<<= 1) {
216 cnt
= read_c0_count();
218 write_c0_compare(cnt
);
219 back_to_back_c0_hazard();
220 if ((int)(read_c0_count() - cnt
) < 0)
222 /* increase delta if the timer was already expired */
225 while ((int)(read_c0_count() - cnt
) <= 0)
226 ; /* Wait for expiry */
228 while (read_c0_count() < (cnt
+ COMPARE_INT_SEEN_TICKS
))
229 if (c0_compare_int_pending())
231 if (!c0_compare_int_pending())
233 cnt
= read_c0_count();
234 write_c0_compare(cnt
);
235 back_to_back_c0_hazard();
236 while (read_c0_count() < (cnt
+ COMPARE_INT_SEEN_TICKS
))
237 if (!c0_compare_int_pending())
239 if (c0_compare_int_pending())
243 * Feels like a real count / compare timer.
248 unsigned int __weak
get_c0_compare_int(void)
250 return MIPS_CPU_IRQ_BASE
+ cp0_compare_irq
;
253 int r4k_clockevent_init(void)
255 unsigned long flags
= IRQF_PERCPU
| IRQF_TIMER
| IRQF_SHARED
;
256 unsigned int cpu
= smp_processor_id();
257 struct clock_event_device
*cd
;
258 unsigned int irq
, min_delta
;
260 if (!cpu_has_counter
|| !mips_hpt_frequency
)
263 if (!c0_compare_int_usable())
267 * With vectored interrupts things are getting platform specific.
268 * get_c0_compare_int is a hook to allow a platform to return the
269 * interrupt number of its liking.
271 irq
= get_c0_compare_int();
273 cd
= &per_cpu(mips_clockevent_device
, cpu
);
276 cd
->features
= CLOCK_EVT_FEAT_ONESHOT
|
277 CLOCK_EVT_FEAT_C3STOP
|
278 CLOCK_EVT_FEAT_PERCPU
;
280 min_delta
= calculate_min_delta();
284 cd
->cpumask
= cpumask_of(cpu
);
285 cd
->set_next_event
= mips_next_event
;
286 cd
->event_handler
= mips_event_handler
;
288 clockevents_config_and_register(cd
, mips_hpt_frequency
, min_delta
, 0x7fffffff);
290 if (cp0_timer_irq_installed
)
293 cp0_timer_irq_installed
= 1;
295 if (request_irq(irq
, c0_compare_interrupt
, flags
, "timer",
296 c0_compare_interrupt
))
297 pr_err("Failed to request irq %d (timer)\n", irq
);