Linux 5.7.6
[linux/fpc-iii.git] / arch / mips / kernel / cpu-probe.c
blobf21a2304401f92ef076d83f0533a0eb13118d382
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Processor capabilities determination functions.
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 */
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/ptrace.h>
13 #include <linux/smp.h>
14 #include <linux/stddef.h>
15 #include <linux/export.h>
17 #include <asm/bugs.h>
18 #include <asm/cpu.h>
19 #include <asm/cpu-features.h>
20 #include <asm/cpu-type.h>
21 #include <asm/fpu.h>
22 #include <asm/mipsregs.h>
23 #include <asm/mipsmtregs.h>
24 #include <asm/msa.h>
25 #include <asm/watch.h>
26 #include <asm/elf.h>
27 #include <asm/pgtable-bits.h>
28 #include <asm/spram.h>
29 #include <linux/uaccess.h>
31 /* Hardware capabilities */
32 unsigned int elf_hwcap __read_mostly;
33 EXPORT_SYMBOL_GPL(elf_hwcap);
35 #ifdef CONFIG_MIPS_FP_SUPPORT
38 * Get the FPU Implementation/Revision.
40 static inline unsigned long cpu_get_fpu_id(void)
42 unsigned long tmp, fpu_id;
44 tmp = read_c0_status();
45 __enable_fpu(FPU_AS_IS);
46 fpu_id = read_32bit_cp1_register(CP1_REVISION);
47 write_c0_status(tmp);
48 return fpu_id;
52 * Check if the CPU has an external FPU.
54 static inline int __cpu_has_fpu(void)
56 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
60 * Determine the FCSR mask for FPU hardware.
62 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
64 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
66 fcsr = c->fpu_csr31;
67 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
69 sr = read_c0_status();
70 __enable_fpu(FPU_AS_IS);
72 fcsr0 = fcsr & mask;
73 write_32bit_cp1_register(CP1_STATUS, fcsr0);
74 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
76 fcsr1 = fcsr | ~mask;
77 write_32bit_cp1_register(CP1_STATUS, fcsr1);
78 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
80 write_32bit_cp1_register(CP1_STATUS, fcsr);
82 write_c0_status(sr);
84 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
88 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
89 * supported by FPU hardware.
91 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
93 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
94 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
95 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
96 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
98 sr = read_c0_status();
99 __enable_fpu(FPU_AS_IS);
101 fir = read_32bit_cp1_register(CP1_REVISION);
102 if (fir & MIPS_FPIR_HAS2008) {
103 fcsr = read_32bit_cp1_register(CP1_STATUS);
106 * MAC2008 toolchain never landed in real world, so we're only
107 * testing wether it can be disabled and don't try to enabled
108 * it.
110 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008 | FPU_CSR_MAC2008);
111 write_32bit_cp1_register(CP1_STATUS, fcsr0);
112 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
114 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
115 write_32bit_cp1_register(CP1_STATUS, fcsr1);
116 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
118 write_32bit_cp1_register(CP1_STATUS, fcsr);
120 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2)) {
122 * The bit for MAC2008 might be reused by R6 in future,
123 * so we only test for R2-R5.
125 if (fcsr0 & FPU_CSR_MAC2008)
126 c->options |= MIPS_CPU_MAC_2008_ONLY;
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
181 break;
182 case LEGACY:
183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
201 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
232 static int __init ieee754_setup(char *s)
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
251 return 0;
254 early_param("ieee754", ieee754_setup);
257 * Set the FIR feature flags for the FPU emulator.
259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
261 u32 value;
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
273 c->fpu_id = value;
276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277 static unsigned int mips_nofpu_msk31;
280 * Set options for FPU hardware.
282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_UFRP)
293 c->options |= MIPS_CPU_UFR;
294 if (c->fpu_id & MIPS_FPIR_FREP)
295 c->options |= MIPS_CPU_FRE;
298 cpu_set_fpu_fcsr_mask(c);
299 cpu_set_fpu_2008(c);
300 cpu_set_nan_2008(c);
304 * Set options for the FPU emulator.
306 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
308 c->options &= ~MIPS_CPU_FPU;
309 c->fpu_msk31 = mips_nofpu_msk31;
311 cpu_set_nofpu_2008(c);
312 cpu_set_nan_2008(c);
313 cpu_set_nofpu_id(c);
316 static int mips_fpu_disabled;
318 static int __init fpu_disable(char *s)
320 cpu_set_nofpu_opts(&boot_cpu_data);
321 mips_fpu_disabled = 1;
323 return 1;
326 __setup("nofpu", fpu_disable);
328 #else /* !CONFIG_MIPS_FP_SUPPORT */
330 #define mips_fpu_disabled 1
332 static inline unsigned long cpu_get_fpu_id(void)
334 return FPIR_IMP_NONE;
337 static inline int __cpu_has_fpu(void)
339 return 0;
342 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
344 /* no-op */
347 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
349 /* no-op */
352 #endif /* CONFIG_MIPS_FP_SUPPORT */
354 static inline unsigned long cpu_get_msa_id(void)
356 unsigned long status, msa_id;
358 status = read_c0_status();
359 __enable_fpu(FPU_64BIT);
360 enable_msa();
361 msa_id = read_msa_ir();
362 disable_msa();
363 write_c0_status(status);
364 return msa_id;
367 static int mips_dsp_disabled;
369 static int __init dsp_disable(char *s)
371 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
372 mips_dsp_disabled = 1;
374 return 1;
377 __setup("nodsp", dsp_disable);
379 static int mips_htw_disabled;
381 static int __init htw_disable(char *s)
383 mips_htw_disabled = 1;
384 cpu_data[0].options &= ~MIPS_CPU_HTW;
385 write_c0_pwctl(read_c0_pwctl() &
386 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
388 return 1;
391 __setup("nohtw", htw_disable);
393 static int mips_ftlb_disabled;
394 static int mips_has_ftlb_configured;
396 enum ftlb_flags {
397 FTLB_EN = 1 << 0,
398 FTLB_SET_PROB = 1 << 1,
401 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
403 static int __init ftlb_disable(char *s)
405 unsigned int config4, mmuextdef;
408 * If the core hasn't done any FTLB configuration, there is nothing
409 * for us to do here.
411 if (!mips_has_ftlb_configured)
412 return 1;
414 /* Disable it in the boot cpu */
415 if (set_ftlb_enable(&cpu_data[0], 0)) {
416 pr_warn("Can't turn FTLB off\n");
417 return 1;
420 config4 = read_c0_config4();
422 /* Check that FTLB has been disabled */
423 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
424 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
425 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
426 /* This should never happen */
427 pr_warn("FTLB could not be disabled!\n");
428 return 1;
431 mips_ftlb_disabled = 1;
432 mips_has_ftlb_configured = 0;
435 * noftlb is mainly used for debug purposes so print
436 * an informative message instead of using pr_debug()
438 pr_info("FTLB has been disabled\n");
441 * Some of these bits are duplicated in the decode_config4.
442 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
443 * once FTLB has been disabled so undo what decode_config4 did.
445 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
446 cpu_data[0].tlbsizeftlbsets;
447 cpu_data[0].tlbsizeftlbsets = 0;
448 cpu_data[0].tlbsizeftlbways = 0;
450 return 1;
453 __setup("noftlb", ftlb_disable);
456 * Check if the CPU has per tc perf counters
458 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
460 if (read_c0_config7() & MTI_CONF7_PTC)
461 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
464 static inline void check_errata(void)
466 struct cpuinfo_mips *c = &current_cpu_data;
468 switch (current_cpu_type()) {
469 case CPU_34K:
471 * Erratum "RPS May Cause Incorrect Instruction Execution"
472 * This code only handles VPE0, any SMP/RTOS code
473 * making use of VPE1 will be responsable for that VPE.
475 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
476 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
477 break;
478 default:
479 break;
483 void __init check_bugs32(void)
485 check_errata();
489 * Probe whether cpu has config register by trying to play with
490 * alternate cache bit and see whether it matters.
491 * It's used by cpu_probe to distinguish between R3000A and R3081.
493 static inline int cpu_has_confreg(void)
495 #ifdef CONFIG_CPU_R3000
496 extern unsigned long r3k_cache_size(unsigned long);
497 unsigned long size1, size2;
498 unsigned long cfg = read_c0_conf();
500 size1 = r3k_cache_size(ST0_ISC);
501 write_c0_conf(cfg ^ R30XX_CONF_AC);
502 size2 = r3k_cache_size(ST0_ISC);
503 write_c0_conf(cfg);
504 return size1 != size2;
505 #else
506 return 0;
507 #endif
510 static inline void set_elf_platform(int cpu, const char *plat)
512 if (cpu == 0)
513 __elf_platform = plat;
516 static inline void set_elf_base_platform(const char *plat)
518 if (__elf_base_platform == NULL) {
519 __elf_base_platform = plat;
523 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
525 #ifdef __NEED_VMBITS_PROBE
526 write_c0_entryhi(0x3fffffffffffe000ULL);
527 back_to_back_c0_hazard();
528 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
529 #endif
532 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
534 switch (isa) {
535 case MIPS_CPU_ISA_M64R2:
536 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
537 set_elf_base_platform("mips64r2");
538 /* fall through */
539 case MIPS_CPU_ISA_M64R1:
540 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
541 set_elf_base_platform("mips64");
542 /* fall through */
543 case MIPS_CPU_ISA_V:
544 c->isa_level |= MIPS_CPU_ISA_V;
545 set_elf_base_platform("mips5");
546 /* fall through */
547 case MIPS_CPU_ISA_IV:
548 c->isa_level |= MIPS_CPU_ISA_IV;
549 set_elf_base_platform("mips4");
550 /* fall through */
551 case MIPS_CPU_ISA_III:
552 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
553 set_elf_base_platform("mips3");
554 break;
556 /* R6 incompatible with everything else */
557 case MIPS_CPU_ISA_M64R6:
558 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
559 set_elf_base_platform("mips64r6");
560 /* fall through */
561 case MIPS_CPU_ISA_M32R6:
562 c->isa_level |= MIPS_CPU_ISA_M32R6;
563 set_elf_base_platform("mips32r6");
564 /* Break here so we don't add incompatible ISAs */
565 break;
566 case MIPS_CPU_ISA_M32R2:
567 c->isa_level |= MIPS_CPU_ISA_M32R2;
568 set_elf_base_platform("mips32r2");
569 /* fall through */
570 case MIPS_CPU_ISA_M32R1:
571 c->isa_level |= MIPS_CPU_ISA_M32R1;
572 set_elf_base_platform("mips32");
573 /* fall through */
574 case MIPS_CPU_ISA_II:
575 c->isa_level |= MIPS_CPU_ISA_II;
576 set_elf_base_platform("mips2");
577 break;
581 static char unknown_isa[] = KERN_ERR \
582 "Unsupported ISA type, c0.config0: %d.";
584 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
587 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
590 * 0 = All TLBWR instructions go to FTLB
591 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
592 * FTLB and 1 goes to the VTLB.
593 * 2 = 7:1: As above with 7:1 ratio.
594 * 3 = 3:1: As above with 3:1 ratio.
596 * Use the linear midpoint as the probability threshold.
598 if (probability >= 12)
599 return 1;
600 else if (probability >= 6)
601 return 2;
602 else
604 * So FTLB is less than 4 times bigger than VTLB.
605 * A 3:1 ratio can still be useful though.
607 return 3;
610 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
612 unsigned int config;
614 /* It's implementation dependent how the FTLB can be enabled */
615 switch (c->cputype) {
616 case CPU_PROAPTIV:
617 case CPU_P5600:
618 case CPU_P6600:
619 /* proAptiv & related cores use Config6 to enable the FTLB */
620 config = read_c0_config6();
622 if (flags & FTLB_EN)
623 config |= MIPS_CONF6_FTLBEN;
624 else
625 config &= ~MIPS_CONF6_FTLBEN;
627 if (flags & FTLB_SET_PROB) {
628 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
629 config |= calculate_ftlb_probability(c)
630 << MIPS_CONF6_FTLBP_SHIFT;
633 write_c0_config6(config);
634 back_to_back_c0_hazard();
635 break;
636 case CPU_I6400:
637 case CPU_I6500:
638 /* There's no way to disable the FTLB */
639 if (!(flags & FTLB_EN))
640 return 1;
641 return 0;
642 case CPU_LOONGSON64:
643 /* Flush ITLB, DTLB, VTLB and FTLB */
644 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
645 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
646 /* Loongson-3 cores use Config6 to enable the FTLB */
647 config = read_c0_config6();
648 if (flags & FTLB_EN)
649 /* Enable FTLB */
650 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
651 else
652 /* Disable FTLB */
653 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
654 break;
655 default:
656 return 1;
659 return 0;
662 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
664 unsigned int config0;
665 int isa, mt;
667 config0 = read_c0_config();
670 * Look for Standard TLB or Dual VTLB and FTLB
672 mt = config0 & MIPS_CONF_MT;
673 if (mt == MIPS_CONF_MT_TLB)
674 c->options |= MIPS_CPU_TLB;
675 else if (mt == MIPS_CONF_MT_FTLB)
676 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
678 isa = (config0 & MIPS_CONF_AT) >> 13;
679 switch (isa) {
680 case 0:
681 switch ((config0 & MIPS_CONF_AR) >> 10) {
682 case 0:
683 set_isa(c, MIPS_CPU_ISA_M32R1);
684 break;
685 case 1:
686 set_isa(c, MIPS_CPU_ISA_M32R2);
687 break;
688 case 2:
689 set_isa(c, MIPS_CPU_ISA_M32R6);
690 break;
691 default:
692 goto unknown;
694 break;
695 case 2:
696 switch ((config0 & MIPS_CONF_AR) >> 10) {
697 case 0:
698 set_isa(c, MIPS_CPU_ISA_M64R1);
699 break;
700 case 1:
701 set_isa(c, MIPS_CPU_ISA_M64R2);
702 break;
703 case 2:
704 set_isa(c, MIPS_CPU_ISA_M64R6);
705 break;
706 default:
707 goto unknown;
709 break;
710 default:
711 goto unknown;
714 return config0 & MIPS_CONF_M;
716 unknown:
717 panic(unknown_isa, config0);
720 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
722 unsigned int config1;
724 config1 = read_c0_config1();
726 if (config1 & MIPS_CONF1_MD)
727 c->ases |= MIPS_ASE_MDMX;
728 if (config1 & MIPS_CONF1_PC)
729 c->options |= MIPS_CPU_PERF;
730 if (config1 & MIPS_CONF1_WR)
731 c->options |= MIPS_CPU_WATCH;
732 if (config1 & MIPS_CONF1_CA)
733 c->ases |= MIPS_ASE_MIPS16;
734 if (config1 & MIPS_CONF1_EP)
735 c->options |= MIPS_CPU_EJTAG;
736 if (config1 & MIPS_CONF1_FP) {
737 c->options |= MIPS_CPU_FPU;
738 c->options |= MIPS_CPU_32FPR;
740 if (cpu_has_tlb) {
741 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
742 c->tlbsizevtlb = c->tlbsize;
743 c->tlbsizeftlbsets = 0;
746 return config1 & MIPS_CONF_M;
749 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
751 unsigned int config2;
753 config2 = read_c0_config2();
755 if (config2 & MIPS_CONF2_SL)
756 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
758 return config2 & MIPS_CONF_M;
761 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
763 unsigned int config3;
765 config3 = read_c0_config3();
767 if (config3 & MIPS_CONF3_SM) {
768 c->ases |= MIPS_ASE_SMARTMIPS;
769 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
771 if (config3 & MIPS_CONF3_RXI)
772 c->options |= MIPS_CPU_RIXI;
773 if (config3 & MIPS_CONF3_CTXTC)
774 c->options |= MIPS_CPU_CTXTC;
775 if (config3 & MIPS_CONF3_DSP)
776 c->ases |= MIPS_ASE_DSP;
777 if (config3 & MIPS_CONF3_DSP2P) {
778 c->ases |= MIPS_ASE_DSP2P;
779 if (cpu_has_mips_r6)
780 c->ases |= MIPS_ASE_DSP3;
782 if (config3 & MIPS_CONF3_VINT)
783 c->options |= MIPS_CPU_VINT;
784 if (config3 & MIPS_CONF3_VEIC)
785 c->options |= MIPS_CPU_VEIC;
786 if (config3 & MIPS_CONF3_LPA)
787 c->options |= MIPS_CPU_LPA;
788 if (config3 & MIPS_CONF3_MT)
789 c->ases |= MIPS_ASE_MIPSMT;
790 if (config3 & MIPS_CONF3_ULRI)
791 c->options |= MIPS_CPU_ULRI;
792 if (config3 & MIPS_CONF3_ISA)
793 c->options |= MIPS_CPU_MICROMIPS;
794 if (config3 & MIPS_CONF3_VZ)
795 c->ases |= MIPS_ASE_VZ;
796 if (config3 & MIPS_CONF3_SC)
797 c->options |= MIPS_CPU_SEGMENTS;
798 if (config3 & MIPS_CONF3_BI)
799 c->options |= MIPS_CPU_BADINSTR;
800 if (config3 & MIPS_CONF3_BP)
801 c->options |= MIPS_CPU_BADINSTRP;
802 if (config3 & MIPS_CONF3_MSA)
803 c->ases |= MIPS_ASE_MSA;
804 if (config3 & MIPS_CONF3_PW) {
805 c->htw_seq = 0;
806 c->options |= MIPS_CPU_HTW;
808 if (config3 & MIPS_CONF3_CDMM)
809 c->options |= MIPS_CPU_CDMM;
810 if (config3 & MIPS_CONF3_SP)
811 c->options |= MIPS_CPU_SP;
813 return config3 & MIPS_CONF_M;
816 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
818 unsigned int config4;
819 unsigned int newcf4;
820 unsigned int mmuextdef;
821 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
822 unsigned long asid_mask;
824 config4 = read_c0_config4();
826 if (cpu_has_tlb) {
827 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
828 c->options |= MIPS_CPU_TLBINV;
831 * R6 has dropped the MMUExtDef field from config4.
832 * On R6 the fields always describe the FTLB, and only if it is
833 * present according to Config.MT.
835 if (!cpu_has_mips_r6)
836 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
837 else if (cpu_has_ftlb)
838 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
839 else
840 mmuextdef = 0;
842 switch (mmuextdef) {
843 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
844 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
845 c->tlbsizevtlb = c->tlbsize;
846 break;
847 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
848 c->tlbsizevtlb +=
849 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
850 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
851 c->tlbsize = c->tlbsizevtlb;
852 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
853 /* fall through */
854 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
855 if (mips_ftlb_disabled)
856 break;
857 newcf4 = (config4 & ~ftlb_page) |
858 (page_size_ftlb(mmuextdef) <<
859 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
860 write_c0_config4(newcf4);
861 back_to_back_c0_hazard();
862 config4 = read_c0_config4();
863 if (config4 != newcf4) {
864 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
865 PAGE_SIZE, config4);
866 /* Switch FTLB off */
867 set_ftlb_enable(c, 0);
868 mips_ftlb_disabled = 1;
869 break;
871 c->tlbsizeftlbsets = 1 <<
872 ((config4 & MIPS_CONF4_FTLBSETS) >>
873 MIPS_CONF4_FTLBSETS_SHIFT);
874 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
875 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
876 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
877 mips_has_ftlb_configured = 1;
878 break;
882 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
883 >> MIPS_CONF4_KSCREXIST_SHIFT;
885 asid_mask = MIPS_ENTRYHI_ASID;
886 if (config4 & MIPS_CONF4_AE)
887 asid_mask |= MIPS_ENTRYHI_ASIDX;
888 set_cpu_asid_mask(c, asid_mask);
891 * Warn if the computed ASID mask doesn't match the mask the kernel
892 * is built for. This may indicate either a serious problem or an
893 * easy optimisation opportunity, but either way should be addressed.
895 WARN_ON(asid_mask != cpu_asid_mask(c));
897 return config4 & MIPS_CONF_M;
900 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
902 unsigned int config5, max_mmid_width;
903 unsigned long asid_mask;
905 config5 = read_c0_config5();
906 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
908 if (cpu_has_mips_r6) {
909 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
910 config5 |= MIPS_CONF5_MI;
911 else
912 config5 &= ~MIPS_CONF5_MI;
915 write_c0_config5(config5);
917 if (config5 & MIPS_CONF5_EVA)
918 c->options |= MIPS_CPU_EVA;
919 if (config5 & MIPS_CONF5_MRP)
920 c->options |= MIPS_CPU_MAAR;
921 if (config5 & MIPS_CONF5_LLB)
922 c->options |= MIPS_CPU_RW_LLB;
923 if (config5 & MIPS_CONF5_MVH)
924 c->options |= MIPS_CPU_MVH;
925 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
926 c->options |= MIPS_CPU_VP;
927 if (config5 & MIPS_CONF5_CA2)
928 c->ases |= MIPS_ASE_MIPS16E2;
930 if (config5 & MIPS_CONF5_CRCP)
931 elf_hwcap |= HWCAP_MIPS_CRC32;
933 if (cpu_has_mips_r6) {
934 /* Ensure the write to config5 above takes effect */
935 back_to_back_c0_hazard();
937 /* Check whether we successfully enabled MMID support */
938 config5 = read_c0_config5();
939 if (config5 & MIPS_CONF5_MI)
940 c->options |= MIPS_CPU_MMID;
943 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
944 * for the CPU we're running on, or if CPUs in an SMP system
945 * have inconsistent MMID support.
947 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
949 if (cpu_has_mmid) {
950 write_c0_memorymapid(~0ul);
951 back_to_back_c0_hazard();
952 asid_mask = read_c0_memorymapid();
955 * We maintain a bitmap to track MMID allocation, and
956 * need a sensible upper bound on the size of that
957 * bitmap. The initial CPU with MMID support (I6500)
958 * supports 16 bit MMIDs, which gives us an 8KiB
959 * bitmap. The architecture recommends that hardware
960 * support 32 bit MMIDs, which would give us a 512MiB
961 * bitmap - that's too big in most cases.
963 * Cap MMID width at 16 bits for now & we can revisit
964 * this if & when hardware supports anything wider.
966 max_mmid_width = 16;
967 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
968 pr_info("Capping MMID width at %d bits",
969 max_mmid_width);
970 asid_mask = GENMASK(max_mmid_width - 1, 0);
973 set_cpu_asid_mask(c, asid_mask);
977 return config5 & MIPS_CONF_M;
980 static void decode_configs(struct cpuinfo_mips *c)
982 int ok;
984 /* MIPS32 or MIPS64 compliant CPU. */
985 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
986 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
988 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
990 /* Enable FTLB if present and not disabled */
991 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
993 ok = decode_config0(c); /* Read Config registers. */
994 BUG_ON(!ok); /* Arch spec violation! */
995 if (ok)
996 ok = decode_config1(c);
997 if (ok)
998 ok = decode_config2(c);
999 if (ok)
1000 ok = decode_config3(c);
1001 if (ok)
1002 ok = decode_config4(c);
1003 if (ok)
1004 ok = decode_config5(c);
1006 /* Probe the EBase.WG bit */
1007 if (cpu_has_mips_r2_r6) {
1008 u64 ebase;
1009 unsigned int status;
1011 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
1012 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
1013 : (s32)read_c0_ebase();
1014 if (ebase & MIPS_EBASE_WG) {
1015 /* WG bit already set, we can avoid the clumsy probe */
1016 c->options |= MIPS_CPU_EBASE_WG;
1017 } else {
1018 /* Its UNDEFINED to change EBase while BEV=0 */
1019 status = read_c0_status();
1020 write_c0_status(status | ST0_BEV);
1021 irq_enable_hazard();
1023 * On pre-r6 cores, this may well clobber the upper bits
1024 * of EBase. This is hard to avoid without potentially
1025 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
1027 if (cpu_has_mips64r6)
1028 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
1029 else
1030 write_c0_ebase(ebase | MIPS_EBASE_WG);
1031 back_to_back_c0_hazard();
1032 /* Restore BEV */
1033 write_c0_status(status);
1034 if (read_c0_ebase() & MIPS_EBASE_WG) {
1035 c->options |= MIPS_CPU_EBASE_WG;
1036 write_c0_ebase(ebase);
1041 /* configure the FTLB write probability */
1042 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
1044 mips_probe_watch_registers(c);
1046 #ifndef CONFIG_MIPS_CPS
1047 if (cpu_has_mips_r2_r6) {
1048 unsigned int core;
1050 core = get_ebase_cpunum();
1051 if (cpu_has_mipsmt)
1052 core >>= fls(core_nvpes()) - 1;
1053 cpu_set_core(c, core);
1055 #endif
1059 * Probe for certain guest capabilities by writing config bits and reading back.
1060 * Finally write back the original value.
1062 #define probe_gc0_config(name, maxconf, bits) \
1063 do { \
1064 unsigned int tmp; \
1065 tmp = read_gc0_##name(); \
1066 write_gc0_##name(tmp | (bits)); \
1067 back_to_back_c0_hazard(); \
1068 maxconf = read_gc0_##name(); \
1069 write_gc0_##name(tmp); \
1070 } while (0)
1073 * Probe for dynamic guest capabilities by changing certain config bits and
1074 * reading back to see if they change. Finally write back the original value.
1076 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
1077 do { \
1078 maxconf = read_gc0_##name(); \
1079 write_gc0_##name(maxconf ^ (bits)); \
1080 back_to_back_c0_hazard(); \
1081 dynconf = maxconf ^ read_gc0_##name(); \
1082 write_gc0_##name(maxconf); \
1083 maxconf |= dynconf; \
1084 } while (0)
1086 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1088 unsigned int config0;
1090 probe_gc0_config(config, config0, MIPS_CONF_M);
1092 if (config0 & MIPS_CONF_M)
1093 c->guest.conf |= BIT(1);
1094 return config0 & MIPS_CONF_M;
1097 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1099 unsigned int config1, config1_dyn;
1101 probe_gc0_config_dyn(config1, config1, config1_dyn,
1102 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1103 MIPS_CONF1_FP);
1105 if (config1 & MIPS_CONF1_FP)
1106 c->guest.options |= MIPS_CPU_FPU;
1107 if (config1_dyn & MIPS_CONF1_FP)
1108 c->guest.options_dyn |= MIPS_CPU_FPU;
1110 if (config1 & MIPS_CONF1_WR)
1111 c->guest.options |= MIPS_CPU_WATCH;
1112 if (config1_dyn & MIPS_CONF1_WR)
1113 c->guest.options_dyn |= MIPS_CPU_WATCH;
1115 if (config1 & MIPS_CONF1_PC)
1116 c->guest.options |= MIPS_CPU_PERF;
1117 if (config1_dyn & MIPS_CONF1_PC)
1118 c->guest.options_dyn |= MIPS_CPU_PERF;
1120 if (config1 & MIPS_CONF_M)
1121 c->guest.conf |= BIT(2);
1122 return config1 & MIPS_CONF_M;
1125 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1127 unsigned int config2;
1129 probe_gc0_config(config2, config2, MIPS_CONF_M);
1131 if (config2 & MIPS_CONF_M)
1132 c->guest.conf |= BIT(3);
1133 return config2 & MIPS_CONF_M;
1136 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1138 unsigned int config3, config3_dyn;
1140 probe_gc0_config_dyn(config3, config3, config3_dyn,
1141 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1142 MIPS_CONF3_CTXTC);
1144 if (config3 & MIPS_CONF3_CTXTC)
1145 c->guest.options |= MIPS_CPU_CTXTC;
1146 if (config3_dyn & MIPS_CONF3_CTXTC)
1147 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1149 if (config3 & MIPS_CONF3_PW)
1150 c->guest.options |= MIPS_CPU_HTW;
1152 if (config3 & MIPS_CONF3_ULRI)
1153 c->guest.options |= MIPS_CPU_ULRI;
1155 if (config3 & MIPS_CONF3_SC)
1156 c->guest.options |= MIPS_CPU_SEGMENTS;
1158 if (config3 & MIPS_CONF3_BI)
1159 c->guest.options |= MIPS_CPU_BADINSTR;
1160 if (config3 & MIPS_CONF3_BP)
1161 c->guest.options |= MIPS_CPU_BADINSTRP;
1163 if (config3 & MIPS_CONF3_MSA)
1164 c->guest.ases |= MIPS_ASE_MSA;
1165 if (config3_dyn & MIPS_CONF3_MSA)
1166 c->guest.ases_dyn |= MIPS_ASE_MSA;
1168 if (config3 & MIPS_CONF_M)
1169 c->guest.conf |= BIT(4);
1170 return config3 & MIPS_CONF_M;
1173 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1175 unsigned int config4;
1177 probe_gc0_config(config4, config4,
1178 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1180 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1181 >> MIPS_CONF4_KSCREXIST_SHIFT;
1183 if (config4 & MIPS_CONF_M)
1184 c->guest.conf |= BIT(5);
1185 return config4 & MIPS_CONF_M;
1188 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1190 unsigned int config5, config5_dyn;
1192 probe_gc0_config_dyn(config5, config5, config5_dyn,
1193 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1195 if (config5 & MIPS_CONF5_MRP)
1196 c->guest.options |= MIPS_CPU_MAAR;
1197 if (config5_dyn & MIPS_CONF5_MRP)
1198 c->guest.options_dyn |= MIPS_CPU_MAAR;
1200 if (config5 & MIPS_CONF5_LLB)
1201 c->guest.options |= MIPS_CPU_RW_LLB;
1203 if (config5 & MIPS_CONF5_MVH)
1204 c->guest.options |= MIPS_CPU_MVH;
1206 if (config5 & MIPS_CONF_M)
1207 c->guest.conf |= BIT(6);
1208 return config5 & MIPS_CONF_M;
1211 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1213 unsigned int ok;
1215 ok = decode_guest_config0(c);
1216 if (ok)
1217 ok = decode_guest_config1(c);
1218 if (ok)
1219 ok = decode_guest_config2(c);
1220 if (ok)
1221 ok = decode_guest_config3(c);
1222 if (ok)
1223 ok = decode_guest_config4(c);
1224 if (ok)
1225 decode_guest_config5(c);
1228 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1230 unsigned int guestctl0, temp;
1232 guestctl0 = read_c0_guestctl0();
1234 if (guestctl0 & MIPS_GCTL0_G0E)
1235 c->options |= MIPS_CPU_GUESTCTL0EXT;
1236 if (guestctl0 & MIPS_GCTL0_G1)
1237 c->options |= MIPS_CPU_GUESTCTL1;
1238 if (guestctl0 & MIPS_GCTL0_G2)
1239 c->options |= MIPS_CPU_GUESTCTL2;
1240 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1241 c->options |= MIPS_CPU_GUESTID;
1244 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1245 * first, otherwise all data accesses will be fully virtualised
1246 * as if they were performed by guest mode.
1248 write_c0_guestctl1(0);
1249 tlbw_use_hazard();
1251 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1252 back_to_back_c0_hazard();
1253 temp = read_c0_guestctl0();
1255 if (temp & MIPS_GCTL0_DRG) {
1256 write_c0_guestctl0(guestctl0);
1257 c->options |= MIPS_CPU_DRG;
1262 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1264 if (cpu_has_guestid) {
1265 /* determine the number of bits of GuestID available */
1266 write_c0_guestctl1(MIPS_GCTL1_ID);
1267 back_to_back_c0_hazard();
1268 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1269 >> MIPS_GCTL1_ID_SHIFT;
1270 write_c0_guestctl1(0);
1274 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1276 /* determine the number of bits of GTOffset available */
1277 write_c0_gtoffset(0xffffffff);
1278 back_to_back_c0_hazard();
1279 c->gtoffset_mask = read_c0_gtoffset();
1280 write_c0_gtoffset(0);
1283 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1285 cpu_probe_guestctl0(c);
1286 if (cpu_has_guestctl1)
1287 cpu_probe_guestctl1(c);
1289 cpu_probe_gtoffset(c);
1291 decode_guest_configs(c);
1294 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1295 | MIPS_CPU_COUNTER)
1297 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1299 switch (c->processor_id & PRID_IMP_MASK) {
1300 case PRID_IMP_R2000:
1301 c->cputype = CPU_R2000;
1302 __cpu_name[cpu] = "R2000";
1303 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1304 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1305 MIPS_CPU_NOFPUEX;
1306 if (__cpu_has_fpu())
1307 c->options |= MIPS_CPU_FPU;
1308 c->tlbsize = 64;
1309 break;
1310 case PRID_IMP_R3000:
1311 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1312 if (cpu_has_confreg()) {
1313 c->cputype = CPU_R3081E;
1314 __cpu_name[cpu] = "R3081";
1315 } else {
1316 c->cputype = CPU_R3000A;
1317 __cpu_name[cpu] = "R3000A";
1319 } else {
1320 c->cputype = CPU_R3000;
1321 __cpu_name[cpu] = "R3000";
1323 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1324 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1325 MIPS_CPU_NOFPUEX;
1326 if (__cpu_has_fpu())
1327 c->options |= MIPS_CPU_FPU;
1328 c->tlbsize = 64;
1329 break;
1330 case PRID_IMP_R4000:
1331 if (read_c0_config() & CONF_SC) {
1332 if ((c->processor_id & PRID_REV_MASK) >=
1333 PRID_REV_R4400) {
1334 c->cputype = CPU_R4400PC;
1335 __cpu_name[cpu] = "R4400PC";
1336 } else {
1337 c->cputype = CPU_R4000PC;
1338 __cpu_name[cpu] = "R4000PC";
1340 } else {
1341 int cca = read_c0_config() & CONF_CM_CMASK;
1342 int mc;
1345 * SC and MC versions can't be reliably told apart,
1346 * but only the latter support coherent caching
1347 * modes so assume the firmware has set the KSEG0
1348 * coherency attribute reasonably (if uncached, we
1349 * assume SC).
1351 switch (cca) {
1352 case CONF_CM_CACHABLE_CE:
1353 case CONF_CM_CACHABLE_COW:
1354 case CONF_CM_CACHABLE_CUW:
1355 mc = 1;
1356 break;
1357 default:
1358 mc = 0;
1359 break;
1361 if ((c->processor_id & PRID_REV_MASK) >=
1362 PRID_REV_R4400) {
1363 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1364 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1365 } else {
1366 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1367 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1371 set_isa(c, MIPS_CPU_ISA_III);
1372 c->fpu_msk31 |= FPU_CSR_CONDX;
1373 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1374 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1375 MIPS_CPU_LLSC;
1376 c->tlbsize = 48;
1377 break;
1378 case PRID_IMP_VR41XX:
1379 set_isa(c, MIPS_CPU_ISA_III);
1380 c->fpu_msk31 |= FPU_CSR_CONDX;
1381 c->options = R4K_OPTS;
1382 c->tlbsize = 32;
1383 switch (c->processor_id & 0xf0) {
1384 case PRID_REV_VR4111:
1385 c->cputype = CPU_VR4111;
1386 __cpu_name[cpu] = "NEC VR4111";
1387 break;
1388 case PRID_REV_VR4121:
1389 c->cputype = CPU_VR4121;
1390 __cpu_name[cpu] = "NEC VR4121";
1391 break;
1392 case PRID_REV_VR4122:
1393 if ((c->processor_id & 0xf) < 0x3) {
1394 c->cputype = CPU_VR4122;
1395 __cpu_name[cpu] = "NEC VR4122";
1396 } else {
1397 c->cputype = CPU_VR4181A;
1398 __cpu_name[cpu] = "NEC VR4181A";
1400 break;
1401 case PRID_REV_VR4130:
1402 if ((c->processor_id & 0xf) < 0x4) {
1403 c->cputype = CPU_VR4131;
1404 __cpu_name[cpu] = "NEC VR4131";
1405 } else {
1406 c->cputype = CPU_VR4133;
1407 c->options |= MIPS_CPU_LLSC;
1408 __cpu_name[cpu] = "NEC VR4133";
1410 break;
1411 default:
1412 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1413 c->cputype = CPU_VR41XX;
1414 __cpu_name[cpu] = "NEC Vr41xx";
1415 break;
1417 break;
1418 case PRID_IMP_R4600:
1419 c->cputype = CPU_R4600;
1420 __cpu_name[cpu] = "R4600";
1421 set_isa(c, MIPS_CPU_ISA_III);
1422 c->fpu_msk31 |= FPU_CSR_CONDX;
1423 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1424 MIPS_CPU_LLSC;
1425 c->tlbsize = 48;
1426 break;
1427 #if 0
1428 case PRID_IMP_R4650:
1430 * This processor doesn't have an MMU, so it's not
1431 * "real easy" to run Linux on it. It is left purely
1432 * for documentation. Commented out because it shares
1433 * it's c0_prid id number with the TX3900.
1435 c->cputype = CPU_R4650;
1436 __cpu_name[cpu] = "R4650";
1437 set_isa(c, MIPS_CPU_ISA_III);
1438 c->fpu_msk31 |= FPU_CSR_CONDX;
1439 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1440 c->tlbsize = 48;
1441 break;
1442 #endif
1443 case PRID_IMP_TX39:
1444 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1445 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1447 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1448 c->cputype = CPU_TX3927;
1449 __cpu_name[cpu] = "TX3927";
1450 c->tlbsize = 64;
1451 } else {
1452 switch (c->processor_id & PRID_REV_MASK) {
1453 case PRID_REV_TX3912:
1454 c->cputype = CPU_TX3912;
1455 __cpu_name[cpu] = "TX3912";
1456 c->tlbsize = 32;
1457 break;
1458 case PRID_REV_TX3922:
1459 c->cputype = CPU_TX3922;
1460 __cpu_name[cpu] = "TX3922";
1461 c->tlbsize = 64;
1462 break;
1465 break;
1466 case PRID_IMP_R4700:
1467 c->cputype = CPU_R4700;
1468 __cpu_name[cpu] = "R4700";
1469 set_isa(c, MIPS_CPU_ISA_III);
1470 c->fpu_msk31 |= FPU_CSR_CONDX;
1471 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1472 MIPS_CPU_LLSC;
1473 c->tlbsize = 48;
1474 break;
1475 case PRID_IMP_TX49:
1476 c->cputype = CPU_TX49XX;
1477 __cpu_name[cpu] = "R49XX";
1478 set_isa(c, MIPS_CPU_ISA_III);
1479 c->fpu_msk31 |= FPU_CSR_CONDX;
1480 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1481 if (!(c->processor_id & 0x08))
1482 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1483 c->tlbsize = 48;
1484 break;
1485 case PRID_IMP_R5000:
1486 c->cputype = CPU_R5000;
1487 __cpu_name[cpu] = "R5000";
1488 set_isa(c, MIPS_CPU_ISA_IV);
1489 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1490 MIPS_CPU_LLSC;
1491 c->tlbsize = 48;
1492 break;
1493 case PRID_IMP_R5500:
1494 c->cputype = CPU_R5500;
1495 __cpu_name[cpu] = "R5500";
1496 set_isa(c, MIPS_CPU_ISA_IV);
1497 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1498 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1499 c->tlbsize = 48;
1500 break;
1501 case PRID_IMP_NEVADA:
1502 c->cputype = CPU_NEVADA;
1503 __cpu_name[cpu] = "Nevada";
1504 set_isa(c, MIPS_CPU_ISA_IV);
1505 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1506 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1507 c->tlbsize = 48;
1508 break;
1509 case PRID_IMP_RM7000:
1510 c->cputype = CPU_RM7000;
1511 __cpu_name[cpu] = "RM7000";
1512 set_isa(c, MIPS_CPU_ISA_IV);
1513 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1514 MIPS_CPU_LLSC;
1516 * Undocumented RM7000: Bit 29 in the info register of
1517 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1518 * entries.
1520 * 29 1 => 64 entry JTLB
1521 * 0 => 48 entry JTLB
1523 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1524 break;
1525 case PRID_IMP_R10000:
1526 c->cputype = CPU_R10000;
1527 __cpu_name[cpu] = "R10000";
1528 set_isa(c, MIPS_CPU_ISA_IV);
1529 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1530 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1531 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1532 MIPS_CPU_LLSC;
1533 c->tlbsize = 64;
1534 break;
1535 case PRID_IMP_R12000:
1536 c->cputype = CPU_R12000;
1537 __cpu_name[cpu] = "R12000";
1538 set_isa(c, MIPS_CPU_ISA_IV);
1539 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1540 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1541 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1542 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1543 c->tlbsize = 64;
1544 break;
1545 case PRID_IMP_R14000:
1546 if (((c->processor_id >> 4) & 0x0f) > 2) {
1547 c->cputype = CPU_R16000;
1548 __cpu_name[cpu] = "R16000";
1549 } else {
1550 c->cputype = CPU_R14000;
1551 __cpu_name[cpu] = "R14000";
1553 set_isa(c, MIPS_CPU_ISA_IV);
1554 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1555 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1556 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1557 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1558 c->tlbsize = 64;
1559 break;
1560 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1561 switch (c->processor_id & PRID_REV_MASK) {
1562 case PRID_REV_LOONGSON2E:
1563 c->cputype = CPU_LOONGSON2EF;
1564 __cpu_name[cpu] = "ICT Loongson-2";
1565 set_elf_platform(cpu, "loongson2e");
1566 set_isa(c, MIPS_CPU_ISA_III);
1567 c->fpu_msk31 |= FPU_CSR_CONDX;
1568 break;
1569 case PRID_REV_LOONGSON2F:
1570 c->cputype = CPU_LOONGSON2EF;
1571 __cpu_name[cpu] = "ICT Loongson-2";
1572 set_elf_platform(cpu, "loongson2f");
1573 set_isa(c, MIPS_CPU_ISA_III);
1574 c->fpu_msk31 |= FPU_CSR_CONDX;
1575 break;
1576 case PRID_REV_LOONGSON3A_R1:
1577 c->cputype = CPU_LOONGSON64;
1578 __cpu_name[cpu] = "ICT Loongson-3";
1579 set_elf_platform(cpu, "loongson3a");
1580 set_isa(c, MIPS_CPU_ISA_M64R1);
1581 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1582 MIPS_ASE_LOONGSON_EXT);
1583 break;
1584 case PRID_REV_LOONGSON3B_R1:
1585 case PRID_REV_LOONGSON3B_R2:
1586 c->cputype = CPU_LOONGSON64;
1587 __cpu_name[cpu] = "ICT Loongson-3";
1588 set_elf_platform(cpu, "loongson3b");
1589 set_isa(c, MIPS_CPU_ISA_M64R1);
1590 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1591 MIPS_ASE_LOONGSON_EXT);
1592 break;
1595 c->options = R4K_OPTS |
1596 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1597 MIPS_CPU_32FPR;
1598 c->tlbsize = 64;
1599 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1600 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1601 break;
1602 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1603 decode_configs(c);
1605 c->cputype = CPU_LOONGSON32;
1607 switch (c->processor_id & PRID_REV_MASK) {
1608 case PRID_REV_LOONGSON1B:
1609 __cpu_name[cpu] = "Loongson 1B";
1610 break;
1613 break;
1617 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1619 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1620 switch (c->processor_id & PRID_IMP_MASK) {
1621 case PRID_IMP_QEMU_GENERIC:
1622 c->writecombine = _CACHE_UNCACHED;
1623 c->cputype = CPU_QEMU_GENERIC;
1624 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1625 break;
1626 case PRID_IMP_4KC:
1627 c->cputype = CPU_4KC;
1628 c->writecombine = _CACHE_UNCACHED;
1629 __cpu_name[cpu] = "MIPS 4Kc";
1630 break;
1631 case PRID_IMP_4KEC:
1632 case PRID_IMP_4KECR2:
1633 c->cputype = CPU_4KEC;
1634 c->writecombine = _CACHE_UNCACHED;
1635 __cpu_name[cpu] = "MIPS 4KEc";
1636 break;
1637 case PRID_IMP_4KSC:
1638 case PRID_IMP_4KSD:
1639 c->cputype = CPU_4KSC;
1640 c->writecombine = _CACHE_UNCACHED;
1641 __cpu_name[cpu] = "MIPS 4KSc";
1642 break;
1643 case PRID_IMP_5KC:
1644 c->cputype = CPU_5KC;
1645 c->writecombine = _CACHE_UNCACHED;
1646 __cpu_name[cpu] = "MIPS 5Kc";
1647 break;
1648 case PRID_IMP_5KE:
1649 c->cputype = CPU_5KE;
1650 c->writecombine = _CACHE_UNCACHED;
1651 __cpu_name[cpu] = "MIPS 5KE";
1652 break;
1653 case PRID_IMP_20KC:
1654 c->cputype = CPU_20KC;
1655 c->writecombine = _CACHE_UNCACHED;
1656 __cpu_name[cpu] = "MIPS 20Kc";
1657 break;
1658 case PRID_IMP_24K:
1659 c->cputype = CPU_24K;
1660 c->writecombine = _CACHE_UNCACHED;
1661 __cpu_name[cpu] = "MIPS 24Kc";
1662 break;
1663 case PRID_IMP_24KE:
1664 c->cputype = CPU_24K;
1665 c->writecombine = _CACHE_UNCACHED;
1666 __cpu_name[cpu] = "MIPS 24KEc";
1667 break;
1668 case PRID_IMP_25KF:
1669 c->cputype = CPU_25KF;
1670 c->writecombine = _CACHE_UNCACHED;
1671 __cpu_name[cpu] = "MIPS 25Kc";
1672 break;
1673 case PRID_IMP_34K:
1674 c->cputype = CPU_34K;
1675 c->writecombine = _CACHE_UNCACHED;
1676 __cpu_name[cpu] = "MIPS 34Kc";
1677 cpu_set_mt_per_tc_perf(c);
1678 break;
1679 case PRID_IMP_74K:
1680 c->cputype = CPU_74K;
1681 c->writecombine = _CACHE_UNCACHED;
1682 __cpu_name[cpu] = "MIPS 74Kc";
1683 break;
1684 case PRID_IMP_M14KC:
1685 c->cputype = CPU_M14KC;
1686 c->writecombine = _CACHE_UNCACHED;
1687 __cpu_name[cpu] = "MIPS M14Kc";
1688 break;
1689 case PRID_IMP_M14KEC:
1690 c->cputype = CPU_M14KEC;
1691 c->writecombine = _CACHE_UNCACHED;
1692 __cpu_name[cpu] = "MIPS M14KEc";
1693 break;
1694 case PRID_IMP_1004K:
1695 c->cputype = CPU_1004K;
1696 c->writecombine = _CACHE_UNCACHED;
1697 __cpu_name[cpu] = "MIPS 1004Kc";
1698 cpu_set_mt_per_tc_perf(c);
1699 break;
1700 case PRID_IMP_1074K:
1701 c->cputype = CPU_1074K;
1702 c->writecombine = _CACHE_UNCACHED;
1703 __cpu_name[cpu] = "MIPS 1074Kc";
1704 break;
1705 case PRID_IMP_INTERAPTIV_UP:
1706 c->cputype = CPU_INTERAPTIV;
1707 __cpu_name[cpu] = "MIPS interAptiv";
1708 cpu_set_mt_per_tc_perf(c);
1709 break;
1710 case PRID_IMP_INTERAPTIV_MP:
1711 c->cputype = CPU_INTERAPTIV;
1712 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1713 cpu_set_mt_per_tc_perf(c);
1714 break;
1715 case PRID_IMP_PROAPTIV_UP:
1716 c->cputype = CPU_PROAPTIV;
1717 __cpu_name[cpu] = "MIPS proAptiv";
1718 break;
1719 case PRID_IMP_PROAPTIV_MP:
1720 c->cputype = CPU_PROAPTIV;
1721 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1722 break;
1723 case PRID_IMP_P5600:
1724 c->cputype = CPU_P5600;
1725 __cpu_name[cpu] = "MIPS P5600";
1726 break;
1727 case PRID_IMP_P6600:
1728 c->cputype = CPU_P6600;
1729 __cpu_name[cpu] = "MIPS P6600";
1730 break;
1731 case PRID_IMP_I6400:
1732 c->cputype = CPU_I6400;
1733 __cpu_name[cpu] = "MIPS I6400";
1734 break;
1735 case PRID_IMP_I6500:
1736 c->cputype = CPU_I6500;
1737 __cpu_name[cpu] = "MIPS I6500";
1738 break;
1739 case PRID_IMP_M5150:
1740 c->cputype = CPU_M5150;
1741 __cpu_name[cpu] = "MIPS M5150";
1742 break;
1743 case PRID_IMP_M6250:
1744 c->cputype = CPU_M6250;
1745 __cpu_name[cpu] = "MIPS M6250";
1746 break;
1749 decode_configs(c);
1751 spram_config();
1753 switch (__get_cpu_type(c->cputype)) {
1754 case CPU_I6500:
1755 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1756 /* fall-through */
1757 case CPU_I6400:
1758 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1759 /* fall-through */
1760 default:
1761 break;
1765 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1767 decode_configs(c);
1768 switch (c->processor_id & PRID_IMP_MASK) {
1769 case PRID_IMP_AU1_REV1:
1770 case PRID_IMP_AU1_REV2:
1771 c->cputype = CPU_ALCHEMY;
1772 switch ((c->processor_id >> 24) & 0xff) {
1773 case 0:
1774 __cpu_name[cpu] = "Au1000";
1775 break;
1776 case 1:
1777 __cpu_name[cpu] = "Au1500";
1778 break;
1779 case 2:
1780 __cpu_name[cpu] = "Au1100";
1781 break;
1782 case 3:
1783 __cpu_name[cpu] = "Au1550";
1784 break;
1785 case 4:
1786 __cpu_name[cpu] = "Au1200";
1787 if ((c->processor_id & PRID_REV_MASK) == 2)
1788 __cpu_name[cpu] = "Au1250";
1789 break;
1790 case 5:
1791 __cpu_name[cpu] = "Au1210";
1792 break;
1793 default:
1794 __cpu_name[cpu] = "Au1xxx";
1795 break;
1797 break;
1801 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1803 decode_configs(c);
1805 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1806 switch (c->processor_id & PRID_IMP_MASK) {
1807 case PRID_IMP_SB1:
1808 c->cputype = CPU_SB1;
1809 __cpu_name[cpu] = "SiByte SB1";
1810 /* FPU in pass1 is known to have issues. */
1811 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1812 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1813 break;
1814 case PRID_IMP_SB1A:
1815 c->cputype = CPU_SB1A;
1816 __cpu_name[cpu] = "SiByte SB1A";
1817 break;
1821 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1823 decode_configs(c);
1824 switch (c->processor_id & PRID_IMP_MASK) {
1825 case PRID_IMP_SR71000:
1826 c->cputype = CPU_SR71000;
1827 __cpu_name[cpu] = "Sandcraft SR71000";
1828 c->scache.ways = 8;
1829 c->tlbsize = 64;
1830 break;
1834 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1836 decode_configs(c);
1837 switch (c->processor_id & PRID_IMP_MASK) {
1838 case PRID_IMP_PR4450:
1839 c->cputype = CPU_PR4450;
1840 __cpu_name[cpu] = "Philips PR4450";
1841 set_isa(c, MIPS_CPU_ISA_M32R1);
1842 break;
1846 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1848 decode_configs(c);
1849 switch (c->processor_id & PRID_IMP_MASK) {
1850 case PRID_IMP_BMIPS32_REV4:
1851 case PRID_IMP_BMIPS32_REV8:
1852 c->cputype = CPU_BMIPS32;
1853 __cpu_name[cpu] = "Broadcom BMIPS32";
1854 set_elf_platform(cpu, "bmips32");
1855 break;
1856 case PRID_IMP_BMIPS3300:
1857 case PRID_IMP_BMIPS3300_ALT:
1858 case PRID_IMP_BMIPS3300_BUG:
1859 c->cputype = CPU_BMIPS3300;
1860 __cpu_name[cpu] = "Broadcom BMIPS3300";
1861 set_elf_platform(cpu, "bmips3300");
1862 break;
1863 case PRID_IMP_BMIPS43XX: {
1864 int rev = c->processor_id & PRID_REV_MASK;
1866 if (rev >= PRID_REV_BMIPS4380_LO &&
1867 rev <= PRID_REV_BMIPS4380_HI) {
1868 c->cputype = CPU_BMIPS4380;
1869 __cpu_name[cpu] = "Broadcom BMIPS4380";
1870 set_elf_platform(cpu, "bmips4380");
1871 c->options |= MIPS_CPU_RIXI;
1872 } else {
1873 c->cputype = CPU_BMIPS4350;
1874 __cpu_name[cpu] = "Broadcom BMIPS4350";
1875 set_elf_platform(cpu, "bmips4350");
1877 break;
1879 case PRID_IMP_BMIPS5000:
1880 case PRID_IMP_BMIPS5200:
1881 c->cputype = CPU_BMIPS5000;
1882 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1883 __cpu_name[cpu] = "Broadcom BMIPS5200";
1884 else
1885 __cpu_name[cpu] = "Broadcom BMIPS5000";
1886 set_elf_platform(cpu, "bmips5000");
1887 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1888 break;
1892 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1894 decode_configs(c);
1895 switch (c->processor_id & PRID_IMP_MASK) {
1896 case PRID_IMP_CAVIUM_CN38XX:
1897 case PRID_IMP_CAVIUM_CN31XX:
1898 case PRID_IMP_CAVIUM_CN30XX:
1899 c->cputype = CPU_CAVIUM_OCTEON;
1900 __cpu_name[cpu] = "Cavium Octeon";
1901 goto platform;
1902 case PRID_IMP_CAVIUM_CN58XX:
1903 case PRID_IMP_CAVIUM_CN56XX:
1904 case PRID_IMP_CAVIUM_CN50XX:
1905 case PRID_IMP_CAVIUM_CN52XX:
1906 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1907 __cpu_name[cpu] = "Cavium Octeon+";
1908 platform:
1909 set_elf_platform(cpu, "octeon");
1910 break;
1911 case PRID_IMP_CAVIUM_CN61XX:
1912 case PRID_IMP_CAVIUM_CN63XX:
1913 case PRID_IMP_CAVIUM_CN66XX:
1914 case PRID_IMP_CAVIUM_CN68XX:
1915 case PRID_IMP_CAVIUM_CNF71XX:
1916 c->cputype = CPU_CAVIUM_OCTEON2;
1917 __cpu_name[cpu] = "Cavium Octeon II";
1918 set_elf_platform(cpu, "octeon2");
1919 break;
1920 case PRID_IMP_CAVIUM_CN70XX:
1921 case PRID_IMP_CAVIUM_CN73XX:
1922 case PRID_IMP_CAVIUM_CNF75XX:
1923 case PRID_IMP_CAVIUM_CN78XX:
1924 c->cputype = CPU_CAVIUM_OCTEON3;
1925 __cpu_name[cpu] = "Cavium Octeon III";
1926 set_elf_platform(cpu, "octeon3");
1927 break;
1928 default:
1929 printk(KERN_INFO "Unknown Octeon chip!\n");
1930 c->cputype = CPU_UNKNOWN;
1931 break;
1935 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1937 switch (c->processor_id & PRID_IMP_MASK) {
1938 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1939 switch (c->processor_id & PRID_REV_MASK) {
1940 case PRID_REV_LOONGSON3A_R2_0:
1941 case PRID_REV_LOONGSON3A_R2_1:
1942 c->cputype = CPU_LOONGSON64;
1943 __cpu_name[cpu] = "ICT Loongson-3";
1944 set_elf_platform(cpu, "loongson3a");
1945 set_isa(c, MIPS_CPU_ISA_M64R2);
1946 break;
1947 case PRID_REV_LOONGSON3A_R3_0:
1948 case PRID_REV_LOONGSON3A_R3_1:
1949 c->cputype = CPU_LOONGSON64;
1950 __cpu_name[cpu] = "ICT Loongson-3";
1951 set_elf_platform(cpu, "loongson3a");
1952 set_isa(c, MIPS_CPU_ISA_M64R2);
1953 break;
1956 decode_configs(c);
1957 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1958 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1959 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1960 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1961 break;
1962 case PRID_IMP_LOONGSON_64G:
1963 c->cputype = CPU_LOONGSON64;
1964 __cpu_name[cpu] = "ICT Loongson-3";
1965 set_elf_platform(cpu, "loongson3a");
1966 set_isa(c, MIPS_CPU_ISA_M64R2);
1967 decode_configs(c);
1968 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1969 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1970 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1971 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1972 break;
1973 default:
1974 panic("Unknown Loongson Processor ID!");
1975 break;
1979 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1981 decode_configs(c);
1984 * XBurst misses a config2 register, so config3 decode was skipped in
1985 * decode_configs().
1987 decode_config3(c);
1989 /* XBurst does not implement the CP0 counter. */
1990 c->options &= ~MIPS_CPU_COUNTER;
1991 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1993 switch (c->processor_id & PRID_IMP_MASK) {
1994 case PRID_IMP_XBURST_REV1:
1997 * The XBurst core by default attempts to avoid branch target
1998 * buffer lookups by detecting & special casing loops. This
1999 * feature will cause BogoMIPS and lpj calculate in error.
2000 * Set cp0 config7 bit 4 to disable this feature.
2002 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
2004 switch (c->processor_id & PRID_COMP_MASK) {
2007 * The config0 register in the XBurst CPUs with a processor ID of
2008 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
2009 * but they don't actually support this ISA.
2011 case PRID_COMP_INGENIC_D0:
2012 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
2013 break;
2016 * The config0 register in the XBurst CPUs with a processor ID of
2017 * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
2018 * mode is not compatible with the MIPS standard, it will cause
2019 * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
2020 * when starting the init process. After chip reset, the default
2021 * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
2022 * switch back to VTLB mode to prevent getting stuck.
2024 case PRID_COMP_INGENIC_D1:
2025 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
2026 break;
2028 default:
2029 break;
2031 /* fall-through */
2032 case PRID_IMP_XBURST_REV2:
2033 c->cputype = CPU_XBURST;
2034 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2035 __cpu_name[cpu] = "Ingenic XBurst";
2036 break;
2038 default:
2039 panic("Unknown Ingenic Processor ID!");
2040 break;
2044 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
2046 decode_configs(c);
2048 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
2049 c->cputype = CPU_ALCHEMY;
2050 __cpu_name[cpu] = "Au1300";
2051 /* following stuff is not for Alchemy */
2052 return;
2055 c->options = (MIPS_CPU_TLB |
2056 MIPS_CPU_4KEX |
2057 MIPS_CPU_COUNTER |
2058 MIPS_CPU_DIVEC |
2059 MIPS_CPU_WATCH |
2060 MIPS_CPU_EJTAG |
2061 MIPS_CPU_LLSC);
2063 switch (c->processor_id & PRID_IMP_MASK) {
2064 case PRID_IMP_NETLOGIC_XLP2XX:
2065 case PRID_IMP_NETLOGIC_XLP9XX:
2066 case PRID_IMP_NETLOGIC_XLP5XX:
2067 c->cputype = CPU_XLP;
2068 __cpu_name[cpu] = "Broadcom XLPII";
2069 break;
2071 case PRID_IMP_NETLOGIC_XLP8XX:
2072 case PRID_IMP_NETLOGIC_XLP3XX:
2073 c->cputype = CPU_XLP;
2074 __cpu_name[cpu] = "Netlogic XLP";
2075 break;
2077 case PRID_IMP_NETLOGIC_XLR732:
2078 case PRID_IMP_NETLOGIC_XLR716:
2079 case PRID_IMP_NETLOGIC_XLR532:
2080 case PRID_IMP_NETLOGIC_XLR308:
2081 case PRID_IMP_NETLOGIC_XLR532C:
2082 case PRID_IMP_NETLOGIC_XLR516C:
2083 case PRID_IMP_NETLOGIC_XLR508C:
2084 case PRID_IMP_NETLOGIC_XLR308C:
2085 c->cputype = CPU_XLR;
2086 __cpu_name[cpu] = "Netlogic XLR";
2087 break;
2089 case PRID_IMP_NETLOGIC_XLS608:
2090 case PRID_IMP_NETLOGIC_XLS408:
2091 case PRID_IMP_NETLOGIC_XLS404:
2092 case PRID_IMP_NETLOGIC_XLS208:
2093 case PRID_IMP_NETLOGIC_XLS204:
2094 case PRID_IMP_NETLOGIC_XLS108:
2095 case PRID_IMP_NETLOGIC_XLS104:
2096 case PRID_IMP_NETLOGIC_XLS616B:
2097 case PRID_IMP_NETLOGIC_XLS608B:
2098 case PRID_IMP_NETLOGIC_XLS416B:
2099 case PRID_IMP_NETLOGIC_XLS412B:
2100 case PRID_IMP_NETLOGIC_XLS408B:
2101 case PRID_IMP_NETLOGIC_XLS404B:
2102 c->cputype = CPU_XLR;
2103 __cpu_name[cpu] = "Netlogic XLS";
2104 break;
2106 default:
2107 pr_info("Unknown Netlogic chip id [%02x]!\n",
2108 c->processor_id);
2109 c->cputype = CPU_XLR;
2110 break;
2113 if (c->cputype == CPU_XLP) {
2114 set_isa(c, MIPS_CPU_ISA_M64R2);
2115 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
2116 /* This will be updated again after all threads are woken up */
2117 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2118 } else {
2119 set_isa(c, MIPS_CPU_ISA_M64R1);
2120 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2122 c->kscratch_mask = 0xf;
2125 #ifdef CONFIG_64BIT
2126 /* For use by uaccess.h */
2127 u64 __ua_limit;
2128 EXPORT_SYMBOL(__ua_limit);
2129 #endif
2131 const char *__cpu_name[NR_CPUS];
2132 const char *__elf_platform;
2133 const char *__elf_base_platform;
2135 void cpu_probe(void)
2137 struct cpuinfo_mips *c = &current_cpu_data;
2138 unsigned int cpu = smp_processor_id();
2141 * Set a default elf platform, cpu probe may later
2142 * overwrite it with a more precise value
2144 set_elf_platform(cpu, "mips");
2146 c->processor_id = PRID_IMP_UNKNOWN;
2147 c->fpu_id = FPIR_IMP_NONE;
2148 c->cputype = CPU_UNKNOWN;
2149 c->writecombine = _CACHE_UNCACHED;
2151 c->fpu_csr31 = FPU_CSR_RN;
2152 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2154 c->processor_id = read_c0_prid();
2155 switch (c->processor_id & PRID_COMP_MASK) {
2156 case PRID_COMP_LEGACY:
2157 cpu_probe_legacy(c, cpu);
2158 break;
2159 case PRID_COMP_MIPS:
2160 cpu_probe_mips(c, cpu);
2161 break;
2162 case PRID_COMP_ALCHEMY:
2163 cpu_probe_alchemy(c, cpu);
2164 break;
2165 case PRID_COMP_SIBYTE:
2166 cpu_probe_sibyte(c, cpu);
2167 break;
2168 case PRID_COMP_BROADCOM:
2169 cpu_probe_broadcom(c, cpu);
2170 break;
2171 case PRID_COMP_SANDCRAFT:
2172 cpu_probe_sandcraft(c, cpu);
2173 break;
2174 case PRID_COMP_NXP:
2175 cpu_probe_nxp(c, cpu);
2176 break;
2177 case PRID_COMP_CAVIUM:
2178 cpu_probe_cavium(c, cpu);
2179 break;
2180 case PRID_COMP_LOONGSON:
2181 cpu_probe_loongson(c, cpu);
2182 break;
2183 case PRID_COMP_INGENIC_D0:
2184 case PRID_COMP_INGENIC_D1:
2185 case PRID_COMP_INGENIC_E1:
2186 cpu_probe_ingenic(c, cpu);
2187 break;
2188 case PRID_COMP_NETLOGIC:
2189 cpu_probe_netlogic(c, cpu);
2190 break;
2193 BUG_ON(!__cpu_name[cpu]);
2194 BUG_ON(c->cputype == CPU_UNKNOWN);
2197 * Platform code can force the cpu type to optimize code
2198 * generation. In that case be sure the cpu type is correctly
2199 * manually setup otherwise it could trigger some nasty bugs.
2201 BUG_ON(current_cpu_type() != c->cputype);
2203 if (cpu_has_rixi) {
2204 /* Enable the RIXI exceptions */
2205 set_c0_pagegrain(PG_IEC);
2206 back_to_back_c0_hazard();
2207 /* Verify the IEC bit is set */
2208 if (read_c0_pagegrain() & PG_IEC)
2209 c->options |= MIPS_CPU_RIXIEX;
2212 if (mips_fpu_disabled)
2213 c->options &= ~MIPS_CPU_FPU;
2215 if (mips_dsp_disabled)
2216 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2218 if (mips_htw_disabled) {
2219 c->options &= ~MIPS_CPU_HTW;
2220 write_c0_pwctl(read_c0_pwctl() &
2221 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2224 if (c->options & MIPS_CPU_FPU)
2225 cpu_set_fpu_opts(c);
2226 else
2227 cpu_set_nofpu_opts(c);
2229 if (cpu_has_bp_ghist)
2230 write_c0_r10k_diag(read_c0_r10k_diag() |
2231 R10K_DIAG_E_GHIST);
2233 if (cpu_has_mips_r2_r6) {
2234 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2235 /* R2 has Performance Counter Interrupt indicator */
2236 c->options |= MIPS_CPU_PCI;
2238 else
2239 c->srsets = 1;
2241 if (cpu_has_mips_r6)
2242 elf_hwcap |= HWCAP_MIPS_R6;
2244 if (cpu_has_msa) {
2245 c->msa_id = cpu_get_msa_id();
2246 WARN(c->msa_id & MSA_IR_WRPF,
2247 "Vector register partitioning unimplemented!");
2248 elf_hwcap |= HWCAP_MIPS_MSA;
2251 if (cpu_has_mips16)
2252 elf_hwcap |= HWCAP_MIPS_MIPS16;
2254 if (cpu_has_mdmx)
2255 elf_hwcap |= HWCAP_MIPS_MDMX;
2257 if (cpu_has_mips3d)
2258 elf_hwcap |= HWCAP_MIPS_MIPS3D;
2260 if (cpu_has_smartmips)
2261 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
2263 if (cpu_has_dsp)
2264 elf_hwcap |= HWCAP_MIPS_DSP;
2266 if (cpu_has_dsp2)
2267 elf_hwcap |= HWCAP_MIPS_DSP2;
2269 if (cpu_has_dsp3)
2270 elf_hwcap |= HWCAP_MIPS_DSP3;
2272 if (cpu_has_mips16e2)
2273 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
2275 if (cpu_has_loongson_mmi)
2276 elf_hwcap |= HWCAP_LOONGSON_MMI;
2278 if (cpu_has_loongson_ext)
2279 elf_hwcap |= HWCAP_LOONGSON_EXT;
2281 if (cpu_has_loongson_ext2)
2282 elf_hwcap |= HWCAP_LOONGSON_EXT2;
2284 if (cpu_has_vz)
2285 cpu_probe_vz(c);
2287 cpu_probe_vmbits(c);
2289 #ifdef CONFIG_64BIT
2290 if (cpu == 0)
2291 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2292 #endif
2295 void cpu_report(void)
2297 struct cpuinfo_mips *c = &current_cpu_data;
2299 pr_info("CPU%d revision is: %08x (%s)\n",
2300 smp_processor_id(), c->processor_id, cpu_name_string());
2301 if (c->options & MIPS_CPU_FPU)
2302 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2303 if (cpu_has_msa)
2304 pr_info("MSA revision is: %08x\n", c->msa_id);
2307 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2309 /* Ensure the core number fits in the field */
2310 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2311 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2313 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2314 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2317 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2319 /* Ensure the core number fits in the field */
2320 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2322 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2323 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2326 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2328 /* Ensure the VP(E) ID fits in the field */
2329 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2331 /* Ensure we're not using VP(E)s without support */
2332 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2333 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2335 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2336 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;