4 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/interrupt.h>
15 #include <linux/ptrace.h>
16 #include <linux/time.h>
18 #include <asm/irq_cpu.h>
19 #include <asm/setup.h>
23 /* SLP bases systems */
24 extern void msp_slp_irq_init(void);
25 extern void msp_slp_irq_dispatch(void);
27 /* CIC based systems */
28 extern void msp_cic_irq_init(void);
29 extern void msp_cic_irq_dispatch(void);
31 /* VSMP support init */
32 extern void msp_vsmp_int_init(void);
34 /* vectored interrupt implementation */
36 /* SW0/1 interrupts are used for SMP */
37 static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0
); }
38 static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1
); }
39 static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR
); }
40 static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB
); }
41 static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC
); }
44 * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
45 * hierarchical system. The first level are the direct MIPS interrupts
46 * and are assigned the interrupt range 0-7. The second level is the SLM
47 * interrupt controller and is assigned the range 8-39. The third level
48 * comprises the Peripherial block, the PCI block, the PCI MSI block and
49 * the SLP. The PCI interrupts and the SLP errors are handled by the
50 * relevant subsystems so the core interrupt code needs only concern
51 * itself with the Peripheral block. These are assigned interrupts in
55 asmlinkage
void plat_irq_dispatch(void)
59 pending
= read_c0_status() & read_c0_cause();
62 * jump to the correct interrupt routine
63 * These are arranged in priority order and the timer
67 #ifdef CONFIG_IRQ_MSP_CIC /* break out the CIC stuff for now */
68 if (pending
& C_IRQ4
) /* do the peripherals first, that's the timer */
69 msp_cic_irq_dispatch();
71 else if (pending
& C_IRQ0
)
74 else if (pending
& C_IRQ1
)
77 else if (pending
& C_IRQ2
)
80 else if (pending
& C_IRQ3
)
83 else if (pending
& C_IRQ5
)
88 do_IRQ(MSP_INT_TIMER
);
90 else if (pending
& C_IRQ0
)
93 else if (pending
& C_IRQ1
)
96 else if (pending
& C_IRQ3
)
99 else if (pending
& C_IRQ4
)
100 msp_slp_irq_dispatch();
103 else if (pending
& C_SW0
) /* do software after hardware */
106 else if (pending
& C_SW1
)
110 void __init
arch_init_irq(void)
112 /* assume we'll be using vectored interrupt mode except in UP mode*/
113 #ifdef CONFIG_MIPS_MT
114 BUG_ON(!cpu_has_vint
);
116 /* initialize the 1st-level CPU based interrupt controller */
119 #ifdef CONFIG_IRQ_MSP_CIC
121 #ifdef CONFIG_MIPS_MT
122 set_vi_handler(MSP_INT_CIC
, msp_cic_irq_dispatch
);
123 set_vi_handler(MSP_INT_MAC0
, mac0_int_dispatch
);
124 set_vi_handler(MSP_INT_MAC1
, mac1_int_dispatch
);
125 set_vi_handler(MSP_INT_SAR
, mac2_int_dispatch
);
126 set_vi_handler(MSP_INT_USB
, usb_int_dispatch
);
127 set_vi_handler(MSP_INT_SEC
, sec_int_dispatch
);
128 #ifdef CONFIG_MIPS_MT_SMP
130 #endif /* CONFIG_MIPS_MT_SMP */
131 #endif /* CONFIG_MIPS_MT */
132 /* setup the cascaded interrupts */
133 if (request_irq(MSP_INT_CIC
, no_action
, IRQF_NO_THREAD
,
134 "MSP CIC cascade", NULL
))
135 pr_err("Failed to register MSP CIC cascade interrupt\n");
136 if (request_irq(MSP_INT_PER
, no_action
, IRQF_NO_THREAD
,
137 "MSP PER cascade", NULL
))
138 pr_err("Failed to register MSP PER cascade interrupt\n");
142 * Setup the 2nd-level SLP register based interrupt controller.
143 * VSMP support support is not enabled for SLP.
147 /* setup the cascaded SLP/PER interrupts */
148 if (request_irq(MSP_INT_SLP
, no_action
, IRQF_NO_THREAD
,
149 "MSP CIC cascade", NULL
))
150 pr_err("Failed to register MSP CIC cascade interrupt\n");
151 if (request_irq(MSP_INT_PER
, no_action
, IRQF_NO_THREAD
,
152 "MSP PER cascade", NULL
))
153 pr_err("Failed to register MSP PER cascade interrupt\n");