drivers/clk/renesas/clk-mstp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * R-Car MSTP clocks
   4  *
   5  * Copyright (C) 2013 Ideas On Board SPRL
   6  * Copyright (C) 2015 Glider bvba
   7  *
   8  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk/renesas.h>
  15 #include <linux/device.h>
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/pm_clock.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/spinlock.h>
  22
  23 /*
  24  * MSTP clocks. We can't use standard gate clocks as we need to poll on the
  25  * status register when enabling the clock.
  26  */
  27
  28 #define MSTP_MAX_CLOCKS         32
  29
  30 /**
  31  * struct mstp_clock_group - MSTP gating clocks group
  32  *
  33  * @data: clocks in this group
  34  * @smstpcr: module stop control register
  35  * @mstpsr: module stop status register (optional)
  36  * @lock: protects writes to SMSTPCR
  37  * @width_8bit: registers are 8-bit, not 32-bit
  38  */
  39 struct mstp_clock_group {
  40         struct clk_onecell_data data;
  41         void __iomem *smstpcr;
  42         void __iomem *mstpsr;
  43         spinlock_t lock;
  44         bool width_8bit;
  45 };
  46
  47 /**
  48  * struct mstp_clock - MSTP gating clock
  49  * @hw: handle between common and hardware-specific interfaces
  50  * @bit_index: control bit index
  51  * @group: MSTP clocks group
  52  */
  53 struct mstp_clock {
  54         struct clk_hw hw;
  55         u32 bit_index;
  56         struct mstp_clock_group *group;
  57 };
  58
  59 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
  60
  61 static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
  62                                 u32 __iomem *reg)
  63 {
  64         return group->width_8bit ? readb(reg) : readl(reg);
  65 }
  66
  67 static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
  68                                   u32 __iomem *reg)
  69 {
  70         group->width_8bit ? writeb(val, reg) : writel(val, reg);
  71 }
  72
  73 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
  74 {
  75         struct mstp_clock *clock = to_mstp_clock(hw);
  76         struct mstp_clock_group *group = clock->group;
  77         u32 bitmask = BIT(clock->bit_index);
  78         unsigned long flags;
  79         unsigned int i;
  80         u32 value;
  81
  82         spin_lock_irqsave(&group->lock, flags);
  83
  84         value = cpg_mstp_read(group, group->smstpcr);
  85         if (enable)
  86                 value &= ~bitmask;
  87         else
  88                 value |= bitmask;
  89         cpg_mstp_write(group, value, group->smstpcr);
  90
  91         if (!group->mstpsr) {
  92                 /* dummy read to ensure write has completed */
  93                 cpg_mstp_read(group, group->smstpcr);
  94                 barrier_data(group->smstpcr);
  95         }
  96
  97         spin_unlock_irqrestore(&group->lock, flags);
  98
  99         if (!enable || !group->mstpsr)
 100                 return 0;
 101
 102         for (i = 1000; i > 0; --i) {
 103                 if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
 104                         break;
 105                 cpu_relax();
 106         }
 107
 108         if (!i) {
 109                 pr_err("%s: failed to enable %p[%d]\n", __func__,
 110                        group->smstpcr, clock->bit_index);
 111                 return -ETIMEDOUT;
 112         }
 113
 114         return 0;
 115 }
 116
 117 static int cpg_mstp_clock_enable(struct clk_hw *hw)
 118 {
 119         return cpg_mstp_clock_endisable(hw, true);
 120 }
 121
 122 static void cpg_mstp_clock_disable(struct clk_hw *hw)
 123 {
 124         cpg_mstp_clock_endisable(hw, false);
 125 }
 126
 127 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
 128 {
 129         struct mstp_clock *clock = to_mstp_clock(hw);
 130         struct mstp_clock_group *group = clock->group;
 131         u32 value;
 132
 133         if (group->mstpsr)
 134                 value = cpg_mstp_read(group, group->mstpsr);
 135         else
 136                 value = cpg_mstp_read(group, group->smstpcr);
 137
 138         return !(value & BIT(clock->bit_index));
 139 }
 140
 141 static const struct clk_ops cpg_mstp_clock_ops = {
 142         .enable = cpg_mstp_clock_enable,
 143         .disable = cpg_mstp_clock_disable,
 144         .is_enabled = cpg_mstp_clock_is_enabled,
 145 };
 146
 147 static struct clk * __init cpg_mstp_clock_register(const char *name,
 148         const char *parent_name, unsigned int index,
 149         struct mstp_clock_group *group)
 150 {
 151         struct clk_init_data init;
 152         struct mstp_clock *clock;
 153         struct clk *clk;
 154
 155         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 156         if (!clock)
 157                 return ERR_PTR(-ENOMEM);
 158
 159         init.name = name;
 160         init.ops = &cpg_mstp_clock_ops;
 161         init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
 162         /* INTC-SYS is the module clock of the GIC, and must not be disabled */
 163         if (!strcmp(name, "intc-sys")) {
 164                 pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
 165                 init.flags |= CLK_IS_CRITICAL;
 166         }
 167         init.parent_names = &parent_name;
 168         init.num_parents = 1;
 169
 170         clock->bit_index = index;
 171         clock->group = group;
 172         clock->hw.init = &init;
 173
 174         clk = clk_register(NULL, &clock->hw);
 175
 176         if (IS_ERR(clk))
 177                 kfree(clock);
 178
 179         return clk;
 180 }
 181
 182 static void __init cpg_mstp_clocks_init(struct device_node *np)
 183 {
 184         struct mstp_clock_group *group;
 185         const char *idxname;
 186         struct clk **clks;
 187         unsigned int i;
 188
 189         group = kzalloc(sizeof(*group), GFP_KERNEL);
 190         clks = kmalloc_array(MSTP_MAX_CLOCKS, sizeof(*clks), GFP_KERNEL);
 191         if (group == NULL || clks == NULL) {
 192                 kfree(group);
 193                 kfree(clks);
 194                 return;
 195         }
 196
 197         spin_lock_init(&group->lock);
 198         group->data.clks = clks;
 199
 200         group->smstpcr = of_iomap(np, 0);
 201         group->mstpsr = of_iomap(np, 1);
 202
 203         if (group->smstpcr == NULL) {
 204                 pr_err("%s: failed to remap SMSTPCR\n", __func__);
 205                 kfree(group);
 206                 kfree(clks);
 207                 return;
 208         }
 209
 210         if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
 211                 group->width_8bit = true;
 212
 213         for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
 214                 clks[i] = ERR_PTR(-ENOENT);
 215
 216         if (of_find_property(np, "clock-indices", &i))
 217                 idxname = "clock-indices";
 218         else
 219                 idxname = "renesas,clock-indices";
 220
 221         for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
 222                 const char *parent_name;
 223                 const char *name;
 224                 u32 clkidx;
 225                 int ret;
 226
 227                 /* Skip clocks with no name. */
 228                 ret = of_property_read_string_index(np, "clock-output-names",
 229                                                     i, &name);
 230                 if (ret < 0 || strlen(name) == 0)
 231                         continue;
 232
 233                 parent_name = of_clk_get_parent_name(np, i);
 234                 ret = of_property_read_u32_index(np, idxname, i, &clkidx);
 235                 if (parent_name == NULL || ret < 0)
 236                         break;
 237
 238                 if (clkidx >= MSTP_MAX_CLOCKS) {
 239                         pr_err("%s: invalid clock %pOFn %s index %u\n",
 240                                __func__, np, name, clkidx);
 241                         continue;
 242                 }
 243
 244                 clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
 245                                                        clkidx, group);
 246                 if (!IS_ERR(clks[clkidx])) {
 247                         group->data.clk_num = max(group->data.clk_num,
 248                                                   clkidx + 1);
 249                         /*
 250                          * Register a clkdev to let board code retrieve the
 251                          * clock by name and register aliases for non-DT
 252                          * devices.
 253                          *
 254                          * FIXME: Remove this when all devices that require a
 255                          * clock will be instantiated from DT.
 256                          */
 257                         clk_register_clkdev(clks[clkidx], name, NULL);
 258                 } else {
 259                         pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
 260                                __func__, np, name, PTR_ERR(clks[clkidx]));
 261                 }
 262         }
 263
 264         of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
 265 }
 266 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
 267
 268 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 269 {
 270         struct device_node *np = dev->of_node;
 271         struct of_phandle_args clkspec;
 272         struct clk *clk;
 273         int i = 0;
 274         int error;
 275
 276         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 277                                            &clkspec)) {
 278                 if (of_device_is_compatible(clkspec.np,
 279                                             "renesas,cpg-mstp-clocks"))
 280                         goto found;
 281
 282                 /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
 283                 if (!strcmp(clkspec.np->name, "zb_clk"))
 284                         goto found;
 285
 286                 of_node_put(clkspec.np);
 287                 i++;
 288         }
 289
 290         return 0;
 291
 292 found:
 293         clk = of_clk_get_from_provider(&clkspec);
 294         of_node_put(clkspec.np);
 295
 296         if (IS_ERR(clk))
 297                 return PTR_ERR(clk);
 298
 299         error = pm_clk_create(dev);
 300         if (error) {
 301                 dev_err(dev, "pm_clk_create failed %d\n", error);
 302                 goto fail_put;
 303         }
 304
 305         error = pm_clk_add_clk(dev, clk);
 306         if (error) {
 307                 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
 308                 goto fail_destroy;
 309         }
 310
 311         return 0;
 312
 313 fail_destroy:
 314         pm_clk_destroy(dev);
 315 fail_put:
 316         clk_put(clk);
 317         return error;
 318 }
 319
 320 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 321 {
 322         if (!pm_clk_no_clocks(dev))
 323                 pm_clk_destroy(dev);
 324 }
 325
 326 void __init cpg_mstp_add_clk_domain(struct device_node *np)
 327 {
 328         struct generic_pm_domain *pd;
 329         u32 ncells;
 330
 331         if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
 332                 pr_warn("%pOF lacks #power-domain-cells\n", np);
 333                 return;
 334         }
 335
 336         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 337         if (!pd)
 338                 return;
 339
 340         pd->name = np->name;
 341         pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
 342         pd->attach_dev = cpg_mstp_attach_dev;
 343         pd->detach_dev = cpg_mstp_detach_dev;
 344         pm_genpd_init(pd, &pm_domain_always_on_gov, false);
 345
 346         of_genpd_add_provider_simple(np, pd);
 347 }