2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Common Clock Framework support for S3C2412 and S3C2413.
11 #include <linux/clk-provider.h>
13 #include <linux/of_address.h>
14 #include <linux/reboot.h>
16 #include <dt-bindings/clock/s3c2412.h>
29 static void __iomem
*reg_base
;
32 * list of controller registers to be saved and restored during a
33 * suspend/resume cycle.
35 static unsigned long s3c2412_clk_regs
[] __initdata
= {
44 static struct clk_div_table divxti_d
[] = {
45 { .val
= 0, .div
= 1 },
46 { .val
= 1, .div
= 2 },
47 { .val
= 2, .div
= 4 },
48 { .val
= 3, .div
= 6 },
49 { .val
= 4, .div
= 8 },
50 { .val
= 5, .div
= 10 },
51 { .val
= 6, .div
= 12 },
52 { .val
= 7, .div
= 14 },
56 static struct samsung_div_clock s3c2412_dividers
[] __initdata
= {
57 DIV_T(0, "div_xti", "xti", CLKSRC
, 0, 3, divxti_d
),
58 DIV(0, "div_cam", "mux_cam", CLKDIVN
, 16, 4),
59 DIV(0, "div_i2s", "mux_i2s", CLKDIVN
, 12, 4),
60 DIV(0, "div_uart", "mux_uart", CLKDIVN
, 8, 4),
61 DIV(0, "div_usb", "mux_usb", CLKDIVN
, 6, 1),
62 DIV(0, "div_hclk_half", "hclk", CLKDIVN
, 5, 1),
63 DIV(ARMDIV
, "armdiv", "msysclk", CLKDIVN
, 3, 1),
64 DIV(PCLK
, "pclk", "hclk", CLKDIVN
, 2, 1),
65 DIV(HCLK
, "hclk", "armdiv", CLKDIVN
, 0, 2),
68 static struct samsung_fixed_factor_clock s3c2412_ffactor
[] __initdata
= {
69 FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT
),
73 * The first two use the OM[4] setting, which is not readable from
74 * software, so assume it is set to xti.
76 PNAME(erefclk_p
) = { "xti", "xti", "xti", "ext" };
77 PNAME(urefclk_p
) = { "xti", "xti", "xti", "ext" };
79 PNAME(camclk_p
) = { "usysclk", "hclk" };
80 PNAME(usbclk_p
) = { "usysclk", "hclk" };
81 PNAME(i2sclk_p
) = { "erefclk", "mpll" };
82 PNAME(uartclk_p
) = { "erefclk", "mpll" };
83 PNAME(usysclk_p
) = { "urefclk", "upll" };
84 PNAME(msysclk_p
) = { "mdivclk", "mpll" };
85 PNAME(mdivclk_p
) = { "xti", "div_xti" };
86 PNAME(armclk_p
) = { "armdiv", "hclk" };
88 static struct samsung_mux_clock s3c2412_muxes
[] __initdata
= {
89 MUX(0, "erefclk", erefclk_p
, CLKSRC
, 14, 2),
90 MUX(0, "urefclk", urefclk_p
, CLKSRC
, 12, 2),
91 MUX(0, "mux_cam", camclk_p
, CLKSRC
, 11, 1),
92 MUX(0, "mux_usb", usbclk_p
, CLKSRC
, 10, 1),
93 MUX(0, "mux_i2s", i2sclk_p
, CLKSRC
, 9, 1),
94 MUX(0, "mux_uart", uartclk_p
, CLKSRC
, 8, 1),
95 MUX(USYSCLK
, "usysclk", usysclk_p
, CLKSRC
, 5, 1),
96 MUX(MSYSCLK
, "msysclk", msysclk_p
, CLKSRC
, 4, 1),
97 MUX(MDIVCLK
, "mdivclk", mdivclk_p
, CLKSRC
, 3, 1),
98 MUX(ARMCLK
, "armclk", armclk_p
, CLKDIVN
, 4, 1),
101 static struct samsung_pll_clock s3c2412_plls
[] __initdata
= {
102 PLL(pll_s3c2440_mpll
, MPLL
, "mpll", "xti", LOCKTIME
, MPLLCON
, NULL
),
103 PLL(pll_s3c2410_upll
, UPLL
, "upll", "urefclk", LOCKTIME
, UPLLCON
, NULL
),
106 static struct samsung_gate_clock s3c2412_gates
[] __initdata
= {
107 GATE(PCLK_WDT
, "wdt", "pclk", CLKCON
, 28, 0, 0),
108 GATE(PCLK_SPI
, "spi", "pclk", CLKCON
, 27, 0, 0),
109 GATE(PCLK_I2S
, "i2s", "pclk", CLKCON
, 26, 0, 0),
110 GATE(PCLK_I2C
, "i2c", "pclk", CLKCON
, 25, 0, 0),
111 GATE(PCLK_ADC
, "adc", "pclk", CLKCON
, 24, 0, 0),
112 GATE(PCLK_RTC
, "rtc", "pclk", CLKCON
, 23, 0, 0),
113 GATE(PCLK_GPIO
, "gpio", "pclk", CLKCON
, 22, CLK_IGNORE_UNUSED
, 0),
114 GATE(PCLK_UART2
, "uart2", "pclk", CLKCON
, 21, 0, 0),
115 GATE(PCLK_UART1
, "uart1", "pclk", CLKCON
, 20, 0, 0),
116 GATE(PCLK_UART0
, "uart0", "pclk", CLKCON
, 19, 0, 0),
117 GATE(PCLK_SDI
, "sdi", "pclk", CLKCON
, 18, 0, 0),
118 GATE(PCLK_PWM
, "pwm", "pclk", CLKCON
, 17, 0, 0),
119 GATE(PCLK_USBD
, "usb-device", "pclk", CLKCON
, 16, 0, 0),
120 GATE(SCLK_CAM
, "sclk_cam", "div_cam", CLKCON
, 15, 0, 0),
121 GATE(SCLK_UART
, "sclk_uart", "div_uart", CLKCON
, 14, 0, 0),
122 GATE(SCLK_I2S
, "sclk_i2s", "div_i2s", CLKCON
, 13, 0, 0),
123 GATE(SCLK_USBH
, "sclk_usbh", "div_usb", CLKCON
, 12, 0, 0),
124 GATE(SCLK_USBD
, "sclk_usbd", "div_usb", CLKCON
, 11, 0, 0),
125 GATE(HCLK_HALF
, "hclk_half", "div_hclk_half", CLKCON
, 10, CLK_IGNORE_UNUSED
, 0),
126 GATE(HCLK_X2
, "hclkx2", "ff_hclk", CLKCON
, 9, CLK_IGNORE_UNUSED
, 0),
127 GATE(HCLK_SDRAM
, "sdram", "hclk", CLKCON
, 8, CLK_IGNORE_UNUSED
, 0),
128 GATE(HCLK_USBH
, "usb-host", "hclk", CLKCON
, 6, 0, 0),
129 GATE(HCLK_LCD
, "lcd", "hclk", CLKCON
, 5, 0, 0),
130 GATE(HCLK_NAND
, "nand", "hclk", CLKCON
, 4, 0, 0),
131 GATE(HCLK_DMA3
, "dma3", "hclk", CLKCON
, 3, CLK_IGNORE_UNUSED
, 0),
132 GATE(HCLK_DMA2
, "dma2", "hclk", CLKCON
, 2, CLK_IGNORE_UNUSED
, 0),
133 GATE(HCLK_DMA1
, "dma1", "hclk", CLKCON
, 1, CLK_IGNORE_UNUSED
, 0),
134 GATE(HCLK_DMA0
, "dma0", "hclk", CLKCON
, 0, CLK_IGNORE_UNUSED
, 0),
137 static struct samsung_clock_alias s3c2412_aliases
[] __initdata
= {
138 ALIAS(PCLK_UART0
, "s3c2412-uart.0", "uart"),
139 ALIAS(PCLK_UART1
, "s3c2412-uart.1", "uart"),
140 ALIAS(PCLK_UART2
, "s3c2412-uart.2", "uart"),
141 ALIAS(PCLK_UART0
, "s3c2412-uart.0", "clk_uart_baud2"),
142 ALIAS(PCLK_UART1
, "s3c2412-uart.1", "clk_uart_baud2"),
143 ALIAS(PCLK_UART2
, "s3c2412-uart.2", "clk_uart_baud2"),
144 ALIAS(SCLK_UART
, NULL
, "clk_uart_baud3"),
145 ALIAS(PCLK_I2C
, "s3c2410-i2c.0", "i2c"),
146 ALIAS(PCLK_ADC
, NULL
, "adc"),
147 ALIAS(PCLK_RTC
, NULL
, "rtc"),
148 ALIAS(PCLK_PWM
, NULL
, "timers"),
149 ALIAS(HCLK_LCD
, NULL
, "lcd"),
150 ALIAS(PCLK_USBD
, NULL
, "usb-device"),
151 ALIAS(SCLK_USBD
, NULL
, "usb-bus-gadget"),
152 ALIAS(HCLK_USBH
, NULL
, "usb-host"),
153 ALIAS(SCLK_USBH
, NULL
, "usb-bus-host"),
154 ALIAS(ARMCLK
, NULL
, "armclk"),
155 ALIAS(HCLK
, NULL
, "hclk"),
156 ALIAS(MPLL
, NULL
, "mpll"),
157 ALIAS(MSYSCLK
, NULL
, "fclk"),
160 static int s3c2412_restart(struct notifier_block
*this,
161 unsigned long mode
, void *cmd
)
163 /* errata "Watch-dog/Software Reset Problem" specifies that
164 * this reset must be done with the SYSCLK sourced from
165 * EXTCLK instead of FOUT to avoid a glitch in the reset
168 * See the watchdog section of the S3C2412 manual for more
169 * information on this fix.
172 __raw_writel(0x00, reg_base
+ CLKSRC
);
173 __raw_writel(0x533C2412, reg_base
+ SWRST
);
177 static struct notifier_block s3c2412_restart_handler
= {
178 .notifier_call
= s3c2412_restart
,
183 * fixed rate clocks generated outside the soc
184 * Only necessary until the devicetree-move is complete
187 static struct samsung_fixed_rate_clock s3c2412_common_frate_clks
[] __initdata
= {
188 FRATE(XTI
, "xti", NULL
, 0, 0),
189 FRATE(0, "ext", NULL
, 0, 0),
192 static void __init
s3c2412_common_clk_register_fixed_ext(
193 struct samsung_clk_provider
*ctx
,
194 unsigned long xti_f
, unsigned long ext_f
)
196 /* xtal alias is necessary for the current cpufreq driver */
197 struct samsung_clock_alias xti_alias
= ALIAS(XTI
, NULL
, "xtal");
199 s3c2412_common_frate_clks
[0].fixed_rate
= xti_f
;
200 s3c2412_common_frate_clks
[1].fixed_rate
= ext_f
;
201 samsung_clk_register_fixed_rate(ctx
, s3c2412_common_frate_clks
,
202 ARRAY_SIZE(s3c2412_common_frate_clks
));
204 samsung_clk_register_alias(ctx
, &xti_alias
, 1);
207 void __init
s3c2412_common_clk_init(struct device_node
*np
, unsigned long xti_f
,
208 unsigned long ext_f
, void __iomem
*base
)
210 struct samsung_clk_provider
*ctx
;
215 reg_base
= of_iomap(np
, 0);
217 panic("%s: failed to map registers\n", __func__
);
220 ctx
= samsung_clk_init(np
, reg_base
, NR_CLKS
);
222 /* Register external clocks only in non-dt cases */
224 s3c2412_common_clk_register_fixed_ext(ctx
, xti_f
, ext_f
);
227 samsung_clk_register_pll(ctx
, s3c2412_plls
, ARRAY_SIZE(s3c2412_plls
),
230 /* Register common internal clocks. */
231 samsung_clk_register_mux(ctx
, s3c2412_muxes
, ARRAY_SIZE(s3c2412_muxes
));
232 samsung_clk_register_div(ctx
, s3c2412_dividers
,
233 ARRAY_SIZE(s3c2412_dividers
));
234 samsung_clk_register_gate(ctx
, s3c2412_gates
,
235 ARRAY_SIZE(s3c2412_gates
));
236 samsung_clk_register_fixed_factor(ctx
, s3c2412_ffactor
,
237 ARRAY_SIZE(s3c2412_ffactor
));
238 samsung_clk_register_alias(ctx
, s3c2412_aliases
,
239 ARRAY_SIZE(s3c2412_aliases
));
241 samsung_clk_sleep_init(reg_base
, s3c2412_clk_regs
,
242 ARRAY_SIZE(s3c2412_clk_regs
));
244 samsung_clk_of_add_provider(np
, ctx
);
246 ret
= register_restart_handler(&s3c2412_restart_handler
);
248 pr_warn("cannot register restart handler, %d\n", ret
);
251 static void __init
s3c2412_clk_init(struct device_node
*np
)
253 s3c2412_common_clk_init(np
, 0, 0, NULL
);
255 CLK_OF_DECLARE(s3c2412_clk
, "samsung,s3c2412-clock", s3c2412_clk_init
);