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mmc: core: Reset HPI enabled state during re-init and in case of errors
[linux/fpc-iii.git] / drivers / soc / fsl / qbman / qman.c
blob5ce24718c2fd1aa37ef0206a12a102025a987b7d
1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Freescale Semiconductor nor the
11 * names of its contributors may be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * ALTERNATIVELY, this software may be distributed under the terms of the
15 * GNU General Public License ("GPL") as published by the Free Software
16 * Foundation, either version 2 of that License or (at your option) any
17 * later version.
18 *
19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qman_priv.h"
32
33 #define DQRR_MAXFILL 15
34 #define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */
35 #define IRQNAME "QMan portal %d"
36 #define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
37 #define QMAN_POLL_LIMIT 32
38 #define QMAN_PIRQ_DQRR_ITHRESH 12
39 #define QMAN_PIRQ_MR_ITHRESH 4
40 #define QMAN_PIRQ_IPERIOD 100
41
42 /* Portal register assists */
43
44 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
45 /* Cache-inhibited register offsets */
46 #define QM_REG_EQCR_PI_CINH 0x3000
47 #define QM_REG_EQCR_CI_CINH 0x3040
48 #define QM_REG_EQCR_ITR 0x3080
49 #define QM_REG_DQRR_PI_CINH 0x3100
50 #define QM_REG_DQRR_CI_CINH 0x3140
51 #define QM_REG_DQRR_ITR 0x3180
52 #define QM_REG_DQRR_DCAP 0x31C0
53 #define QM_REG_DQRR_SDQCR 0x3200
54 #define QM_REG_DQRR_VDQCR 0x3240
55 #define QM_REG_DQRR_PDQCR 0x3280
56 #define QM_REG_MR_PI_CINH 0x3300
57 #define QM_REG_MR_CI_CINH 0x3340
58 #define QM_REG_MR_ITR 0x3380
59 #define QM_REG_CFG 0x3500
60 #define QM_REG_ISR 0x3600
61 #define QM_REG_IER 0x3640
62 #define QM_REG_ISDR 0x3680
63 #define QM_REG_IIR 0x36C0
64 #define QM_REG_ITPR 0x3740
65
66 /* Cache-enabled register offsets */
67 #define QM_CL_EQCR 0x0000
68 #define QM_CL_DQRR 0x1000
69 #define QM_CL_MR 0x2000
70 #define QM_CL_EQCR_PI_CENA 0x3000
71 #define QM_CL_EQCR_CI_CENA 0x3040
72 #define QM_CL_DQRR_PI_CENA 0x3100
73 #define QM_CL_DQRR_CI_CENA 0x3140
74 #define QM_CL_MR_PI_CENA 0x3300
75 #define QM_CL_MR_CI_CENA 0x3340
76 #define QM_CL_CR 0x3800
77 #define QM_CL_RR0 0x3900
78 #define QM_CL_RR1 0x3940
79
80 #else
81 /* Cache-inhibited register offsets */
82 #define QM_REG_EQCR_PI_CINH 0x0000
83 #define QM_REG_EQCR_CI_CINH 0x0004
84 #define QM_REG_EQCR_ITR 0x0008
85 #define QM_REG_DQRR_PI_CINH 0x0040
86 #define QM_REG_DQRR_CI_CINH 0x0044
87 #define QM_REG_DQRR_ITR 0x0048
88 #define QM_REG_DQRR_DCAP 0x0050
89 #define QM_REG_DQRR_SDQCR 0x0054
90 #define QM_REG_DQRR_VDQCR 0x0058
91 #define QM_REG_DQRR_PDQCR 0x005c
92 #define QM_REG_MR_PI_CINH 0x0080
93 #define QM_REG_MR_CI_CINH 0x0084
94 #define QM_REG_MR_ITR 0x0088
95 #define QM_REG_CFG 0x0100
96 #define QM_REG_ISR 0x0e00
97 #define QM_REG_IER 0x0e04
98 #define QM_REG_ISDR 0x0e08
99 #define QM_REG_IIR 0x0e0c
100 #define QM_REG_ITPR 0x0e14
101
102 /* Cache-enabled register offsets */
103 #define QM_CL_EQCR 0x0000
104 #define QM_CL_DQRR 0x1000
105 #define QM_CL_MR 0x2000
106 #define QM_CL_EQCR_PI_CENA 0x3000
107 #define QM_CL_EQCR_CI_CENA 0x3100
108 #define QM_CL_DQRR_PI_CENA 0x3200
109 #define QM_CL_DQRR_CI_CENA 0x3300
110 #define QM_CL_MR_PI_CENA 0x3400
111 #define QM_CL_MR_CI_CENA 0x3500
112 #define QM_CL_CR 0x3800
113 #define QM_CL_RR0 0x3900
114 #define QM_CL_RR1 0x3940
115 #endif
116
117 /*
118 * BTW, the drivers (and h/w programming model) already obtain the required
119 * synchronisation for portal accesses and data-dependencies. Use of barrier()s
120 * or other order-preserving primitives simply degrade performance. Hence the
121 * use of the __raw_*() interfaces, which simply ensure that the compiler treats
122 * the portal registers as volatile
123 */
124
125 /* Cache-enabled ring access */
126 #define qm_cl(base, idx) ((void *)base + ((idx) << 6))
127
128 /*
129 * Portal modes.
130 * Enum types;
131 * pmode == production mode
132 * cmode == consumption mode,
133 * dmode == h/w dequeue mode.
134 * Enum values use 3 letter codes. First letter matches the portal mode,
135 * remaining two letters indicate;
136 * ci == cache-inhibited portal register
137 * ce == cache-enabled portal register
138 * vb == in-band valid-bit (cache-enabled)
139 * dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
140 * As for "enum qm_dqrr_dmode", it should be self-explanatory.
141 */
142 enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
143 qm_eqcr_pci = 0, /* PI index, cache-inhibited */
144 qm_eqcr_pce = 1, /* PI index, cache-enabled */
145 qm_eqcr_pvb = 2 /* valid-bit */
146 };
147 enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
148 qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
149 qm_dqrr_dpull = 1 /* PDQCR */
150 };
151 enum qm_dqrr_pmode { /* s/w-only */
152 qm_dqrr_pci, /* reads DQRR_PI_CINH */
153 qm_dqrr_pce, /* reads DQRR_PI_CENA */
154 qm_dqrr_pvb /* reads valid-bit */
155 };
156 enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
157 qm_dqrr_cci = 0, /* CI index, cache-inhibited */
158 qm_dqrr_cce = 1, /* CI index, cache-enabled */
159 qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
160 };
161 enum qm_mr_pmode { /* s/w-only */
162 qm_mr_pci, /* reads MR_PI_CINH */
163 qm_mr_pce, /* reads MR_PI_CENA */
164 qm_mr_pvb /* reads valid-bit */
165 };
166 enum qm_mr_cmode { /* matches QCSP_CFG::MM */
167 qm_mr_cci = 0, /* CI index, cache-inhibited */
168 qm_mr_cce = 1 /* CI index, cache-enabled */
169 };
170
171 /* --- Portal structures --- */
172
173 #define QM_EQCR_SIZE 8
174 #define QM_DQRR_SIZE 16
175 #define QM_MR_SIZE 8
176
177 /* "Enqueue Command" */
178 struct qm_eqcr_entry {
179 u8 _ncw_verb; /* writes to this are non-coherent */
180 u8 dca;
181 __be16 seqnum;
182 u8 __reserved[4];
183 __be32 fqid; /* 24-bit */
184 __be32 tag;
185 struct qm_fd fd;
186 u8 __reserved3[32];
187 } __packed;
188 #define QM_EQCR_VERB_VBIT 0x80
189 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
190 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01
191 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
192 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
193 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
194
195 struct qm_eqcr {
196 struct qm_eqcr_entry *ring, *cursor;
197 u8 ci, available, ithresh, vbit;
198 #ifdef CONFIG_FSL_DPAA_CHECKING
199 u32 busy;
200 enum qm_eqcr_pmode pmode;
201 #endif
202 };
203
204 struct qm_dqrr {
205 const struct qm_dqrr_entry *ring, *cursor;
206 u8 pi, ci, fill, ithresh, vbit;
207 #ifdef CONFIG_FSL_DPAA_CHECKING
208 enum qm_dqrr_dmode dmode;
209 enum qm_dqrr_pmode pmode;
210 enum qm_dqrr_cmode cmode;
211 #endif
212 };
213
214 struct qm_mr {
215 union qm_mr_entry *ring, *cursor;
216 u8 pi, ci, fill, ithresh, vbit;
217 #ifdef CONFIG_FSL_DPAA_CHECKING
218 enum qm_mr_pmode pmode;
219 enum qm_mr_cmode cmode;
220 #endif
221 };
222
223 /* MC (Management Command) command */
224 /* "FQ" command layout */
225 struct qm_mcc_fq {
226 u8 _ncw_verb;
227 u8 __reserved1[3];
228 __be32 fqid; /* 24-bit */
229 u8 __reserved2[56];
230 } __packed;
231
232 /* "CGR" command layout */
233 struct qm_mcc_cgr {
234 u8 _ncw_verb;
235 u8 __reserved1[30];
236 u8 cgid;
237 u8 __reserved2[32];
238 };
239
240 #define QM_MCC_VERB_VBIT 0x80
241 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
242 #define QM_MCC_VERB_INITFQ_PARKED 0x40
243 #define QM_MCC_VERB_INITFQ_SCHED 0x41
244 #define QM_MCC_VERB_QUERYFQ 0x44
245 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
246 #define QM_MCC_VERB_QUERYWQ 0x46
247 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
248 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
249 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
250 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
251 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
252 #define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
253 #define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
254 #define QM_MCC_VERB_INITCGR 0x50
255 #define QM_MCC_VERB_MODIFYCGR 0x51
256 #define QM_MCC_VERB_CGRTESTWRITE 0x52
257 #define QM_MCC_VERB_QUERYCGR 0x58
258 #define QM_MCC_VERB_QUERYCONGESTION 0x59
259 union qm_mc_command {
260 struct {
261 u8 _ncw_verb; /* writes to this are non-coherent */
262 u8 __reserved[63];
263 };
264 struct qm_mcc_initfq initfq;
265 struct qm_mcc_initcgr initcgr;
266 struct qm_mcc_fq fq;
267 struct qm_mcc_cgr cgr;
268 };
269
270 /* MC (Management Command) result */
271 /* "Query FQ" */
272 struct qm_mcr_queryfq {
273 u8 verb;
274 u8 result;
275 u8 __reserved1[8];
276 struct qm_fqd fqd; /* the FQD fields are here */
277 u8 __reserved2[30];
278 } __packed;
279
280 /* "Alter FQ State Commands" */
281 struct qm_mcr_alterfq {
282 u8 verb;
283 u8 result;
284 u8 fqs; /* Frame Queue Status */
285 u8 __reserved1[61];
286 };
287 #define QM_MCR_VERB_RRID 0x80
288 #define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
289 #define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
290 #define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
291 #define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
292 #define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
293 #define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
294 #define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
295 #define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
296 #define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
297 #define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
298 #define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
299 #define QM_MCR_RESULT_NULL 0x00
300 #define QM_MCR_RESULT_OK 0xf0
301 #define QM_MCR_RESULT_ERR_FQID 0xf1
302 #define QM_MCR_RESULT_ERR_FQSTATE 0xf2
303 #define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
304 #define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
305 #define QM_MCR_RESULT_PENDING 0xf8
306 #define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
307 #define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
308 #define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
309 #define QM_MCR_TIMEOUT 10000 /* us */
310 union qm_mc_result {
311 struct {
312 u8 verb;
313 u8 result;
314 u8 __reserved1[62];
315 };
316 struct qm_mcr_queryfq queryfq;
317 struct qm_mcr_alterfq alterfq;
318 struct qm_mcr_querycgr querycgr;
319 struct qm_mcr_querycongestion querycongestion;
320 struct qm_mcr_querywq querywq;
321 struct qm_mcr_queryfq_np queryfq_np;
322 };
323
324 struct qm_mc {
325 union qm_mc_command *cr;
326 union qm_mc_result *rr;
327 u8 rridx, vbit;
328 #ifdef CONFIG_FSL_DPAA_CHECKING
329 enum {
330 /* Can be _mc_start()ed */
331 qman_mc_idle,
332 /* Can be _mc_commit()ed or _mc_abort()ed */
333 qman_mc_user,
334 /* Can only be _mc_retry()ed */
335 qman_mc_hw
336 } state;
337 #endif
338 };
339
340 struct qm_addr {
341 void *ce; /* cache-enabled */
342 __be32 *ce_be; /* same value as above but for direct access */
343 void __iomem *ci; /* cache-inhibited */
344 };
345
346 struct qm_portal {
347 /*
348 * In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to
349 * and including 'mc' fits within a cacheline (yay!). The 'config' part
350 * is setup-only, so isn't a cause for a concern. In other words, don't
351 * rearrange this structure on a whim, there be dragons ...
352 */
353 struct qm_addr addr;
354 struct qm_eqcr eqcr;
355 struct qm_dqrr dqrr;
356 struct qm_mr mr;
357 struct qm_mc mc;
358 } ____cacheline_aligned;
359
360 /* Cache-inhibited register access. */
361 static inline u32 qm_in(struct qm_portal *p, u32 offset)
362 {
363 return ioread32be(p->addr.ci + offset);
364 }
365
366 static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)
367 {
368 iowrite32be(val, p->addr.ci + offset);
369 }
370
371 /* Cache Enabled Portal Access */
372 static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset)
373 {
374 dpaa_invalidate(p->addr.ce + offset);
375 }
376
377 static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)
378 {
379 dpaa_touch_ro(p->addr.ce + offset);
380 }
381
382 static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)
383 {
384 return be32_to_cpu(*(p->addr.ce_be + (offset/4)));
385 }
386
387 /* --- EQCR API --- */
388
389 #define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry))
390 #define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT)
391
392 /* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
393 static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p)
394 {
395 uintptr_t addr = (uintptr_t)p;
396
397 addr &= ~EQCR_CARRY;
398
399 return (struct qm_eqcr_entry *)addr;
400 }
401
402 /* Bit-wise logic to convert a ring pointer to a ring index */
403 static int eqcr_ptr2idx(struct qm_eqcr_entry *e)
404 {
405 return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1);
406 }
407
408 /* Increment the 'cursor' ring pointer, taking 'vbit' into account */
409 static inline void eqcr_inc(struct qm_eqcr *eqcr)
410 {
411 /* increment to the next EQCR pointer and handle overflow and 'vbit' */
412 struct qm_eqcr_entry *partial = eqcr->cursor + 1;
413
414 eqcr->cursor = eqcr_carryclear(partial);
415 if (partial != eqcr->cursor)
416 eqcr->vbit ^= QM_EQCR_VERB_VBIT;
417 }
418
419 static inline int qm_eqcr_init(struct qm_portal *portal,
420 enum qm_eqcr_pmode pmode,
421 unsigned int eq_stash_thresh,
422 int eq_stash_prio)
423 {
424 struct qm_eqcr *eqcr = &portal->eqcr;
425 u32 cfg;
426 u8 pi;
427
428 eqcr->ring = portal->addr.ce + QM_CL_EQCR;
429 eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
430 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
431 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
432 eqcr->cursor = eqcr->ring + pi;
433 eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ?
434 QM_EQCR_VERB_VBIT : 0;
435 eqcr->available = QM_EQCR_SIZE - 1 -
436 dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
437 eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR);
438 #ifdef CONFIG_FSL_DPAA_CHECKING
439 eqcr->busy = 0;
440 eqcr->pmode = pmode;
441 #endif
442 cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) |
443 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
444 (eq_stash_prio << 26) | /* QCSP_CFG: EP */
445 ((pmode & 0x3) << 24); /* QCSP_CFG::EPM */
446 qm_out(portal, QM_REG_CFG, cfg);
447 return 0;
448 }
449
450 static inline unsigned int qm_eqcr_get_ci_stashing(struct qm_portal *portal)
451 {
452 return (qm_in(portal, QM_REG_CFG) >> 28) & 0x7;
453 }
454
455 static inline void qm_eqcr_finish(struct qm_portal *portal)
456 {
457 struct qm_eqcr *eqcr = &portal->eqcr;
458 u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
459 u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
460
461 DPAA_ASSERT(!eqcr->busy);
462 if (pi != eqcr_ptr2idx(eqcr->cursor))
463 pr_crit("losing uncommitted EQCR entries\n");
464 if (ci != eqcr->ci)
465 pr_crit("missing existing EQCR completions\n");
466 if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
467 pr_crit("EQCR destroyed unquiesced\n");
468 }
469
470 static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
471 *portal)
472 {
473 struct qm_eqcr *eqcr = &portal->eqcr;
474
475 DPAA_ASSERT(!eqcr->busy);
476 if (!eqcr->available)
477 return NULL;
478
479 #ifdef CONFIG_FSL_DPAA_CHECKING
480 eqcr->busy = 1;
481 #endif
482 dpaa_zero(eqcr->cursor);
483 return eqcr->cursor;
484 }
485
486 static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
487 *portal)
488 {
489 struct qm_eqcr *eqcr = &portal->eqcr;
490 u8 diff, old_ci;
491
492 DPAA_ASSERT(!eqcr->busy);
493 if (!eqcr->available) {
494 old_ci = eqcr->ci;
495 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) &
496 (QM_EQCR_SIZE - 1);
497 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
498 eqcr->available += diff;
499 if (!diff)
500 return NULL;
501 }
502 #ifdef CONFIG_FSL_DPAA_CHECKING
503 eqcr->busy = 1;
504 #endif
505 dpaa_zero(eqcr->cursor);
506 return eqcr->cursor;
507 }
508
509 static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
510 {
511 DPAA_ASSERT(eqcr->busy);
512 DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK));
513 DPAA_ASSERT(eqcr->available >= 1);
514 }
515
516 static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
517 {
518 struct qm_eqcr *eqcr = &portal->eqcr;
519 struct qm_eqcr_entry *eqcursor;
520
521 eqcr_commit_checks(eqcr);
522 DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
523 dma_wmb();
524 eqcursor = eqcr->cursor;
525 eqcursor->_ncw_verb = myverb | eqcr->vbit;
526 dpaa_flush(eqcursor);
527 eqcr_inc(eqcr);
528 eqcr->available--;
529 #ifdef CONFIG_FSL_DPAA_CHECKING
530 eqcr->busy = 0;
531 #endif
532 }
533
534 static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
535 {
536 qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA);
537 }
538
539 static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
540 {
541 struct qm_eqcr *eqcr = &portal->eqcr;
542 u8 diff, old_ci = eqcr->ci;
543
544 eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1);
545 qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
546 diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
547 eqcr->available += diff;
548 return diff;
549 }
550
551 static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
552 {
553 struct qm_eqcr *eqcr = &portal->eqcr;
554
555 eqcr->ithresh = ithresh;
556 qm_out(portal, QM_REG_EQCR_ITR, ithresh);
557 }
558
559 static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
560 {
561 struct qm_eqcr *eqcr = &portal->eqcr;
562
563 return eqcr->available;
564 }
565
566 static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
567 {
568 struct qm_eqcr *eqcr = &portal->eqcr;
569
570 return QM_EQCR_SIZE - 1 - eqcr->available;
571 }
572
573 /* --- DQRR API --- */
574
575 #define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry))
576 #define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT)
577
578 static const struct qm_dqrr_entry *dqrr_carryclear(
579 const struct qm_dqrr_entry *p)
580 {
581 uintptr_t addr = (uintptr_t)p;
582
583 addr &= ~DQRR_CARRY;
584
585 return (const struct qm_dqrr_entry *)addr;
586 }
587
588 static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e)
589 {
590 return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1);
591 }
592
593 static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e)
594 {
595 return dqrr_carryclear(e + 1);
596 }
597
598 static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
599 {
600 qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) |
601 ((mf & (QM_DQRR_SIZE - 1)) << 20));
602 }
603
604 static inline int qm_dqrr_init(struct qm_portal *portal,
605 const struct qm_portal_config *config,
606 enum qm_dqrr_dmode dmode,
607 enum qm_dqrr_pmode pmode,
608 enum qm_dqrr_cmode cmode, u8 max_fill)
609 {
610 struct qm_dqrr *dqrr = &portal->dqrr;
611 u32 cfg;
612
613 /* Make sure the DQRR will be idle when we enable */
614 qm_out(portal, QM_REG_DQRR_SDQCR, 0);
615 qm_out(portal, QM_REG_DQRR_VDQCR, 0);
616 qm_out(portal, QM_REG_DQRR_PDQCR, 0);
617 dqrr->ring = portal->addr.ce + QM_CL_DQRR;
618 dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
619 dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
620 dqrr->cursor = dqrr->ring + dqrr->ci;
621 dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
622 dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ?
623 QM_DQRR_VERB_VBIT : 0;
624 dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR);
625 #ifdef CONFIG_FSL_DPAA_CHECKING
626 dqrr->dmode = dmode;
627 dqrr->pmode = pmode;
628 dqrr->cmode = cmode;
629 #endif
630 /* Invalidate every ring entry before beginning */
631 for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
632 dpaa_invalidate(qm_cl(dqrr->ring, cfg));
633 cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) |
634 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
635 ((dmode & 1) << 18) | /* DP */
636 ((cmode & 3) << 16) | /* DCM */
637 0xa0 | /* RE+SE */
638 (0 ? 0x40 : 0) | /* Ignore RP */
639 (0 ? 0x10 : 0); /* Ignore SP */
640 qm_out(portal, QM_REG_CFG, cfg);
641 qm_dqrr_set_maxfill(portal, max_fill);
642 return 0;
643 }
644
645 static inline void qm_dqrr_finish(struct qm_portal *portal)
646 {
647 #ifdef CONFIG_FSL_DPAA_CHECKING
648 struct qm_dqrr *dqrr = &portal->dqrr;
649
650 if (dqrr->cmode != qm_dqrr_cdc &&
651 dqrr->ci != dqrr_ptr2idx(dqrr->cursor))
652 pr_crit("Ignoring completed DQRR entries\n");
653 #endif
654 }
655
656 static inline const struct qm_dqrr_entry *qm_dqrr_current(
657 struct qm_portal *portal)
658 {
659 struct qm_dqrr *dqrr = &portal->dqrr;
660
661 if (!dqrr->fill)
662 return NULL;
663 return dqrr->cursor;
664 }
665
666 static inline u8 qm_dqrr_next(struct qm_portal *portal)
667 {
668 struct qm_dqrr *dqrr = &portal->dqrr;
669
670 DPAA_ASSERT(dqrr->fill);
671 dqrr->cursor = dqrr_inc(dqrr->cursor);
672 return --dqrr->fill;
673 }
674
675 static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
676 {
677 struct qm_dqrr *dqrr = &portal->dqrr;
678 struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
679
680 DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
681 #ifndef CONFIG_FSL_PAMU
682 /*
683 * If PAMU is not available we need to invalidate the cache.
684 * When PAMU is available the cache is updated by stash
685 */
686 dpaa_invalidate_touch_ro(res);
687 #endif
688 if ((res->verb & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
689 dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
690 if (!dqrr->pi)
691 dqrr->vbit ^= QM_DQRR_VERB_VBIT;
692 dqrr->fill++;
693 }
694 }
695
696 static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
697 const struct qm_dqrr_entry *dq,
698 int park)
699 {
700 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
701 int idx = dqrr_ptr2idx(dq);
702
703 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
704 DPAA_ASSERT((dqrr->ring + idx) == dq);
705 DPAA_ASSERT(idx < QM_DQRR_SIZE);
706 qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
707 ((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
708 idx); /* DQRR_DCAP::DCAP_CI */
709 }
710
711 static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask)
712 {
713 __maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
714
715 DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
716 qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
717 (bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
718 }
719
720 static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
721 {
722 qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr);
723 }
724
725 static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
726 {
727 qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr);
728 }
729
730 static inline void qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
731 {
732 qm_out(portal, QM_REG_DQRR_ITR, ithresh);
733 }
734
735 /* --- MR API --- */
736
737 #define MR_SHIFT ilog2(sizeof(union qm_mr_entry))
738 #define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT)
739
740 static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p)
741 {
742 uintptr_t addr = (uintptr_t)p;
743
744 addr &= ~MR_CARRY;
745
746 return (union qm_mr_entry *)addr;
747 }
748
749 static inline int mr_ptr2idx(const union qm_mr_entry *e)
750 {
751 return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1);
752 }
753
754 static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e)
755 {
756 return mr_carryclear(e + 1);
757 }
758
759 static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode,
760 enum qm_mr_cmode cmode)
761 {
762 struct qm_mr *mr = &portal->mr;
763 u32 cfg;
764
765 mr->ring = portal->addr.ce + QM_CL_MR;
766 mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1);
767 mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1);
768 mr->cursor = mr->ring + mr->ci;
769 mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
770 mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE)
771 ? QM_MR_VERB_VBIT : 0;
772 mr->ithresh = qm_in(portal, QM_REG_MR_ITR);
773 #ifdef CONFIG_FSL_DPAA_CHECKING
774 mr->pmode = pmode;
775 mr->cmode = cmode;
776 #endif
777 cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) |
778 ((cmode & 1) << 8); /* QCSP_CFG:MM */
779 qm_out(portal, QM_REG_CFG, cfg);
780 return 0;
781 }
782
783 static inline void qm_mr_finish(struct qm_portal *portal)
784 {
785 struct qm_mr *mr = &portal->mr;
786
787 if (mr->ci != mr_ptr2idx(mr->cursor))
788 pr_crit("Ignoring completed MR entries\n");
789 }
790
791 static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal)
792 {
793 struct qm_mr *mr = &portal->mr;
794
795 if (!mr->fill)
796 return NULL;
797 return mr->cursor;
798 }
799
800 static inline int qm_mr_next(struct qm_portal *portal)
801 {
802 struct qm_mr *mr = &portal->mr;
803
804 DPAA_ASSERT(mr->fill);
805 mr->cursor = mr_inc(mr->cursor);
806 return --mr->fill;
807 }
808
809 static inline void qm_mr_pvb_update(struct qm_portal *portal)
810 {
811 struct qm_mr *mr = &portal->mr;
812 union qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
813
814 DPAA_ASSERT(mr->pmode == qm_mr_pvb);
815
816 if ((res->verb & QM_MR_VERB_VBIT) == mr->vbit) {
817 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
818 if (!mr->pi)
819 mr->vbit ^= QM_MR_VERB_VBIT;
820 mr->fill++;
821 res = mr_inc(res);
822 }
823 dpaa_invalidate_touch_ro(res);
824 }
825
826 static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
827 {
828 struct qm_mr *mr = &portal->mr;
829
830 DPAA_ASSERT(mr->cmode == qm_mr_cci);
831 mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
832 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
833 }
834
835 static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
836 {
837 struct qm_mr *mr = &portal->mr;
838
839 DPAA_ASSERT(mr->cmode == qm_mr_cci);
840 mr->ci = mr_ptr2idx(mr->cursor);
841 qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
842 }
843
844 static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
845 {
846 qm_out(portal, QM_REG_MR_ITR, ithresh);
847 }
848
849 /* --- Management command API --- */
850
851 static inline int qm_mc_init(struct qm_portal *portal)
852 {
853 u8 rr0, rr1;
854 struct qm_mc *mc = &portal->mc;
855
856 mc->cr = portal->addr.ce + QM_CL_CR;
857 mc->rr = portal->addr.ce + QM_CL_RR0;
858 /*
859 * The expected valid bit polarity for the next CR command is 0
860 * if RR1 contains a valid response, and is 1 if RR0 contains a
861 * valid response. If both RR contain all 0, this indicates either
862 * that no command has been executed since reset (in which case the
863 * expected valid bit polarity is 1)
864 */
865 rr0 = mc->rr->verb;
866 rr1 = (mc->rr+1)->verb;
867 if ((rr0 == 0 && rr1 == 0) || rr0 != 0)
868 mc->rridx = 1;
869 else
870 mc->rridx = 0;
871 mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
872 #ifdef CONFIG_FSL_DPAA_CHECKING
873 mc->state = qman_mc_idle;
874 #endif
875 return 0;
876 }
877
878 static inline void qm_mc_finish(struct qm_portal *portal)
879 {
880 #ifdef CONFIG_FSL_DPAA_CHECKING
881 struct qm_mc *mc = &portal->mc;
882
883 DPAA_ASSERT(mc->state == qman_mc_idle);
884 if (mc->state != qman_mc_idle)
885 pr_crit("Losing incomplete MC command\n");
886 #endif
887 }
888
889 static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal)
890 {
891 struct qm_mc *mc = &portal->mc;
892
893 DPAA_ASSERT(mc->state == qman_mc_idle);
894 #ifdef CONFIG_FSL_DPAA_CHECKING
895 mc->state = qman_mc_user;
896 #endif
897 dpaa_zero(mc->cr);
898 return mc->cr;
899 }
900
901 static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
902 {
903 struct qm_mc *mc = &portal->mc;
904 union qm_mc_result *rr = mc->rr + mc->rridx;
905
906 DPAA_ASSERT(mc->state == qman_mc_user);
907 dma_wmb();
908 mc->cr->_ncw_verb = myverb | mc->vbit;
909 dpaa_flush(mc->cr);
910 dpaa_invalidate_touch_ro(rr);
911 #ifdef CONFIG_FSL_DPAA_CHECKING
912 mc->state = qman_mc_hw;
913 #endif
914 }
915
916 static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)
917 {
918 struct qm_mc *mc = &portal->mc;
919 union qm_mc_result *rr = mc->rr + mc->rridx;
920
921 DPAA_ASSERT(mc->state == qman_mc_hw);
922 /*
923 * The inactive response register's verb byte always returns zero until
924 * its command is submitted and completed. This includes the valid-bit,
925 * in case you were wondering...
926 */
927 if (!rr->verb) {
928 dpaa_invalidate_touch_ro(rr);
929 return NULL;
930 }
931 mc->rridx ^= 1;
932 mc->vbit ^= QM_MCC_VERB_VBIT;
933 #ifdef CONFIG_FSL_DPAA_CHECKING
934 mc->state = qman_mc_idle;
935 #endif
936 return rr;
937 }
938
939 static inline int qm_mc_result_timeout(struct qm_portal *portal,
940 union qm_mc_result **mcr)
941 {
942 int timeout = QM_MCR_TIMEOUT;
943
944 do {
945 *mcr = qm_mc_result(portal);
946 if (*mcr)
947 break;
948 udelay(1);
949 } while (--timeout);
950
951 return timeout;
952 }
953
954 static inline void fq_set(struct qman_fq *fq, u32 mask)
955 {
956 fq->flags |= mask;
957 }
958
959 static inline void fq_clear(struct qman_fq *fq, u32 mask)
960 {
961 fq->flags &= ~mask;
962 }
963
964 static inline int fq_isset(struct qman_fq *fq, u32 mask)
965 {
966 return fq->flags & mask;
967 }
968
969 static inline int fq_isclear(struct qman_fq *fq, u32 mask)
970 {
971 return !(fq->flags & mask);
972 }
973
974 struct qman_portal {
975 struct qm_portal p;
976 /* PORTAL_BITS_*** - dynamic, strictly internal */
977 unsigned long bits;
978 /* interrupt sources processed by portal_isr(), configurable */
979 unsigned long irq_sources;
980 u32 use_eqcr_ci_stashing;
981 /* only 1 volatile dequeue at a time */
982 struct qman_fq *vdqcr_owned;
983 u32 sdqcr;
984 /* probing time config params for cpu-affine portals */
985 const struct qm_portal_config *config;
986 /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
987 struct qman_cgrs *cgrs;
988 /* linked-list of CSCN handlers. */
989 struct list_head cgr_cbs;
990 /* list lock */
991 spinlock_t cgr_lock;
992 struct work_struct congestion_work;
993 struct work_struct mr_work;
994 char irqname[MAX_IRQNAME];
995 };
996
997 static cpumask_t affine_mask;
998 static DEFINE_SPINLOCK(affine_mask_lock);
999 static u16 affine_channels[NR_CPUS];
1000 static DEFINE_PER_CPU(struct qman_portal, qman_affine_portal);
1001 struct qman_portal *affine_portals[NR_CPUS];
1002
1003 static inline struct qman_portal *get_affine_portal(void)
1004 {
1005 return &get_cpu_var(qman_affine_portal);
1006 }
1007
1008 static inline void put_affine_portal(void)
1009 {
1010 put_cpu_var(qman_affine_portal);
1011 }
1012
1013 static struct workqueue_struct *qm_portal_wq;
1014
1015 void qman_dqrr_set_ithresh(struct qman_portal *portal, u8 ithresh)
1016 {
1017 if (!portal)
1018 return;
1019
1020 qm_dqrr_set_ithresh(&portal->p, ithresh);
1021 portal->p.dqrr.ithresh = ithresh;
1022 }
1023 EXPORT_SYMBOL(qman_dqrr_set_ithresh);
1024
1025 void qman_dqrr_get_ithresh(struct qman_portal *portal, u8 *ithresh)
1026 {
1027 if (portal && ithresh)
1028 *ithresh = portal->p.dqrr.ithresh;
1029 }
1030 EXPORT_SYMBOL(qman_dqrr_get_ithresh);
1031
1032 void qman_portal_get_iperiod(struct qman_portal *portal, u32 *iperiod)
1033 {
1034 if (portal && iperiod)
1035 *iperiod = qm_in(&portal->p, QM_REG_ITPR);
1036 }
1037 EXPORT_SYMBOL(qman_portal_get_iperiod);
1038
1039 void qman_portal_set_iperiod(struct qman_portal *portal, u32 iperiod)
1040 {
1041 if (portal)
1042 qm_out(&portal->p, QM_REG_ITPR, iperiod);
1043 }
1044 EXPORT_SYMBOL(qman_portal_set_iperiod);
1045
1046 int qman_wq_alloc(void)
1047 {
1048 qm_portal_wq = alloc_workqueue("qman_portal_wq", 0, 1);
1049 if (!qm_portal_wq)
1050 return -ENOMEM;
1051 return 0;
1052 }
1053
1054 /*
1055 * This is what everything can wait on, even if it migrates to a different cpu
1056 * to the one whose affine portal it is waiting on.
1057 */
1058 static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
1059
1060 static struct qman_fq **fq_table;
1061 static u32 num_fqids;
1062
1063 int qman_alloc_fq_table(u32 _num_fqids)
1064 {
1065 num_fqids = _num_fqids;
1066
1067 fq_table = vzalloc(array3_size(sizeof(struct qman_fq *),
1068 num_fqids, 2));
1069 if (!fq_table)
1070 return -ENOMEM;
1071
1072 pr_debug("Allocated fq lookup table at %p, entry count %u\n",
1073 fq_table, num_fqids * 2);
1074 return 0;
1075 }
1076
1077 static struct qman_fq *idx_to_fq(u32 idx)
1078 {
1079 struct qman_fq *fq;
1080
1081 #ifdef CONFIG_FSL_DPAA_CHECKING
1082 if (WARN_ON(idx >= num_fqids * 2))
1083 return NULL;
1084 #endif
1085 fq = fq_table[idx];
1086 DPAA_ASSERT(!fq || idx == fq->idx);
1087
1088 return fq;
1089 }
1090
1091 /*
1092 * Only returns full-service fq objects, not enqueue-only
1093 * references (QMAN_FQ_FLAG_NO_MODIFY).
1094 */
1095 static struct qman_fq *fqid_to_fq(u32 fqid)
1096 {
1097 return idx_to_fq(fqid * 2);
1098 }
1099
1100 static struct qman_fq *tag_to_fq(u32 tag)
1101 {
1102 #if BITS_PER_LONG == 64
1103 return idx_to_fq(tag);
1104 #else
1105 return (struct qman_fq *)tag;
1106 #endif
1107 }
1108
1109 static u32 fq_to_tag(struct qman_fq *fq)
1110 {
1111 #if BITS_PER_LONG == 64
1112 return fq->idx;
1113 #else
1114 return (u32)fq;
1115 #endif
1116 }
1117
1118 static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
1119 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1120 unsigned int poll_limit);
1121 static void qm_congestion_task(struct work_struct *work);
1122 static void qm_mr_process_task(struct work_struct *work);
1123
1124 static irqreturn_t portal_isr(int irq, void *ptr)
1125 {
1126 struct qman_portal *p = ptr;
1127
1128 u32 clear = QM_DQAVAIL_MASK | p->irq_sources;
1129 u32 is = qm_in(&p->p, QM_REG_ISR) & p->irq_sources;
1130
1131 if (unlikely(!is))
1132 return IRQ_NONE;
1133
1134 /* DQRR-handling if it's interrupt-driven */
1135 if (is & QM_PIRQ_DQRI)
1136 __poll_portal_fast(p, QMAN_POLL_LIMIT);
1137 /* Handling of anything else that's interrupt-driven */
1138 clear |= __poll_portal_slow(p, is);
1139 qm_out(&p->p, QM_REG_ISR, clear);
1140 return IRQ_HANDLED;
1141 }
1142
1143 static int drain_mr_fqrni(struct qm_portal *p)
1144 {
1145 const union qm_mr_entry *msg;
1146 loop:
1147 msg = qm_mr_current(p);
1148 if (!msg) {
1149 /*
1150 * if MR was full and h/w had other FQRNI entries to produce, we
1151 * need to allow it time to produce those entries once the
1152 * existing entries are consumed. A worst-case situation
1153 * (fully-loaded system) means h/w sequencers may have to do 3-4
1154 * other things before servicing the portal's MR pump, each of
1155 * which (if slow) may take ~50 qman cycles (which is ~200
1156 * processor cycles). So rounding up and then multiplying this
1157 * worst-case estimate by a factor of 10, just to be
1158 * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
1159 * one entry at a time, so h/w has an opportunity to produce new
1160 * entries well before the ring has been fully consumed, so
1161 * we're being *really* paranoid here.
1162 */
1163 msleep(1);
1164 msg = qm_mr_current(p);
1165 if (!msg)
1166 return 0;
1167 }
1168 if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
1169 /* We aren't draining anything but FQRNIs */
1170 pr_err("Found verb 0x%x in MR\n", msg->verb);
1171 return -1;
1172 }
1173 qm_mr_next(p);
1174 qm_mr_cci_consume(p, 1);
1175 goto loop;
1176 }
1177
1178 static int qman_create_portal(struct qman_portal *portal,
1179 const struct qm_portal_config *c,
1180 const struct qman_cgrs *cgrs)
1181 {
1182 struct qm_portal *p;
1183 int ret;
1184 u32 isdr;
1185
1186 p = &portal->p;
1187
1188 #ifdef CONFIG_FSL_PAMU
1189 /* PAMU is required for stashing */
1190 portal->use_eqcr_ci_stashing = ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
1191 #else
1192 portal->use_eqcr_ci_stashing = 0;
1193 #endif
1194 /*
1195 * prep the low-level portal struct with the mapped addresses from the
1196 * config, everything that follows depends on it and "config" is more
1197 * for (de)reference
1198 */
1199 p->addr.ce = c->addr_virt_ce;
1200 p->addr.ce_be = c->addr_virt_ce;
1201 p->addr.ci = c->addr_virt_ci;
1202 /*
1203 * If CI-stashing is used, the current defaults use a threshold of 3,
1204 * and stash with high-than-DQRR priority.
1205 */
1206 if (qm_eqcr_init(p, qm_eqcr_pvb,
1207 portal->use_eqcr_ci_stashing ? 3 : 0, 1)) {
1208 dev_err(c->dev, "EQCR initialisation failed\n");
1209 goto fail_eqcr;
1210 }
1211 if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
1212 qm_dqrr_cdc, DQRR_MAXFILL)) {
1213 dev_err(c->dev, "DQRR initialisation failed\n");
1214 goto fail_dqrr;
1215 }
1216 if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
1217 dev_err(c->dev, "MR initialisation failed\n");
1218 goto fail_mr;
1219 }
1220 if (qm_mc_init(p)) {
1221 dev_err(c->dev, "MC initialisation failed\n");
1222 goto fail_mc;
1223 }
1224 /* static interrupt-gating controls */
1225 qm_dqrr_set_ithresh(p, QMAN_PIRQ_DQRR_ITHRESH);
1226 qm_mr_set_ithresh(p, QMAN_PIRQ_MR_ITHRESH);
1227 qm_out(p, QM_REG_ITPR, QMAN_PIRQ_IPERIOD);
1228 portal->cgrs = kmalloc_array(2, sizeof(*cgrs), GFP_KERNEL);
1229 if (!portal->cgrs)
1230 goto fail_cgrs;
1231 /* initial snapshot is no-depletion */
1232 qman_cgrs_init(&portal->cgrs[1]);
1233 if (cgrs)
1234 portal->cgrs[0] = *cgrs;
1235 else
1236 /* if the given mask is NULL, assume all CGRs can be seen */
1237 qman_cgrs_fill(&portal->cgrs[0]);
1238 INIT_LIST_HEAD(&portal->cgr_cbs);
1239 spin_lock_init(&portal->cgr_lock);
1240 INIT_WORK(&portal->congestion_work, qm_congestion_task);
1241 INIT_WORK(&portal->mr_work, qm_mr_process_task);
1242 portal->bits = 0;
1243 portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
1244 QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
1245 QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
1246 isdr = 0xffffffff;
1247 qm_out(p, QM_REG_ISDR, isdr);
1248 portal->irq_sources = 0;
1249 qm_out(p, QM_REG_IER, 0);
1250 qm_out(p, QM_REG_ISR, 0xffffffff);
1251 snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
1252 if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
1253 dev_err(c->dev, "request_irq() failed\n");
1254 goto fail_irq;
1255 }
1256
1257 if (dpaa_set_portal_irq_affinity(c->dev, c->irq, c->cpu))
1258 goto fail_affinity;
1259
1260 /* Need EQCR to be empty before continuing */
1261 isdr &= ~QM_PIRQ_EQCI;
1262 qm_out(p, QM_REG_ISDR, isdr);
1263 ret = qm_eqcr_get_fill(p);
1264 if (ret) {
1265 dev_err(c->dev, "EQCR unclean\n");
1266 goto fail_eqcr_empty;
1267 }
1268 isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
1269 qm_out(p, QM_REG_ISDR, isdr);
1270 if (qm_dqrr_current(p)) {
1271 dev_err(c->dev, "DQRR unclean\n");
1272 qm_dqrr_cdc_consume_n(p, 0xffff);
1273 }
1274 if (qm_mr_current(p) && drain_mr_fqrni(p)) {
1275 /* special handling, drain just in case it's a few FQRNIs */
1276 const union qm_mr_entry *e = qm_mr_current(p);
1277
1278 dev_err(c->dev, "MR dirty, VB 0x%x, rc 0x%x, addr 0x%llx\n",
1279 e->verb, e->ern.rc, qm_fd_addr_get64(&e->ern.fd));
1280 goto fail_dqrr_mr_empty;
1281 }
1282 /* Success */
1283 portal->config = c;
1284 qm_out(p, QM_REG_ISDR, 0);
1285 qm_out(p, QM_REG_IIR, 0);
1286 /* Write a sane SDQCR */
1287 qm_dqrr_sdqcr_set(p, portal->sdqcr);
1288 return 0;
1289
1290 fail_dqrr_mr_empty:
1291 fail_eqcr_empty:
1292 fail_affinity:
1293 free_irq(c->irq, portal);
1294 fail_irq:
1295 kfree(portal->cgrs);
1296 fail_cgrs:
1297 qm_mc_finish(p);
1298 fail_mc:
1299 qm_mr_finish(p);
1300 fail_mr:
1301 qm_dqrr_finish(p);
1302 fail_dqrr:
1303 qm_eqcr_finish(p);
1304 fail_eqcr:
1305 return -EIO;
1306 }
1307
1308 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
1309 const struct qman_cgrs *cgrs)
1310 {
1311 struct qman_portal *portal;
1312 int err;
1313
1314 portal = &per_cpu(qman_affine_portal, c->cpu);
1315 err = qman_create_portal(portal, c, cgrs);
1316 if (err)
1317 return NULL;
1318
1319 spin_lock(&affine_mask_lock);
1320 cpumask_set_cpu(c->cpu, &affine_mask);
1321 affine_channels[c->cpu] = c->channel;
1322 affine_portals[c->cpu] = portal;
1323 spin_unlock(&affine_mask_lock);
1324
1325 return portal;
1326 }
1327
1328 static void qman_destroy_portal(struct qman_portal *qm)
1329 {
1330 const struct qm_portal_config *pcfg;
1331
1332 /* Stop dequeues on the portal */
1333 qm_dqrr_sdqcr_set(&qm->p, 0);
1334
1335 /*
1336 * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
1337 * something related to QM_PIRQ_EQCI, this may need fixing.
1338 * Also, due to the prefetching model used for CI updates in the enqueue
1339 * path, this update will only invalidate the CI cacheline *after*
1340 * working on it, so we need to call this twice to ensure a full update
1341 * irrespective of where the enqueue processing was at when the teardown
1342 * began.
1343 */
1344 qm_eqcr_cce_update(&qm->p);
1345 qm_eqcr_cce_update(&qm->p);
1346 pcfg = qm->config;
1347
1348 free_irq(pcfg->irq, qm);
1349
1350 kfree(qm->cgrs);
1351 qm_mc_finish(&qm->p);
1352 qm_mr_finish(&qm->p);
1353 qm_dqrr_finish(&qm->p);
1354 qm_eqcr_finish(&qm->p);
1355
1356 qm->config = NULL;
1357 }
1358
1359 const struct qm_portal_config *qman_destroy_affine_portal(void)
1360 {
1361 struct qman_portal *qm = get_affine_portal();
1362 const struct qm_portal_config *pcfg;
1363 int cpu;
1364
1365 pcfg = qm->config;
1366 cpu = pcfg->cpu;
1367
1368 qman_destroy_portal(qm);
1369
1370 spin_lock(&affine_mask_lock);
1371 cpumask_clear_cpu(cpu, &affine_mask);
1372 spin_unlock(&affine_mask_lock);
1373 put_affine_portal();
1374 return pcfg;
1375 }
1376
1377 /* Inline helper to reduce nesting in __poll_portal_slow() */
1378 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
1379 const union qm_mr_entry *msg, u8 verb)
1380 {
1381 switch (verb) {
1382 case QM_MR_VERB_FQRL:
1383 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
1384 fq_clear(fq, QMAN_FQ_STATE_ORL);
1385 break;
1386 case QM_MR_VERB_FQRN:
1387 DPAA_ASSERT(fq->state == qman_fq_state_parked ||
1388 fq->state == qman_fq_state_sched);
1389 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
1390 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
1391 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
1392 fq_set(fq, QMAN_FQ_STATE_NE);
1393 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
1394 fq_set(fq, QMAN_FQ_STATE_ORL);
1395 fq->state = qman_fq_state_retired;
1396 break;
1397 case QM_MR_VERB_FQPN:
1398 DPAA_ASSERT(fq->state == qman_fq_state_sched);
1399 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
1400 fq->state = qman_fq_state_parked;
1401 }
1402 }
1403
1404 static void qm_congestion_task(struct work_struct *work)
1405 {
1406 struct qman_portal *p = container_of(work, struct qman_portal,
1407 congestion_work);
1408 struct qman_cgrs rr, c;
1409 union qm_mc_result *mcr;
1410 struct qman_cgr *cgr;
1411
1412 spin_lock(&p->cgr_lock);
1413 qm_mc_start(&p->p);
1414 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1415 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1416 spin_unlock(&p->cgr_lock);
1417 dev_crit(p->config->dev, "QUERYCONGESTION timeout\n");
1418 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
1419 return;
1420 }
1421 /* mask out the ones I'm not interested in */
1422 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state,
1423 &p->cgrs[0]);
1424 /* check previous snapshot for delta, enter/exit congestion */
1425 qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
1426 /* update snapshot */
1427 qman_cgrs_cp(&p->cgrs[1], &rr);
1428 /* Invoke callback */
1429 list_for_each_entry(cgr, &p->cgr_cbs, node)
1430 if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
1431 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
1432 spin_unlock(&p->cgr_lock);
1433 qman_p_irqsource_add(p, QM_PIRQ_CSCI);
1434 }
1435
1436 static void qm_mr_process_task(struct work_struct *work)
1437 {
1438 struct qman_portal *p = container_of(work, struct qman_portal,
1439 mr_work);
1440 const union qm_mr_entry *msg;
1441 struct qman_fq *fq;
1442 u8 verb, num = 0;
1443
1444 preempt_disable();
1445
1446 while (1) {
1447 qm_mr_pvb_update(&p->p);
1448 msg = qm_mr_current(&p->p);
1449 if (!msg)
1450 break;
1451
1452 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
1453 /* The message is a software ERN iff the 0x20 bit is clear */
1454 if (verb & 0x20) {
1455 switch (verb) {
1456 case QM_MR_VERB_FQRNI:
1457 /* nada, we drop FQRNIs on the floor */
1458 break;
1459 case QM_MR_VERB_FQRN:
1460 case QM_MR_VERB_FQRL:
1461 /* Lookup in the retirement table */
1462 fq = fqid_to_fq(qm_fqid_get(&msg->fq));
1463 if (WARN_ON(!fq))
1464 break;
1465 fq_state_change(p, fq, msg, verb);
1466 if (fq->cb.fqs)
1467 fq->cb.fqs(p, fq, msg);
1468 break;
1469 case QM_MR_VERB_FQPN:
1470 /* Parked */
1471 fq = tag_to_fq(be32_to_cpu(msg->fq.context_b));
1472 fq_state_change(p, fq, msg, verb);
1473 if (fq->cb.fqs)
1474 fq->cb.fqs(p, fq, msg);
1475 break;
1476 case QM_MR_VERB_DC_ERN:
1477 /* DCP ERN */
1478 pr_crit_once("Leaking DCP ERNs!\n");
1479 break;
1480 default:
1481 pr_crit("Invalid MR verb 0x%02x\n", verb);
1482 }
1483 } else {
1484 /* Its a software ERN */
1485 fq = tag_to_fq(be32_to_cpu(msg->ern.tag));
1486 fq->cb.ern(p, fq, msg);
1487 }
1488 num++;
1489 qm_mr_next(&p->p);
1490 }
1491
1492 qm_mr_cci_consume(&p->p, num);
1493 qman_p_irqsource_add(p, QM_PIRQ_MRI);
1494 preempt_enable();
1495 }
1496
1497 static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
1498 {
1499 if (is & QM_PIRQ_CSCI) {
1500 qman_p_irqsource_remove(p, QM_PIRQ_CSCI);
1501 queue_work_on(smp_processor_id(), qm_portal_wq,
1502 &p->congestion_work);
1503 }
1504
1505 if (is & QM_PIRQ_EQRI) {
1506 qm_eqcr_cce_update(&p->p);
1507 qm_eqcr_set_ithresh(&p->p, 0);
1508 wake_up(&affine_queue);
1509 }
1510
1511 if (is & QM_PIRQ_MRI) {
1512 qman_p_irqsource_remove(p, QM_PIRQ_MRI);
1513 queue_work_on(smp_processor_id(), qm_portal_wq,
1514 &p->mr_work);
1515 }
1516
1517 return is;
1518 }
1519
1520 /*
1521 * remove some slowish-path stuff from the "fast path" and make sure it isn't
1522 * inlined.
1523 */
1524 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
1525 {
1526 p->vdqcr_owned = NULL;
1527 fq_clear(fq, QMAN_FQ_STATE_VDQCR);
1528 wake_up(&affine_queue);
1529 }
1530
1531 /*
1532 * The only states that would conflict with other things if they ran at the
1533 * same time on the same cpu are:
1534 *
1535 * (i) setting/clearing vdqcr_owned, and
1536 * (ii) clearing the NE (Not Empty) flag.
1537 *
1538 * Both are safe. Because;
1539 *
1540 * (i) this clearing can only occur after qman_volatile_dequeue() has set the
1541 * vdqcr_owned field (which it does before setting VDQCR), and
1542 * qman_volatile_dequeue() blocks interrupts and preemption while this is
1543 * done so that we can't interfere.
1544 * (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
1545 * with (i) that API prevents us from interfering until it's safe.
1546 *
1547 * The good thing is that qman_volatile_dequeue() and qman_retire_fq() run far
1548 * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
1549 * advantage comes from this function not having to "lock" anything at all.
1550 *
1551 * Note also that the callbacks are invoked at points which are safe against the
1552 * above potential conflicts, but that this function itself is not re-entrant
1553 * (this is because the function tracks one end of each FIFO in the portal and
1554 * we do *not* want to lock that). So the consequence is that it is safe for
1555 * user callbacks to call into any QMan API.
1556 */
1557 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
1558 unsigned int poll_limit)
1559 {
1560 const struct qm_dqrr_entry *dq;
1561 struct qman_fq *fq;
1562 enum qman_cb_dqrr_result res;
1563 unsigned int limit = 0;
1564
1565 do {
1566 qm_dqrr_pvb_update(&p->p);
1567 dq = qm_dqrr_current(&p->p);
1568 if (!dq)
1569 break;
1570
1571 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
1572 /*
1573 * VDQCR: don't trust context_b as the FQ may have
1574 * been configured for h/w consumption and we're
1575 * draining it post-retirement.
1576 */
1577 fq = p->vdqcr_owned;
1578 /*
1579 * We only set QMAN_FQ_STATE_NE when retiring, so we
1580 * only need to check for clearing it when doing
1581 * volatile dequeues. It's one less thing to check
1582 * in the critical path (SDQCR).
1583 */
1584 if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1585 fq_clear(fq, QMAN_FQ_STATE_NE);
1586 /*
1587 * This is duplicated from the SDQCR code, but we
1588 * have stuff to do before *and* after this callback,
1589 * and we don't want multiple if()s in the critical
1590 * path (SDQCR).
1591 */
1592 res = fq->cb.dqrr(p, fq, dq);
1593 if (res == qman_cb_dqrr_stop)
1594 break;
1595 /* Check for VDQCR completion */
1596 if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1597 clear_vdqcr(p, fq);
1598 } else {
1599 /* SDQCR: context_b points to the FQ */
1600 fq = tag_to_fq(be32_to_cpu(dq->context_b));
1601 /* Now let the callback do its stuff */
1602 res = fq->cb.dqrr(p, fq, dq);
1603 /*
1604 * The callback can request that we exit without
1605 * consuming this entry nor advancing;
1606 */
1607 if (res == qman_cb_dqrr_stop)
1608 break;
1609 }
1610 /* Interpret 'dq' from a driver perspective. */
1611 /*
1612 * Parking isn't possible unless HELDACTIVE was set. NB,
1613 * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1614 * check for HELDACTIVE to cover both.
1615 */
1616 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1617 (res != qman_cb_dqrr_park));
1618 /* just means "skip it, I'll consume it myself later on" */
1619 if (res != qman_cb_dqrr_defer)
1620 qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1621 res == qman_cb_dqrr_park);
1622 /* Move forward */
1623 qm_dqrr_next(&p->p);
1624 /*
1625 * Entry processed and consumed, increment our counter. The
1626 * callback can request that we exit after consuming the
1627 * entry, and we also exit if we reach our processing limit,
1628 * so loop back only if neither of these conditions is met.
1629 */
1630 } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1631
1632 return limit;
1633 }
1634
1635 void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
1636 {
1637 unsigned long irqflags;
1638
1639 local_irq_save(irqflags);
1640 p->irq_sources |= bits & QM_PIRQ_VISIBLE;
1641 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1642 local_irq_restore(irqflags);
1643 }
1644 EXPORT_SYMBOL(qman_p_irqsource_add);
1645
1646 void qman_p_irqsource_remove(struct qman_portal *p, u32 bits)
1647 {
1648 unsigned long irqflags;
1649 u32 ier;
1650
1651 /*
1652 * Our interrupt handler only processes+clears status register bits that
1653 * are in p->irq_sources. As we're trimming that mask, if one of them
1654 * were to assert in the status register just before we remove it from
1655 * the enable register, there would be an interrupt-storm when we
1656 * release the IRQ lock. So we wait for the enable register update to
1657 * take effect in h/w (by reading it back) and then clear all other bits
1658 * in the status register. Ie. we clear them from ISR once it's certain
1659 * IER won't allow them to reassert.
1660 */
1661 local_irq_save(irqflags);
1662 bits &= QM_PIRQ_VISIBLE;
1663 p->irq_sources &= ~bits;
1664 qm_out(&p->p, QM_REG_IER, p->irq_sources);
1665 ier = qm_in(&p->p, QM_REG_IER);
1666 /*
1667 * Using "~ier" (rather than "bits" or "~p->irq_sources") creates a
1668 * data-dependency, ie. to protect against re-ordering.
1669 */
1670 qm_out(&p->p, QM_REG_ISR, ~ier);
1671 local_irq_restore(irqflags);
1672 }
1673 EXPORT_SYMBOL(qman_p_irqsource_remove);
1674
1675 const cpumask_t *qman_affine_cpus(void)
1676 {
1677 return &affine_mask;
1678 }
1679 EXPORT_SYMBOL(qman_affine_cpus);
1680
1681 u16 qman_affine_channel(int cpu)
1682 {
1683 if (cpu < 0) {
1684 struct qman_portal *portal = get_affine_portal();
1685
1686 cpu = portal->config->cpu;
1687 put_affine_portal();
1688 }
1689 WARN_ON(!cpumask_test_cpu(cpu, &affine_mask));
1690 return affine_channels[cpu];
1691 }
1692 EXPORT_SYMBOL(qman_affine_channel);
1693
1694 struct qman_portal *qman_get_affine_portal(int cpu)
1695 {
1696 return affine_portals[cpu];
1697 }
1698 EXPORT_SYMBOL(qman_get_affine_portal);
1699
1700 int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit)
1701 {
1702 return __poll_portal_fast(p, limit);
1703 }
1704 EXPORT_SYMBOL(qman_p_poll_dqrr);
1705
1706 void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools)
1707 {
1708 unsigned long irqflags;
1709
1710 local_irq_save(irqflags);
1711 pools &= p->config->pools;
1712 p->sdqcr |= pools;
1713 qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1714 local_irq_restore(irqflags);
1715 }
1716 EXPORT_SYMBOL(qman_p_static_dequeue_add);
1717
1718 /* Frame queue API */
1719
1720 static const char *mcr_result_str(u8 result)
1721 {
1722 switch (result) {
1723 case QM_MCR_RESULT_NULL:
1724 return "QM_MCR_RESULT_NULL";
1725 case QM_MCR_RESULT_OK:
1726 return "QM_MCR_RESULT_OK";
1727 case QM_MCR_RESULT_ERR_FQID:
1728 return "QM_MCR_RESULT_ERR_FQID";
1729 case QM_MCR_RESULT_ERR_FQSTATE:
1730 return "QM_MCR_RESULT_ERR_FQSTATE";
1731 case QM_MCR_RESULT_ERR_NOTEMPTY:
1732 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1733 case QM_MCR_RESULT_PENDING:
1734 return "QM_MCR_RESULT_PENDING";
1735 case QM_MCR_RESULT_ERR_BADCOMMAND:
1736 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1737 }
1738 return "<unknown MCR result>";
1739 }
1740
1741 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1742 {
1743 if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1744 int ret = qman_alloc_fqid(&fqid);
1745
1746 if (ret)
1747 return ret;
1748 }
1749 fq->fqid = fqid;
1750 fq->flags = flags;
1751 fq->state = qman_fq_state_oos;
1752 fq->cgr_groupid = 0;
1753
1754 /* A context_b of 0 is allegedly special, so don't use that fqid */
1755 if (fqid == 0 || fqid >= num_fqids) {
1756 WARN(1, "bad fqid %d\n", fqid);
1757 return -EINVAL;
1758 }
1759
1760 fq->idx = fqid * 2;
1761 if (flags & QMAN_FQ_FLAG_NO_MODIFY)
1762 fq->idx++;
1763
1764 WARN_ON(fq_table[fq->idx]);
1765 fq_table[fq->idx] = fq;
1766
1767 return 0;
1768 }
1769 EXPORT_SYMBOL(qman_create_fq);
1770
1771 void qman_destroy_fq(struct qman_fq *fq)
1772 {
1773 /*
1774 * We don't need to lock the FQ as it is a pre-condition that the FQ be
1775 * quiesced. Instead, run some checks.
1776 */
1777 switch (fq->state) {
1778 case qman_fq_state_parked:
1779 case qman_fq_state_oos:
1780 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1781 qman_release_fqid(fq->fqid);
1782
1783 DPAA_ASSERT(fq_table[fq->idx]);
1784 fq_table[fq->idx] = NULL;
1785 return;
1786 default:
1787 break;
1788 }
1789 DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1790 }
1791 EXPORT_SYMBOL(qman_destroy_fq);
1792
1793 u32 qman_fq_fqid(struct qman_fq *fq)
1794 {
1795 return fq->fqid;
1796 }
1797 EXPORT_SYMBOL(qman_fq_fqid);
1798
1799 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1800 {
1801 union qm_mc_command *mcc;
1802 union qm_mc_result *mcr;
1803 struct qman_portal *p;
1804 u8 res, myverb;
1805 int ret = 0;
1806
1807 myverb = (flags & QMAN_INITFQ_FLAG_SCHED)
1808 ? QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1809
1810 if (fq->state != qman_fq_state_oos &&
1811 fq->state != qman_fq_state_parked)
1812 return -EINVAL;
1813 #ifdef CONFIG_FSL_DPAA_CHECKING
1814 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1815 return -EINVAL;
1816 #endif
1817 if (opts && (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_OAC)) {
1818 /* And can't be set at the same time as TDTHRESH */
1819 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_TDTHRESH)
1820 return -EINVAL;
1821 }
1822 /* Issue an INITFQ_[PARKED|SCHED] management command */
1823 p = get_affine_portal();
1824 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1825 (fq->state != qman_fq_state_oos &&
1826 fq->state != qman_fq_state_parked)) {
1827 ret = -EBUSY;
1828 goto out;
1829 }
1830 mcc = qm_mc_start(&p->p);
1831 if (opts)
1832 mcc->initfq = *opts;
1833 qm_fqid_set(&mcc->fq, fq->fqid);
1834 mcc->initfq.count = 0;
1835 /*
1836 * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a
1837 * demux pointer. Otherwise, the caller-provided value is allowed to
1838 * stand, don't overwrite it.
1839 */
1840 if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1841 dma_addr_t phys_fq;
1842
1843 mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB);
1844 mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq));
1845 /*
1846 * and the physical address - NB, if the user wasn't trying to
1847 * set CONTEXTA, clear the stashing settings.
1848 */
1849 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1850 QM_INITFQ_WE_CONTEXTA)) {
1851 mcc->initfq.we_mask |=
1852 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1853 memset(&mcc->initfq.fqd.context_a, 0,
1854 sizeof(mcc->initfq.fqd.context_a));
1855 } else {
1856 struct qman_portal *p = qman_dma_portal;
1857
1858 phys_fq = dma_map_single(p->config->dev, fq,
1859 sizeof(*fq), DMA_TO_DEVICE);
1860 if (dma_mapping_error(p->config->dev, phys_fq)) {
1861 dev_err(p->config->dev, "dma_mapping failed\n");
1862 ret = -EIO;
1863 goto out;
1864 }
1865
1866 qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1867 }
1868 }
1869 if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1870 int wq = 0;
1871
1872 if (!(be16_to_cpu(mcc->initfq.we_mask) &
1873 QM_INITFQ_WE_DESTWQ)) {
1874 mcc->initfq.we_mask |=
1875 cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1876 wq = 4;
1877 }
1878 qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);
1879 }
1880 qm_mc_commit(&p->p, myverb);
1881 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1882 dev_err(p->config->dev, "MCR timeout\n");
1883 ret = -ETIMEDOUT;
1884 goto out;
1885 }
1886
1887 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1888 res = mcr->result;
1889 if (res != QM_MCR_RESULT_OK) {
1890 ret = -EIO;
1891 goto out;
1892 }
1893 if (opts) {
1894 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) {
1895 if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE)
1896 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1897 else
1898 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1899 }
1900 if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_CGID)
1901 fq->cgr_groupid = opts->fqd.cgid;
1902 }
1903 fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1904 qman_fq_state_sched : qman_fq_state_parked;
1905
1906 out:
1907 put_affine_portal();
1908 return ret;
1909 }
1910 EXPORT_SYMBOL(qman_init_fq);
1911
1912 int qman_schedule_fq(struct qman_fq *fq)
1913 {
1914 union qm_mc_command *mcc;
1915 union qm_mc_result *mcr;
1916 struct qman_portal *p;
1917 int ret = 0;
1918
1919 if (fq->state != qman_fq_state_parked)
1920 return -EINVAL;
1921 #ifdef CONFIG_FSL_DPAA_CHECKING
1922 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1923 return -EINVAL;
1924 #endif
1925 /* Issue a ALTERFQ_SCHED management command */
1926 p = get_affine_portal();
1927 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1928 fq->state != qman_fq_state_parked) {
1929 ret = -EBUSY;
1930 goto out;
1931 }
1932 mcc = qm_mc_start(&p->p);
1933 qm_fqid_set(&mcc->fq, fq->fqid);
1934 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1935 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1936 dev_err(p->config->dev, "ALTER_SCHED timeout\n");
1937 ret = -ETIMEDOUT;
1938 goto out;
1939 }
1940
1941 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1942 if (mcr->result != QM_MCR_RESULT_OK) {
1943 ret = -EIO;
1944 goto out;
1945 }
1946 fq->state = qman_fq_state_sched;
1947 out:
1948 put_affine_portal();
1949 return ret;
1950 }
1951 EXPORT_SYMBOL(qman_schedule_fq);
1952
1953 int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1954 {
1955 union qm_mc_command *mcc;
1956 union qm_mc_result *mcr;
1957 struct qman_portal *p;
1958 int ret;
1959 u8 res;
1960
1961 if (fq->state != qman_fq_state_parked &&
1962 fq->state != qman_fq_state_sched)
1963 return -EINVAL;
1964 #ifdef CONFIG_FSL_DPAA_CHECKING
1965 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
1966 return -EINVAL;
1967 #endif
1968 p = get_affine_portal();
1969 if (fq_isset(fq, QMAN_FQ_STATE_CHANGING) ||
1970 fq->state == qman_fq_state_retired ||
1971 fq->state == qman_fq_state_oos) {
1972 ret = -EBUSY;
1973 goto out;
1974 }
1975 mcc = qm_mc_start(&p->p);
1976 qm_fqid_set(&mcc->fq, fq->fqid);
1977 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1978 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1979 dev_crit(p->config->dev, "ALTER_RETIRE timeout\n");
1980 ret = -ETIMEDOUT;
1981 goto out;
1982 }
1983
1984 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
1985 res = mcr->result;
1986 /*
1987 * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
1988 * and defer the flags until FQRNI or FQRN (respectively) show up. But
1989 * "Friendly" is to process OK immediately, and not set CHANGING. We do
1990 * friendly, otherwise the caller doesn't necessarily have a fully
1991 * "retired" FQ on return even if the retirement was immediate. However
1992 * this does mean some code duplication between here and
1993 * fq_state_change().
1994 */
1995 if (res == QM_MCR_RESULT_OK) {
1996 ret = 0;
1997 /* Process 'fq' right away, we'll ignore FQRNI */
1998 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
1999 fq_set(fq, QMAN_FQ_STATE_NE);
2000 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
2001 fq_set(fq, QMAN_FQ_STATE_ORL);
2002 if (flags)
2003 *flags = fq->flags;
2004 fq->state = qman_fq_state_retired;
2005 if (fq->cb.fqs) {
2006 /*
2007 * Another issue with supporting "immediate" retirement
2008 * is that we're forced to drop FQRNIs, because by the
2009 * time they're seen it may already be "too late" (the
2010 * fq may have been OOS'd and free()'d already). But if
2011 * the upper layer wants a callback whether it's
2012 * immediate or not, we have to fake a "MR" entry to
2013 * look like an FQRNI...
2014 */
2015 union qm_mr_entry msg;
2016
2017 msg.verb = QM_MR_VERB_FQRNI;
2018 msg.fq.fqs = mcr->alterfq.fqs;
2019 qm_fqid_set(&msg.fq, fq->fqid);
2020 msg.fq.context_b = cpu_to_be32(fq_to_tag(fq));
2021 fq->cb.fqs(p, fq, &msg);
2022 }
2023 } else if (res == QM_MCR_RESULT_PENDING) {
2024 ret = 1;
2025 fq_set(fq, QMAN_FQ_STATE_CHANGING);
2026 } else {
2027 ret = -EIO;
2028 }
2029 out:
2030 put_affine_portal();
2031 return ret;
2032 }
2033 EXPORT_SYMBOL(qman_retire_fq);
2034
2035 int qman_oos_fq(struct qman_fq *fq)
2036 {
2037 union qm_mc_command *mcc;
2038 union qm_mc_result *mcr;
2039 struct qman_portal *p;
2040 int ret = 0;
2041
2042 if (fq->state != qman_fq_state_retired)
2043 return -EINVAL;
2044 #ifdef CONFIG_FSL_DPAA_CHECKING
2045 if (fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY))
2046 return -EINVAL;
2047 #endif
2048 p = get_affine_portal();
2049 if (fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS) ||
2050 fq->state != qman_fq_state_retired) {
2051 ret = -EBUSY;
2052 goto out;
2053 }
2054 mcc = qm_mc_start(&p->p);
2055 qm_fqid_set(&mcc->fq, fq->fqid);
2056 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2057 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2058 ret = -ETIMEDOUT;
2059 goto out;
2060 }
2061 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
2062 if (mcr->result != QM_MCR_RESULT_OK) {
2063 ret = -EIO;
2064 goto out;
2065 }
2066 fq->state = qman_fq_state_oos;
2067 out:
2068 put_affine_portal();
2069 return ret;
2070 }
2071 EXPORT_SYMBOL(qman_oos_fq);
2072
2073 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
2074 {
2075 union qm_mc_command *mcc;
2076 union qm_mc_result *mcr;
2077 struct qman_portal *p = get_affine_portal();
2078 int ret = 0;
2079
2080 mcc = qm_mc_start(&p->p);
2081 qm_fqid_set(&mcc->fq, fq->fqid);
2082 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2083 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2084 ret = -ETIMEDOUT;
2085 goto out;
2086 }
2087
2088 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2089 if (mcr->result == QM_MCR_RESULT_OK)
2090 *fqd = mcr->queryfq.fqd;
2091 else
2092 ret = -EIO;
2093 out:
2094 put_affine_portal();
2095 return ret;
2096 }
2097
2098 int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
2099 {
2100 union qm_mc_command *mcc;
2101 union qm_mc_result *mcr;
2102 struct qman_portal *p = get_affine_portal();
2103 int ret = 0;
2104
2105 mcc = qm_mc_start(&p->p);
2106 qm_fqid_set(&mcc->fq, fq->fqid);
2107 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2108 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2109 ret = -ETIMEDOUT;
2110 goto out;
2111 }
2112
2113 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2114 if (mcr->result == QM_MCR_RESULT_OK)
2115 *np = mcr->queryfq_np;
2116 else if (mcr->result == QM_MCR_RESULT_ERR_FQID)
2117 ret = -ERANGE;
2118 else
2119 ret = -EIO;
2120 out:
2121 put_affine_portal();
2122 return ret;
2123 }
2124 EXPORT_SYMBOL(qman_query_fq_np);
2125
2126 static int qman_query_cgr(struct qman_cgr *cgr,
2127 struct qm_mcr_querycgr *cgrd)
2128 {
2129 union qm_mc_command *mcc;
2130 union qm_mc_result *mcr;
2131 struct qman_portal *p = get_affine_portal();
2132 int ret = 0;
2133
2134 mcc = qm_mc_start(&p->p);
2135 mcc->cgr.cgid = cgr->cgrid;
2136 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
2137 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2138 ret = -ETIMEDOUT;
2139 goto out;
2140 }
2141 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
2142 if (mcr->result == QM_MCR_RESULT_OK)
2143 *cgrd = mcr->querycgr;
2144 else {
2145 dev_err(p->config->dev, "QUERY_CGR failed: %s\n",
2146 mcr_result_str(mcr->result));
2147 ret = -EIO;
2148 }
2149 out:
2150 put_affine_portal();
2151 return ret;
2152 }
2153
2154 int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result)
2155 {
2156 struct qm_mcr_querycgr query_cgr;
2157 int err;
2158
2159 err = qman_query_cgr(cgr, &query_cgr);
2160 if (err)
2161 return err;
2162
2163 *result = !!query_cgr.cgr.cs;
2164 return 0;
2165 }
2166 EXPORT_SYMBOL(qman_query_cgr_congested);
2167
2168 /* internal function used as a wait_event() expression */
2169 static int set_p_vdqcr(struct qman_portal *p, struct qman_fq *fq, u32 vdqcr)
2170 {
2171 unsigned long irqflags;
2172 int ret = -EBUSY;
2173
2174 local_irq_save(irqflags);
2175 if (p->vdqcr_owned)
2176 goto out;
2177 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2178 goto out;
2179
2180 fq_set(fq, QMAN_FQ_STATE_VDQCR);
2181 p->vdqcr_owned = fq;
2182 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2183 ret = 0;
2184 out:
2185 local_irq_restore(irqflags);
2186 return ret;
2187 }
2188
2189 static int set_vdqcr(struct qman_portal **p, struct qman_fq *fq, u32 vdqcr)
2190 {
2191 int ret;
2192
2193 *p = get_affine_portal();
2194 ret = set_p_vdqcr(*p, fq, vdqcr);
2195 put_affine_portal();
2196 return ret;
2197 }
2198
2199 static int wait_vdqcr_start(struct qman_portal **p, struct qman_fq *fq,
2200 u32 vdqcr, u32 flags)
2201 {
2202 int ret = 0;
2203
2204 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2205 ret = wait_event_interruptible(affine_queue,
2206 !set_vdqcr(p, fq, vdqcr));
2207 else
2208 wait_event(affine_queue, !set_vdqcr(p, fq, vdqcr));
2209 return ret;
2210 }
2211
2212 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr)
2213 {
2214 struct qman_portal *p;
2215 int ret;
2216
2217 if (fq->state != qman_fq_state_parked &&
2218 fq->state != qman_fq_state_retired)
2219 return -EINVAL;
2220 if (vdqcr & QM_VDQCR_FQID_MASK)
2221 return -EINVAL;
2222 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
2223 return -EBUSY;
2224 vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
2225 if (flags & QMAN_VOLATILE_FLAG_WAIT)
2226 ret = wait_vdqcr_start(&p, fq, vdqcr, flags);
2227 else
2228 ret = set_vdqcr(&p, fq, vdqcr);
2229 if (ret)
2230 return ret;
2231 /* VDQCR is set */
2232 if (flags & QMAN_VOLATILE_FLAG_FINISH) {
2233 if (flags & QMAN_VOLATILE_FLAG_WAIT_INT)
2234 /*
2235 * NB: don't propagate any error - the caller wouldn't
2236 * know whether the VDQCR was issued or not. A signal
2237 * could arrive after returning anyway, so the caller
2238 * can check signal_pending() if that's an issue.
2239 */
2240 wait_event_interruptible(affine_queue,
2241 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2242 else
2243 wait_event(affine_queue,
2244 !fq_isset(fq, QMAN_FQ_STATE_VDQCR));
2245 }
2246 return 0;
2247 }
2248 EXPORT_SYMBOL(qman_volatile_dequeue);
2249
2250 static void update_eqcr_ci(struct qman_portal *p, u8 avail)
2251 {
2252 if (avail)
2253 qm_eqcr_cce_prefetch(&p->p);
2254 else
2255 qm_eqcr_cce_update(&p->p);
2256 }
2257
2258 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd)
2259 {
2260 struct qman_portal *p;
2261 struct qm_eqcr_entry *eq;
2262 unsigned long irqflags;
2263 u8 avail;
2264
2265 p = get_affine_portal();
2266 local_irq_save(irqflags);
2267
2268 if (p->use_eqcr_ci_stashing) {
2269 /*
2270 * The stashing case is easy, only update if we need to in
2271 * order to try and liberate ring entries.
2272 */
2273 eq = qm_eqcr_start_stash(&p->p);
2274 } else {
2275 /*
2276 * The non-stashing case is harder, need to prefetch ahead of
2277 * time.
2278 */
2279 avail = qm_eqcr_get_avail(&p->p);
2280 if (avail < 2)
2281 update_eqcr_ci(p, avail);
2282 eq = qm_eqcr_start_no_stash(&p->p);
2283 }
2284
2285 if (unlikely(!eq))
2286 goto out;
2287
2288 qm_fqid_set(eq, fq->fqid);
2289 eq->tag = cpu_to_be32(fq_to_tag(fq));
2290 eq->fd = *fd;
2291
2292 qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE);
2293 out:
2294 local_irq_restore(irqflags);
2295 put_affine_portal();
2296 return 0;
2297 }
2298 EXPORT_SYMBOL(qman_enqueue);
2299
2300 static int qm_modify_cgr(struct qman_cgr *cgr, u32 flags,
2301 struct qm_mcc_initcgr *opts)
2302 {
2303 union qm_mc_command *mcc;
2304 union qm_mc_result *mcr;
2305 struct qman_portal *p = get_affine_portal();
2306 u8 verb = QM_MCC_VERB_MODIFYCGR;
2307 int ret = 0;
2308
2309 mcc = qm_mc_start(&p->p);
2310 if (opts)
2311 mcc->initcgr = *opts;
2312 mcc->initcgr.cgid = cgr->cgrid;
2313 if (flags & QMAN_CGR_FLAG_USE_INIT)
2314 verb = QM_MCC_VERB_INITCGR;
2315 qm_mc_commit(&p->p, verb);
2316 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2317 ret = -ETIMEDOUT;
2318 goto out;
2319 }
2320
2321 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2322 if (mcr->result != QM_MCR_RESULT_OK)
2323 ret = -EIO;
2324
2325 out:
2326 put_affine_portal();
2327 return ret;
2328 }
2329
2330 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
2331
2332 /* congestion state change notification target update control */
2333 static void qm_cgr_cscn_targ_set(struct __qm_mc_cgr *cgr, int pi, u32 val)
2334 {
2335 if (qman_ip_rev >= QMAN_REV30)
2336 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi |
2337 QM_CGR_TARG_UDP_CTRL_WRITE_BIT);
2338 else
2339 cgr->cscn_targ = cpu_to_be32(val | QM_CGR_TARG_PORTAL(pi));
2340 }
2341
2342 static void qm_cgr_cscn_targ_clear(struct __qm_mc_cgr *cgr, int pi, u32 val)
2343 {
2344 if (qman_ip_rev >= QMAN_REV30)
2345 cgr->cscn_targ_upd_ctrl = cpu_to_be16(pi);
2346 else
2347 cgr->cscn_targ = cpu_to_be32(val & ~QM_CGR_TARG_PORTAL(pi));
2348 }
2349
2350 static u8 qman_cgr_cpus[CGR_NUM];
2351
2352 void qman_init_cgr_all(void)
2353 {
2354 struct qman_cgr cgr;
2355 int err_cnt = 0;
2356
2357 for (cgr.cgrid = 0; cgr.cgrid < CGR_NUM; cgr.cgrid++) {
2358 if (qm_modify_cgr(&cgr, QMAN_CGR_FLAG_USE_INIT, NULL))
2359 err_cnt++;
2360 }
2361
2362 if (err_cnt)
2363 pr_err("Warning: %d error%s while initialising CGR h/w\n",
2364 err_cnt, (err_cnt > 1) ? "s" : "");
2365 }
2366
2367 int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2368 struct qm_mcc_initcgr *opts)
2369 {
2370 struct qm_mcr_querycgr cgr_state;
2371 int ret;
2372 struct qman_portal *p;
2373
2374 /*
2375 * We have to check that the provided CGRID is within the limits of the
2376 * data-structures, for obvious reasons. However we'll let h/w take
2377 * care of determining whether it's within the limits of what exists on
2378 * the SoC.
2379 */
2380 if (cgr->cgrid >= CGR_NUM)
2381 return -EINVAL;
2382
2383 preempt_disable();
2384 p = get_affine_portal();
2385 qman_cgr_cpus[cgr->cgrid] = smp_processor_id();
2386 preempt_enable();
2387
2388 cgr->chan = p->config->channel;
2389 spin_lock(&p->cgr_lock);
2390
2391 if (opts) {
2392 struct qm_mcc_initcgr local_opts = *opts;
2393
2394 ret = qman_query_cgr(cgr, &cgr_state);
2395 if (ret)
2396 goto out;
2397
2398 qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p),
2399 be32_to_cpu(cgr_state.cgr.cscn_targ));
2400 local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG);
2401
2402 /* send init if flags indicate so */
2403 if (flags & QMAN_CGR_FLAG_USE_INIT)
2404 ret = qm_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2405 &local_opts);
2406 else
2407 ret = qm_modify_cgr(cgr, 0, &local_opts);
2408 if (ret)
2409 goto out;
2410 }
2411
2412 list_add(&cgr->node, &p->cgr_cbs);
2413
2414 /* Determine if newly added object requires its callback to be called */
2415 ret = qman_query_cgr(cgr, &cgr_state);
2416 if (ret) {
2417 /* we can't go back, so proceed and return success */
2418 dev_err(p->config->dev, "CGR HW state partially modified\n");
2419 ret = 0;
2420 goto out;
2421 }
2422 if (cgr->cb && cgr_state.cgr.cscn_en &&
2423 qman_cgrs_get(&p->cgrs[1], cgr->cgrid))
2424 cgr->cb(p, cgr, 1);
2425 out:
2426 spin_unlock(&p->cgr_lock);
2427 put_affine_portal();
2428 return ret;
2429 }
2430 EXPORT_SYMBOL(qman_create_cgr);
2431
2432 int qman_delete_cgr(struct qman_cgr *cgr)
2433 {
2434 unsigned long irqflags;
2435 struct qm_mcr_querycgr cgr_state;
2436 struct qm_mcc_initcgr local_opts;
2437 int ret = 0;
2438 struct qman_cgr *i;
2439 struct qman_portal *p = get_affine_portal();
2440
2441 if (cgr->chan != p->config->channel) {
2442 /* attempt to delete from other portal than creator */
2443 dev_err(p->config->dev, "CGR not owned by current portal");
2444 dev_dbg(p->config->dev, " create 0x%x, delete 0x%x\n",
2445 cgr->chan, p->config->channel);
2446
2447 ret = -EINVAL;
2448 goto put_portal;
2449 }
2450 memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2451 spin_lock_irqsave(&p->cgr_lock, irqflags);
2452 list_del(&cgr->node);
2453 /*
2454 * If there are no other CGR objects for this CGRID in the list,
2455 * update CSCN_TARG accordingly
2456 */
2457 list_for_each_entry(i, &p->cgr_cbs, node)
2458 if (i->cgrid == cgr->cgrid && i->cb)
2459 goto release_lock;
2460 ret = qman_query_cgr(cgr, &cgr_state);
2461 if (ret) {
2462 /* add back to the list */
2463 list_add(&cgr->node, &p->cgr_cbs);
2464 goto release_lock;
2465 }
2466
2467 local_opts.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_TARG);
2468 qm_cgr_cscn_targ_clear(&local_opts.cgr, PORTAL_IDX(p),
2469 be32_to_cpu(cgr_state.cgr.cscn_targ));
2470
2471 ret = qm_modify_cgr(cgr, 0, &local_opts);
2472 if (ret)
2473 /* add back to the list */
2474 list_add(&cgr->node, &p->cgr_cbs);
2475 release_lock:
2476 spin_unlock_irqrestore(&p->cgr_lock, irqflags);
2477 put_portal:
2478 put_affine_portal();
2479 return ret;
2480 }
2481 EXPORT_SYMBOL(qman_delete_cgr);
2482
2483 struct cgr_comp {
2484 struct qman_cgr *cgr;
2485 struct completion completion;
2486 };
2487
2488 static void qman_delete_cgr_smp_call(void *p)
2489 {
2490 qman_delete_cgr((struct qman_cgr *)p);
2491 }
2492
2493 void qman_delete_cgr_safe(struct qman_cgr *cgr)
2494 {
2495 preempt_disable();
2496 if (qman_cgr_cpus[cgr->cgrid] != smp_processor_id()) {
2497 smp_call_function_single(qman_cgr_cpus[cgr->cgrid],
2498 qman_delete_cgr_smp_call, cgr, true);
2499 preempt_enable();
2500 return;
2501 }
2502
2503 qman_delete_cgr(cgr);
2504 preempt_enable();
2505 }
2506 EXPORT_SYMBOL(qman_delete_cgr_safe);
2507
2508 /* Cleanup FQs */
2509
2510 static int _qm_mr_consume_and_match_verb(struct qm_portal *p, int v)
2511 {
2512 const union qm_mr_entry *msg;
2513 int found = 0;
2514
2515 qm_mr_pvb_update(p);
2516 msg = qm_mr_current(p);
2517 while (msg) {
2518 if ((msg->verb & QM_MR_VERB_TYPE_MASK) == v)
2519 found = 1;
2520 qm_mr_next(p);
2521 qm_mr_cci_consume_to_current(p);
2522 qm_mr_pvb_update(p);
2523 msg = qm_mr_current(p);
2524 }
2525 return found;
2526 }
2527
2528 static int _qm_dqrr_consume_and_match(struct qm_portal *p, u32 fqid, int s,
2529 bool wait)
2530 {
2531 const struct qm_dqrr_entry *dqrr;
2532 int found = 0;
2533
2534 do {
2535 qm_dqrr_pvb_update(p);
2536 dqrr = qm_dqrr_current(p);
2537 if (!dqrr)
2538 cpu_relax();
2539 } while (wait && !dqrr);
2540
2541 while (dqrr) {
2542 if (qm_fqid_get(dqrr) == fqid && (dqrr->stat & s))
2543 found = 1;
2544 qm_dqrr_cdc_consume_1ptr(p, dqrr, 0);
2545 qm_dqrr_pvb_update(p);
2546 qm_dqrr_next(p);
2547 dqrr = qm_dqrr_current(p);
2548 }
2549 return found;
2550 }
2551
2552 #define qm_mr_drain(p, V) \
2553 _qm_mr_consume_and_match_verb(p, QM_MR_VERB_##V)
2554
2555 #define qm_dqrr_drain(p, f, S) \
2556 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, false)
2557
2558 #define qm_dqrr_drain_wait(p, f, S) \
2559 _qm_dqrr_consume_and_match(p, f, QM_DQRR_STAT_##S, true)
2560
2561 #define qm_dqrr_drain_nomatch(p) \
2562 _qm_dqrr_consume_and_match(p, 0, 0, false)
2563
2564 static int qman_shutdown_fq(u32 fqid)
2565 {
2566 struct qman_portal *p;
2567 struct device *dev;
2568 union qm_mc_command *mcc;
2569 union qm_mc_result *mcr;
2570 int orl_empty, drain = 0, ret = 0;
2571 u32 channel, wq, res;
2572 u8 state;
2573
2574 p = get_affine_portal();
2575 dev = p->config->dev;
2576 /* Determine the state of the FQID */
2577 mcc = qm_mc_start(&p->p);
2578 qm_fqid_set(&mcc->fq, fqid);
2579 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
2580 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2581 dev_err(dev, "QUERYFQ_NP timeout\n");
2582 ret = -ETIMEDOUT;
2583 goto out;
2584 }
2585
2586 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2587 state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2588 if (state == QM_MCR_NP_STATE_OOS)
2589 goto out; /* Already OOS, no need to do anymore checks */
2590
2591 /* Query which channel the FQ is using */
2592 mcc = qm_mc_start(&p->p);
2593 qm_fqid_set(&mcc->fq, fqid);
2594 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
2595 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2596 dev_err(dev, "QUERYFQ timeout\n");
2597 ret = -ETIMEDOUT;
2598 goto out;
2599 }
2600
2601 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2602 /* Need to store these since the MCR gets reused */
2603 channel = qm_fqd_get_chan(&mcr->queryfq.fqd);
2604 wq = qm_fqd_get_wq(&mcr->queryfq.fqd);
2605
2606 switch (state) {
2607 case QM_MCR_NP_STATE_TEN_SCHED:
2608 case QM_MCR_NP_STATE_TRU_SCHED:
2609 case QM_MCR_NP_STATE_ACTIVE:
2610 case QM_MCR_NP_STATE_PARKED:
2611 orl_empty = 0;
2612 mcc = qm_mc_start(&p->p);
2613 qm_fqid_set(&mcc->fq, fqid);
2614 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
2615 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2616 dev_err(dev, "QUERYFQ_NP timeout\n");
2617 ret = -ETIMEDOUT;
2618 goto out;
2619 }
2620 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2621 QM_MCR_VERB_ALTER_RETIRE);
2622 res = mcr->result; /* Make a copy as we reuse MCR below */
2623
2624 if (res == QM_MCR_RESULT_PENDING) {
2625 /*
2626 * Need to wait for the FQRN in the message ring, which
2627 * will only occur once the FQ has been drained. In
2628 * order for the FQ to drain the portal needs to be set
2629 * to dequeue from the channel the FQ is scheduled on
2630 */
2631 int found_fqrn = 0;
2632 u16 dequeue_wq = 0;
2633
2634 /* Flag that we need to drain FQ */
2635 drain = 1;
2636
2637 if (channel >= qm_channel_pool1 &&
2638 channel < qm_channel_pool1 + 15) {
2639 /* Pool channel, enable the bit in the portal */
2640 dequeue_wq = (channel -
2641 qm_channel_pool1 + 1)<<4 | wq;
2642 } else if (channel < qm_channel_pool1) {
2643 /* Dedicated channel */
2644 dequeue_wq = wq;
2645 } else {
2646 dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x",
2647 fqid, channel);
2648 ret = -EBUSY;
2649 goto out;
2650 }
2651 /* Set the sdqcr to drain this channel */
2652 if (channel < qm_channel_pool1)
2653 qm_dqrr_sdqcr_set(&p->p,
2654 QM_SDQCR_TYPE_ACTIVE |
2655 QM_SDQCR_CHANNELS_DEDICATED);
2656 else
2657 qm_dqrr_sdqcr_set(&p->p,
2658 QM_SDQCR_TYPE_ACTIVE |
2659 QM_SDQCR_CHANNELS_POOL_CONV
2660 (channel));
2661 do {
2662 /* Keep draining DQRR while checking the MR*/
2663 qm_dqrr_drain_nomatch(&p->p);
2664 /* Process message ring too */
2665 found_fqrn = qm_mr_drain(&p->p, FQRN);
2666 cpu_relax();
2667 } while (!found_fqrn);
2668
2669 }
2670 if (res != QM_MCR_RESULT_OK &&
2671 res != QM_MCR_RESULT_PENDING) {
2672 dev_err(dev, "retire_fq failed: FQ 0x%x, res=0x%x\n",
2673 fqid, res);
2674 ret = -EIO;
2675 goto out;
2676 }
2677 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2678 /*
2679 * ORL had no entries, no need to wait until the
2680 * ERNs come in
2681 */
2682 orl_empty = 1;
2683 }
2684 /*
2685 * Retirement succeeded, check to see if FQ needs
2686 * to be drained
2687 */
2688 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2689 /* FQ is Not Empty, drain using volatile DQ commands */
2690 do {
2691 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2692
2693 qm_dqrr_vdqcr_set(&p->p, vdqcr);
2694 /*
2695 * Wait for a dequeue and process the dequeues,
2696 * making sure to empty the ring completely
2697 */
2698 } while (qm_dqrr_drain_wait(&p->p, fqid, FQ_EMPTY));
2699 }
2700 qm_dqrr_sdqcr_set(&p->p, 0);
2701
2702 while (!orl_empty) {
2703 /* Wait for the ORL to have been completely drained */
2704 orl_empty = qm_mr_drain(&p->p, FQRL);
2705 cpu_relax();
2706 }
2707 mcc = qm_mc_start(&p->p);
2708 qm_fqid_set(&mcc->fq, fqid);
2709 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2710 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2711 ret = -ETIMEDOUT;
2712 goto out;
2713 }
2714
2715 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2716 QM_MCR_VERB_ALTER_OOS);
2717 if (mcr->result != QM_MCR_RESULT_OK) {
2718 dev_err(dev, "OOS after drain fail: FQ 0x%x (0x%x)\n",
2719 fqid, mcr->result);
2720 ret = -EIO;
2721 goto out;
2722 }
2723 break;
2724
2725 case QM_MCR_NP_STATE_RETIRED:
2726 /* Send OOS Command */
2727 mcc = qm_mc_start(&p->p);
2728 qm_fqid_set(&mcc->fq, fqid);
2729 qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
2730 if (!qm_mc_result_timeout(&p->p, &mcr)) {
2731 ret = -ETIMEDOUT;
2732 goto out;
2733 }
2734
2735 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2736 QM_MCR_VERB_ALTER_OOS);
2737 if (mcr->result) {
2738 dev_err(dev, "OOS fail: FQ 0x%x (0x%x)\n",
2739 fqid, mcr->result);
2740 ret = -EIO;
2741 goto out;
2742 }
2743 break;
2744
2745 case QM_MCR_NP_STATE_OOS:
2746 /* Done */
2747 break;
2748
2749 default:
2750 ret = -EIO;
2751 }
2752
2753 out:
2754 put_affine_portal();
2755 return ret;
2756 }
2757
2758 const struct qm_portal_config *qman_get_qm_portal_config(
2759 struct qman_portal *portal)
2760 {
2761 return portal->config;
2762 }
2763 EXPORT_SYMBOL(qman_get_qm_portal_config);
2764
2765 struct gen_pool *qm_fqalloc; /* FQID allocator */
2766 struct gen_pool *qm_qpalloc; /* pool-channel allocator */
2767 struct gen_pool *qm_cgralloc; /* CGR ID allocator */
2768
2769 static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)
2770 {
2771 unsigned long addr;
2772
2773 if (!p)
2774 return -ENODEV;
2775
2776 addr = gen_pool_alloc(p, cnt);
2777 if (!addr)
2778 return -ENOMEM;
2779
2780 *result = addr & ~DPAA_GENALLOC_OFF;
2781
2782 return 0;
2783 }
2784
2785 int qman_alloc_fqid_range(u32 *result, u32 count)
2786 {
2787 return qman_alloc_range(qm_fqalloc, result, count);
2788 }
2789 EXPORT_SYMBOL(qman_alloc_fqid_range);
2790
2791 int qman_alloc_pool_range(u32 *result, u32 count)
2792 {
2793 return qman_alloc_range(qm_qpalloc, result, count);
2794 }
2795 EXPORT_SYMBOL(qman_alloc_pool_range);
2796
2797 int qman_alloc_cgrid_range(u32 *result, u32 count)
2798 {
2799 return qman_alloc_range(qm_cgralloc, result, count);
2800 }
2801 EXPORT_SYMBOL(qman_alloc_cgrid_range);
2802
2803 int qman_release_fqid(u32 fqid)
2804 {
2805 int ret = qman_shutdown_fq(fqid);
2806
2807 if (ret) {
2808 pr_debug("FQID %d leaked\n", fqid);
2809 return ret;
2810 }
2811
2812 gen_pool_free(qm_fqalloc, fqid | DPAA_GENALLOC_OFF, 1);
2813 return 0;
2814 }
2815 EXPORT_SYMBOL(qman_release_fqid);
2816
2817 static int qpool_cleanup(u32 qp)
2818 {
2819 /*
2820 * We query all FQDs starting from
2821 * FQID 1 until we get an "invalid FQID" error, looking for non-OOS FQDs
2822 * whose destination channel is the pool-channel being released.
2823 * When a non-OOS FQD is found we attempt to clean it up
2824 */
2825 struct qman_fq fq = {
2826 .fqid = QM_FQID_RANGE_START
2827 };
2828 int err;
2829
2830 do {
2831 struct qm_mcr_queryfq_np np;
2832
2833 err = qman_query_fq_np(&fq, &np);
2834 if (err == -ERANGE)
2835 /* FQID range exceeded, found no problems */
2836 return 0;
2837 else if (WARN_ON(err))
2838 return err;
2839
2840 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2841 struct qm_fqd fqd;
2842
2843 err = qman_query_fq(&fq, &fqd);
2844 if (WARN_ON(err))
2845 return err;
2846 if (qm_fqd_get_chan(&fqd) == qp) {
2847 /* The channel is the FQ's target, clean it */
2848 err = qman_shutdown_fq(fq.fqid);
2849 if (err)
2850 /*
2851 * Couldn't shut down the FQ
2852 * so the pool must be leaked
2853 */
2854 return err;
2855 }
2856 }
2857 /* Move to the next FQID */
2858 fq.fqid++;
2859 } while (1);
2860 }
2861
2862 int qman_release_pool(u32 qp)
2863 {
2864 int ret;
2865
2866 ret = qpool_cleanup(qp);
2867 if (ret) {
2868 pr_debug("CHID %d leaked\n", qp);
2869 return ret;
2870 }
2871
2872 gen_pool_free(qm_qpalloc, qp | DPAA_GENALLOC_OFF, 1);
2873 return 0;
2874 }
2875 EXPORT_SYMBOL(qman_release_pool);
2876
2877 static int cgr_cleanup(u32 cgrid)
2878 {
2879 /*
2880 * query all FQDs starting from FQID 1 until we get an "invalid FQID"
2881 * error, looking for non-OOS FQDs whose CGR is the CGR being released
2882 */
2883 struct qman_fq fq = {
2884 .fqid = QM_FQID_RANGE_START
2885 };
2886 int err;
2887
2888 do {
2889 struct qm_mcr_queryfq_np np;
2890
2891 err = qman_query_fq_np(&fq, &np);
2892 if (err == -ERANGE)
2893 /* FQID range exceeded, found no problems */
2894 return 0;
2895 else if (WARN_ON(err))
2896 return err;
2897
2898 if ((np.state & QM_MCR_NP_STATE_MASK) != QM_MCR_NP_STATE_OOS) {
2899 struct qm_fqd fqd;
2900
2901 err = qman_query_fq(&fq, &fqd);
2902 if (WARN_ON(err))
2903 return err;
2904 if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE &&
2905 fqd.cgid == cgrid) {
2906 pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
2907 cgrid, fq.fqid);
2908 return -EIO;
2909 }
2910 }
2911 /* Move to the next FQID */
2912 fq.fqid++;
2913 } while (1);
2914 }
2915
2916 int qman_release_cgrid(u32 cgrid)
2917 {
2918 int ret;
2919
2920 ret = cgr_cleanup(cgrid);
2921 if (ret) {
2922 pr_debug("CGRID %d leaked\n", cgrid);
2923 return ret;
2924 }
2925
2926 gen_pool_free(qm_cgralloc, cgrid | DPAA_GENALLOC_OFF, 1);
2927 return 0;
2928 }
2929 EXPORT_SYMBOL(qman_release_cgrid);
Linux with added FPC-III support