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mmc: core: Reset HPI enabled state during re-init and in case of errors
[linux/fpc-iii.git] / drivers / staging / rtlwifi / wifi.h
blob9cb6c7906213192e78d541b3986498d42b2a5877
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 *
4 * Copyright(c) 2009-2012 Realtek Corporation.
5 *
6 * Contact Information:
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
9 * Hsinchu 300, Taiwan.
10 *
11 * Larry Finger <Larry.Finger@lwfinger.net>
12 *
13 *****************************************************************************/
14
15 #ifndef __RTL_WIFI_H__
16 #define __RTL_WIFI_H__
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/sched.h>
21 #include <linux/firmware.h>
22 #include <linux/etherdevice.h>
23 #include <linux/vmalloc.h>
24 #include <linux/usb.h>
25 #include <net/mac80211.h>
26 #include <linux/completion.h>
27 #include "debug.h"
28
29 #define MASKBYTE0 0xff
30 #define MASKBYTE1 0xff00
31 #define MASKBYTE2 0xff0000
32 #define MASKBYTE3 0xff000000
33 #define MASKHWORD 0xffff0000
34 #define MASKLWORD 0x0000ffff
35 #define MASKDWORD 0xffffffff
36 #define MASK12BITS 0xfff
37 #define MASKH4BITS 0xf0000000
38 #define MASKOFDM_D 0xffc00000
39 #define MASKCCK 0x3f3f3f3f
40
41 #define MASK4BITS 0x0f
42 #define MASK20BITS 0xfffff
43 #define RFREG_OFFSET_MASK 0xfffff
44
45 #define MASKBYTE0 0xff
46 #define MASKBYTE1 0xff00
47 #define MASKBYTE2 0xff0000
48 #define MASKBYTE3 0xff000000
49 #define MASKHWORD 0xffff0000
50 #define MASKLWORD 0x0000ffff
51 #define MASKDWORD 0xffffffff
52 #define MASK12BITS 0xfff
53 #define MASKH4BITS 0xf0000000
54 #define MASKOFDM_D 0xffc00000
55 #define MASKCCK 0x3f3f3f3f
56
57 #define MASK4BITS 0x0f
58 #define MASK20BITS 0xfffff
59 #define RFREG_OFFSET_MASK 0xfffff
60
61 #define RF_CHANGE_BY_INIT 0
62 #define RF_CHANGE_BY_IPS BIT(28)
63 #define RF_CHANGE_BY_PS BIT(29)
64 #define RF_CHANGE_BY_HW BIT(30)
65 #define RF_CHANGE_BY_SW BIT(31)
66
67 #define IQK_ADDA_REG_NUM 16
68 #define IQK_MAC_REG_NUM 4
69 #define IQK_THRESHOLD 8
70
71 #define MAX_KEY_LEN 61
72 #define KEY_BUF_SIZE 5
73
74 /* QoS related. */
75 /*aci: 0x00 Best Effort*/
76 /*aci: 0x01 Background*/
77 /*aci: 0x10 Video*/
78 /*aci: 0x11 Voice*/
79 /*Max: define total number.*/
80 #define AC0_BE 0
81 #define AC1_BK 1
82 #define AC2_VI 2
83 #define AC3_VO 3
84 #define AC_MAX 4
85 #define QOS_QUEUE_NUM 4
86 #define RTL_MAC80211_NUM_QUEUE 5
87 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
88 #define RTL_USB_MAX_RX_COUNT 100
89 #define QBSS_LOAD_SIZE 5
90 #define MAX_WMMELE_LENGTH 64
91 #define ASPM_L1_LATENCY 7
92
93 #define TOTAL_CAM_ENTRY 32
94
95 /*slot time for 11g. */
96 #define RTL_SLOT_TIME_9 9
97 #define RTL_SLOT_TIME_20 20
98
99 /*related to tcp/ip. */
100 #define SNAP_SIZE 6
101 #define PROTOC_TYPE_SIZE 2
102
103 /*related with 802.11 frame*/
104 #define MAC80211_3ADDR_LEN 24
105 #define MAC80211_4ADDR_LEN 30
106
107 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
108 #define CHANNEL_MAX_NUMBER_2G 14
109 #define CHANNEL_MAX_NUMBER_5G 49 /* Please refer to
110 *"phy_GetChnlGroup8812A" and
111 * "Hal_ReadTxPowerInfo8812A"
112 */
113 #define CHANNEL_MAX_NUMBER_5G_80M 7
114 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
115 #define MAX_PG_GROUP 13
116 #define CHANNEL_GROUP_MAX_2G 3
117 #define CHANNEL_GROUP_IDX_5GL 3
118 #define CHANNEL_GROUP_IDX_5GM 6
119 #define CHANNEL_GROUP_IDX_5GH 9
120 #define CHANNEL_GROUP_MAX_5G 9
121 #define CHANNEL_MAX_NUMBER_2G 14
122 #define AVG_THERMAL_NUM 8
123 #define AVG_THERMAL_NUM_88E 4
124 #define AVG_THERMAL_NUM_8723BE 4
125 #define MAX_TID_COUNT 9
126
127 /* for early mode */
128 #define FCS_LEN 4
129 #define EM_HDR_LEN 8
130
131 enum rtl8192c_h2c_cmd {
132 H2C_AP_OFFLOAD = 0,
133 H2C_SETPWRMODE = 1,
134 H2C_JOINBSSRPT = 2,
135 H2C_RSVDPAGE = 3,
136 H2C_RSSI_REPORT = 5,
137 H2C_RA_MASK = 6,
138 H2C_MACID_PS_MODE = 7,
139 H2C_P2P_PS_OFFLOAD = 8,
140 H2C_MAC_MODE_SEL = 9,
141 H2C_PWRM = 15,
142 H2C_P2P_PS_CTW_CMD = 24,
143 MAX_H2CCMD
144 };
145
146 #define MAX_TX_COUNT 4
147 #define MAX_REGULATION_NUM 4
148 #define MAX_RF_PATH_NUM 4
149 #define MAX_RATE_SECTION_NUM 6 /* = MAX_RATE_SECTION */
150 #define MAX_2_4G_BANDWIDTH_NUM 4
151 #define MAX_5G_BANDWIDTH_NUM 4
152 #define MAX_RF_PATH 4
153 #define MAX_CHNL_GROUP_24G 6
154 #define MAX_CHNL_GROUP_5G 14
155
156 #define TX_PWR_BY_RATE_NUM_BAND 2
157 #define TX_PWR_BY_RATE_NUM_RF 4
158 #define TX_PWR_BY_RATE_NUM_SECTION 12
159 /* compatible with TX_PWR_BY_RATE_NUM_SECTION */
160 #define TX_PWR_BY_RATE_NUM_RATE 84
161 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 /* MAX_RATE_SECTION */
162 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 /* MAX_RATE_SECTION -1 */
163
164 #define BUFDESC_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
165
166 #define DEL_SW_IDX_SZ 30
167
168 /* For now, it's just for 8192ee
169 * but not OK yet, keep it 0
170 */
171 #define RTL8192EE_SEG_NUM BUFDESC_SEG_NUM
172 #define RTL8822BE_SEG_NUM BUFDESC_SEG_NUM
173
174 enum rf_tx_num {
175 RF_1TX = 0,
176 RF_2TX,
177 RF_MAX_TX_NUM,
178 RF_TX_NUM_NONIMPLEMENT,
179 };
180
181 #define PACKET_NORMAL 0
182 #define PACKET_DHCP 1
183 #define PACKET_ARP 2
184 #define PACKET_EAPOL 3
185
186 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
187 #define RSVD_WOL_PATTERN_NUM 1
188 #define WKFMCAM_ADDR_NUM 6
189 #define WKFMCAM_SIZE 24
190
191 #define MAX_WOL_BIT_MASK_SIZE 16
192 /* MIN LEN keeps 13 here */
193 #define MIN_WOL_PATTERN_SIZE 13
194 #define MAX_WOL_PATTERN_SIZE 128
195
196 #define WAKE_ON_MAGIC_PACKET BIT(0)
197 #define WAKE_ON_PATTERN_MATCH BIT(1)
198
199 #define WOL_REASON_PTK_UPDATE BIT(0)
200 #define WOL_REASON_GTK_UPDATE BIT(1)
201 #define WOL_REASON_DISASSOC BIT(2)
202 #define WOL_REASON_DEAUTH BIT(3)
203 #define WOL_REASON_AP_LOST BIT(4)
204 #define WOL_REASON_MAGIC_PKT BIT(5)
205 #define WOL_REASON_UNICAST_PKT BIT(6)
206 #define WOL_REASON_PATTERN_PKT BIT(7)
207 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
208 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
209 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
210
211 struct rtlwifi_firmware_header {
212 __le16 signature;
213 u8 category;
214 u8 function;
215 __le16 version;
216 u8 subversion;
217 u8 rsvd1;
218 u8 month;
219 u8 date;
220 u8 hour;
221 u8 minute;
222 __le16 ramcodesize;
223 __le16 rsvd2;
224 __le32 svnindex;
225 __le32 rsvd3;
226 __le32 rsvd4;
227 __le32 rsvd5;
228 };
229
230 struct txpower_info_2g {
231 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
232 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
233 /*If only one tx, only BW20 and OFDM are used.*/
234 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
235 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
236 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
237 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
238 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
239 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
240 };
241
242 struct txpower_info_5g {
243 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
244 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
245 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
246 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
247 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
248 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
249 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
250 };
251
252 enum rate_section {
253 CCK = 0,
254 OFDM,
255 HT_MCS0_MCS7,
256 HT_MCS8_MCS15,
257 VHT_1SSMCS0_1SSMCS9,
258 VHT_2SSMCS0_2SSMCS9,
259 MAX_RATE_SECTION,
260 };
261
262 enum intf_type {
263 INTF_PCI = 0,
264 INTF_USB = 1,
265 };
266
267 enum radio_path {
268 RF90_PATH_A = 0,
269 RF90_PATH_B = 1,
270 RF90_PATH_C = 2,
271 RF90_PATH_D = 3,
272 };
273
274 enum radio_mask {
275 RF_MASK_A = BIT(0),
276 RF_MASK_B = BIT(1),
277 RF_MASK_C = BIT(2),
278 RF_MASK_D = BIT(3),
279 };
280
281 enum regulation_txpwr_lmt {
282 TXPWR_LMT_FCC = 0,
283 TXPWR_LMT_MKK = 1,
284 TXPWR_LMT_ETSI = 2,
285 TXPWR_LMT_WW = 3,
286
287 TXPWR_LMT_MAX_REGULATION_NUM = 4
288 };
289
290 enum rt_eeprom_type {
291 EEPROM_93C46,
292 EEPROM_93C56,
293 EEPROM_BOOT_EFUSE,
294 };
295
296 enum ttl_status {
297 RTL_STATUS_INTERFACE_START = 0,
298 };
299
300 enum hardware_type {
301 HARDWARE_TYPE_RTL8192E,
302 HARDWARE_TYPE_RTL8192U,
303 HARDWARE_TYPE_RTL8192SE,
304 HARDWARE_TYPE_RTL8192SU,
305 HARDWARE_TYPE_RTL8192CE,
306 HARDWARE_TYPE_RTL8192CU,
307 HARDWARE_TYPE_RTL8192DE,
308 HARDWARE_TYPE_RTL8192DU,
309 HARDWARE_TYPE_RTL8723AE,
310 HARDWARE_TYPE_RTL8723U,
311 HARDWARE_TYPE_RTL8188EE,
312 HARDWARE_TYPE_RTL8723BE,
313 HARDWARE_TYPE_RTL8192EE,
314 HARDWARE_TYPE_RTL8821AE,
315 HARDWARE_TYPE_RTL8812AE,
316 HARDWARE_TYPE_RTL8822BE,
317
318 /* keep it last */
319 HARDWARE_TYPE_NUM
320 };
321
322 #define RTL_HW_TYPE(rtlpriv) (rtl_hal((struct rtl_priv *)rtlpriv)->hw_type)
323 #define IS_NEW_GENERATION_IC(rtlpriv) \
324 (RTL_HW_TYPE(rtlpriv) >= HARDWARE_TYPE_RTL8192EE)
325 #define IS_HARDWARE_TYPE_8192CE(rtlpriv) \
326 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192CE)
327 #define IS_HARDWARE_TYPE_8812(rtlpriv) \
328 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8812AE)
329 #define IS_HARDWARE_TYPE_8821(rtlpriv) \
330 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8821AE)
331 #define IS_HARDWARE_TYPE_8723A(rtlpriv) \
332 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723AE)
333 #define IS_HARDWARE_TYPE_8723B(rtlpriv) \
334 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8723BE)
335 #define IS_HARDWARE_TYPE_8192E(rtlpriv) \
336 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8192EE)
337 #define IS_HARDWARE_TYPE_8822B(rtlpriv) \
338 (RTL_HW_TYPE(rtlpriv) == HARDWARE_TYPE_RTL8822BE)
339
340 #define RX_HAL_IS_CCK_RATE(rxmcs) \
341 ((rxmcs) == DESC_RATE1M || \
342 (rxmcs) == DESC_RATE2M || \
343 (rxmcs) == DESC_RATE5_5M || \
344 (rxmcs) == DESC_RATE11M)
345
346 enum scan_operation_backup_opt {
347 SCAN_OPT_BACKUP = 0,
348 SCAN_OPT_BACKUP_BAND0 = 0,
349 SCAN_OPT_BACKUP_BAND1,
350 SCAN_OPT_RESTORE,
351 SCAN_OPT_MAX
352 };
353
354 /*RF state.*/
355 enum rf_pwrstate {
356 ERFON,
357 ERFSLEEP,
358 ERFOFF
359 };
360
361 struct bb_reg_def {
362 u32 rfintfs;
363 u32 rfintfi;
364 u32 rfintfo;
365 u32 rfintfe;
366 u32 rf3wire_offset;
367 u32 rflssi_select;
368 u32 rftxgain_stage;
369 u32 rfhssi_para1;
370 u32 rfhssi_para2;
371 u32 rfsw_ctrl;
372 u32 rfagc_control1;
373 u32 rfagc_control2;
374 u32 rfrxiq_imbal;
375 u32 rfrx_afe;
376 u32 rftxiq_imbal;
377 u32 rftx_afe;
378 u32 rf_rb; /* rflssi_readback */
379 u32 rf_rbpi; /* rflssi_readbackpi */
380 };
381
382 enum io_type {
383 IO_CMD_PAUSE_DM_BY_SCAN = 0,
384 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
385 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
386 IO_CMD_RESUME_DM_BY_SCAN = 2,
387 };
388
389 enum hw_variables {
390 HW_VAR_ETHER_ADDR = 0x0,
391 HW_VAR_MULTICAST_REG = 0x1,
392 HW_VAR_BASIC_RATE = 0x2,
393 HW_VAR_BSSID = 0x3,
394 HW_VAR_MEDIA_STATUS = 0x4,
395 HW_VAR_SECURITY_CONF = 0x5,
396 HW_VAR_BEACON_INTERVAL = 0x6,
397 HW_VAR_ATIM_WINDOW = 0x7,
398 HW_VAR_LISTEN_INTERVAL = 0x8,
399 HW_VAR_CS_COUNTER = 0x9,
400 HW_VAR_DEFAULTKEY0 = 0xa,
401 HW_VAR_DEFAULTKEY1 = 0xb,
402 HW_VAR_DEFAULTKEY2 = 0xc,
403 HW_VAR_DEFAULTKEY3 = 0xd,
404 HW_VAR_SIFS = 0xe,
405 HW_VAR_R2T_SIFS = 0xf,
406 HW_VAR_DIFS = 0x10,
407 HW_VAR_EIFS = 0x11,
408 HW_VAR_SLOT_TIME = 0x12,
409 HW_VAR_ACK_PREAMBLE = 0x13,
410 HW_VAR_CW_CONFIG = 0x14,
411 HW_VAR_CW_VALUES = 0x15,
412 HW_VAR_RATE_FALLBACK_CONTROL = 0x16,
413 HW_VAR_CONTENTION_WINDOW = 0x17,
414 HW_VAR_RETRY_COUNT = 0x18,
415 HW_VAR_TR_SWITCH = 0x19,
416 HW_VAR_COMMAND = 0x1a,
417 HW_VAR_WPA_CONFIG = 0x1b,
418 HW_VAR_AMPDU_MIN_SPACE = 0x1c,
419 HW_VAR_SHORTGI_DENSITY = 0x1d,
420 HW_VAR_AMPDU_FACTOR = 0x1e,
421 HW_VAR_MCS_RATE_AVAILABLE = 0x1f,
422 HW_VAR_AC_PARAM = 0x20,
423 HW_VAR_ACM_CTRL = 0x21,
424 HW_VAR_DIS_REQ_QSIZE = 0x22,
425 HW_VAR_CCX_CHNL_LOAD = 0x23,
426 HW_VAR_CCX_NOISE_HISTOGRAM = 0x24,
427 HW_VAR_CCX_CLM_NHM = 0x25,
428 HW_VAR_TXOPLIMIT = 0x26,
429 HW_VAR_TURBO_MODE = 0x27,
430 HW_VAR_RF_STATE = 0x28,
431 HW_VAR_RF_OFF_BY_HW = 0x29,
432 HW_VAR_BUS_SPEED = 0x2a,
433 HW_VAR_SET_DEV_POWER = 0x2b,
434
435 HW_VAR_RCR = 0x2c,
436 HW_VAR_RATR_0 = 0x2d,
437 HW_VAR_RRSR = 0x2e,
438 HW_VAR_CPU_RST = 0x2f,
439 HW_VAR_CHECK_BSSID = 0x30,
440 HW_VAR_LBK_MODE = 0x31,
441 HW_VAR_AES_11N_FIX = 0x32,
442 HW_VAR_USB_RX_AGGR = 0x33,
443 HW_VAR_USER_CONTROL_TURBO_MODE = 0x34,
444 HW_VAR_RETRY_LIMIT = 0x35,
445 HW_VAR_INIT_TX_RATE = 0x36,
446 HW_VAR_TX_RATE_REG = 0x37,
447 HW_VAR_EFUSE_USAGE = 0x38,
448 HW_VAR_EFUSE_BYTES = 0x39,
449 HW_VAR_AUTOLOAD_STATUS = 0x3a,
450 HW_VAR_RF_2R_DISABLE = 0x3b,
451 HW_VAR_SET_RPWM = 0x3c,
452 HW_VAR_H2C_FW_PWRMODE = 0x3d,
453 HW_VAR_H2C_FW_JOINBSSRPT = 0x3e,
454 HW_VAR_H2C_FW_MEDIASTATUSRPT = 0x3f,
455 HW_VAR_H2C_FW_P2P_PS_OFFLOAD = 0x40,
456 HW_VAR_FW_PSMODE_STATUS = 0x41,
457 HW_VAR_INIT_RTS_RATE = 0x42,
458 HW_VAR_RESUME_CLK_ON = 0x43,
459 HW_VAR_FW_LPS_ACTION = 0x44,
460 HW_VAR_1X1_RECV_COMBINE = 0x45,
461 HW_VAR_STOP_SEND_BEACON = 0x46,
462 HW_VAR_TSF_TIMER = 0x47,
463 HW_VAR_IO_CMD = 0x48,
464
465 HW_VAR_RF_RECOVERY = 0x49,
466 HW_VAR_H2C_FW_UPDATE_GTK = 0x4a,
467 HW_VAR_WF_MASK = 0x4b,
468 HW_VAR_WF_CRC = 0x4c,
469 HW_VAR_WF_IS_MAC_ADDR = 0x4d,
470 HW_VAR_H2C_FW_OFFLOAD = 0x4e,
471 HW_VAR_RESET_WFCRC = 0x4f,
472
473 HW_VAR_HANDLE_FW_C2H = 0x50,
474 HW_VAR_DL_FW_RSVD_PAGE = 0x51,
475 HW_VAR_AID = 0x52,
476 HW_VAR_HW_SEQ_ENABLE = 0x53,
477 HW_VAR_CORRECT_TSF = 0x54,
478 HW_VAR_BCN_VALID = 0x55,
479 HW_VAR_FWLPS_RF_ON = 0x56,
480 HW_VAR_DUAL_TSF_RST = 0x57,
481 HW_VAR_SWITCH_EPHY_WOWLAN = 0x58,
482 HW_VAR_INT_MIGRATION = 0x59,
483 HW_VAR_INT_AC = 0x5a,
484 HW_VAR_RF_TIMING = 0x5b,
485
486 HAL_DEF_WOWLAN = 0x5c,
487 HW_VAR_MRC = 0x5d,
488 HW_VAR_KEEP_ALIVE = 0x5e,
489 HW_VAR_NAV_UPPER = 0x5f,
490
491 HW_VAR_MGT_FILTER = 0x60,
492 HW_VAR_CTRL_FILTER = 0x61,
493 HW_VAR_DATA_FILTER = 0x62,
494 };
495
496 enum rt_media_status {
497 RT_MEDIA_DISCONNECT = 0,
498 RT_MEDIA_CONNECT = 1
499 };
500
501 enum rt_oem_id {
502 RT_CID_DEFAULT = 0,
503 RT_CID_8187_ALPHA0 = 1,
504 RT_CID_8187_SERCOMM_PS = 2,
505 RT_CID_8187_HW_LED = 3,
506 RT_CID_8187_NETGEAR = 4,
507 RT_CID_WHQL = 5,
508 RT_CID_819X_CAMEO = 6,
509 RT_CID_819X_RUNTOP = 7,
510 RT_CID_819X_SENAO = 8,
511 RT_CID_TOSHIBA = 9,
512 RT_CID_819X_NETCORE = 10,
513 RT_CID_NETTRONIX = 11,
514 RT_CID_DLINK = 12,
515 RT_CID_PRONET = 13,
516 RT_CID_COREGA = 14,
517 RT_CID_819X_ALPHA = 15,
518 RT_CID_819X_SITECOM = 16,
519 RT_CID_CCX = 17,
520 RT_CID_819X_LENOVO = 18,
521 RT_CID_819X_QMI = 19,
522 RT_CID_819X_EDIMAX_BELKIN = 20,
523 RT_CID_819X_SERCOMM_BELKIN = 21,
524 RT_CID_819X_CAMEO1 = 22,
525 RT_CID_819X_MSI = 23,
526 RT_CID_819X_ACER = 24,
527 RT_CID_819X_HP = 27,
528 RT_CID_819X_CLEVO = 28,
529 RT_CID_819X_ARCADYAN_BELKIN = 29,
530 RT_CID_819X_SAMSUNG = 30,
531 RT_CID_819X_WNC_COREGA = 31,
532 RT_CID_819X_FOXCOON = 32,
533 RT_CID_819X_DELL = 33,
534 RT_CID_819X_PRONETS = 34,
535 RT_CID_819X_EDIMAX_ASUS = 35,
536 RT_CID_NETGEAR = 36,
537 RT_CID_PLANEX = 37,
538 RT_CID_CC_C = 38,
539 };
540
541 enum hw_descs {
542 HW_DESC_OWN,
543 HW_DESC_RXOWN,
544 HW_DESC_TX_NEXTDESC_ADDR,
545 HW_DESC_TXBUFF_ADDR,
546 HW_DESC_RXBUFF_ADDR,
547 HW_DESC_RXPKT_LEN,
548 HW_DESC_RXERO,
549 HW_DESC_RX_PREPARE,
550 };
551
552 enum prime_sc {
553 PRIME_CHNL_OFFSET_DONT_CARE = 0,
554 PRIME_CHNL_OFFSET_LOWER = 1,
555 PRIME_CHNL_OFFSET_UPPER = 2,
556 };
557
558 enum rf_type {
559 RF_1T1R = 0,
560 RF_1T2R = 1,
561 RF_2T2R = 2,
562 RF_2T2R_GREEN = 3,
563 RF_2T3R = 4,
564 RF_2T4R = 5,
565 RF_3T3R = 6,
566 RF_3T4R = 7,
567 RF_4T4R = 8,
568 };
569
570 enum ht_channel_width {
571 HT_CHANNEL_WIDTH_20 = 0,
572 HT_CHANNEL_WIDTH_20_40 = 1,
573 HT_CHANNEL_WIDTH_80 = 2,
574 HT_CHANNEL_WIDTH_MAX,
575 };
576
577 /* Ref: 802.11i spec D10.0 7.3.2.25.1
578 * Cipher Suites Encryption Algorithms
579 */
580 enum rt_enc_alg {
581 NO_ENCRYPTION = 0,
582 WEP40_ENCRYPTION = 1,
583 TKIP_ENCRYPTION = 2,
584 RSERVED_ENCRYPTION = 3,
585 AESCCMP_ENCRYPTION = 4,
586 WEP104_ENCRYPTION = 5,
587 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
588 };
589
590 enum rtl_hal_state {
591 _HAL_STATE_STOP = 0,
592 _HAL_STATE_START = 1,
593 };
594
595 enum rtl_desc_rate {
596 DESC_RATE1M = 0x00,
597 DESC_RATE2M = 0x01,
598 DESC_RATE5_5M = 0x02,
599 DESC_RATE11M = 0x03,
600
601 DESC_RATE6M = 0x04,
602 DESC_RATE9M = 0x05,
603 DESC_RATE12M = 0x06,
604 DESC_RATE18M = 0x07,
605 DESC_RATE24M = 0x08,
606 DESC_RATE36M = 0x09,
607 DESC_RATE48M = 0x0a,
608 DESC_RATE54M = 0x0b,
609
610 DESC_RATEMCS0 = 0x0c,
611 DESC_RATEMCS1 = 0x0d,
612 DESC_RATEMCS2 = 0x0e,
613 DESC_RATEMCS3 = 0x0f,
614 DESC_RATEMCS4 = 0x10,
615 DESC_RATEMCS5 = 0x11,
616 DESC_RATEMCS6 = 0x12,
617 DESC_RATEMCS7 = 0x13,
618 DESC_RATEMCS8 = 0x14,
619 DESC_RATEMCS9 = 0x15,
620 DESC_RATEMCS10 = 0x16,
621 DESC_RATEMCS11 = 0x17,
622 DESC_RATEMCS12 = 0x18,
623 DESC_RATEMCS13 = 0x19,
624 DESC_RATEMCS14 = 0x1a,
625 DESC_RATEMCS15 = 0x1b,
626 DESC_RATEMCS15_SG = 0x1c,
627 DESC_RATEMCS32 = 0x20,
628
629 DESC_RATEVHT1SS_MCS0 = 0x2c,
630 DESC_RATEVHT1SS_MCS1 = 0x2d,
631 DESC_RATEVHT1SS_MCS2 = 0x2e,
632 DESC_RATEVHT1SS_MCS3 = 0x2f,
633 DESC_RATEVHT1SS_MCS4 = 0x30,
634 DESC_RATEVHT1SS_MCS5 = 0x31,
635 DESC_RATEVHT1SS_MCS6 = 0x32,
636 DESC_RATEVHT1SS_MCS7 = 0x33,
637 DESC_RATEVHT1SS_MCS8 = 0x34,
638 DESC_RATEVHT1SS_MCS9 = 0x35,
639 DESC_RATEVHT2SS_MCS0 = 0x36,
640 DESC_RATEVHT2SS_MCS1 = 0x37,
641 DESC_RATEVHT2SS_MCS2 = 0x38,
642 DESC_RATEVHT2SS_MCS3 = 0x39,
643 DESC_RATEVHT2SS_MCS4 = 0x3a,
644 DESC_RATEVHT2SS_MCS5 = 0x3b,
645 DESC_RATEVHT2SS_MCS6 = 0x3c,
646 DESC_RATEVHT2SS_MCS7 = 0x3d,
647 DESC_RATEVHT2SS_MCS8 = 0x3e,
648 DESC_RATEVHT2SS_MCS9 = 0x3f,
649 };
650
651 enum rtl_var_map {
652 /*reg map */
653 SYS_ISO_CTRL = 0,
654 SYS_FUNC_EN,
655 SYS_CLK,
656 MAC_RCR_AM,
657 MAC_RCR_AB,
658 MAC_RCR_ACRC32,
659 MAC_RCR_ACF,
660 MAC_RCR_AAP,
661 MAC_HIMR,
662 MAC_HIMRE,
663 MAC_HSISR,
664
665 /*efuse map */
666 EFUSE_TEST,
667 EFUSE_CTRL,
668 EFUSE_CLK,
669 EFUSE_CLK_CTRL,
670 EFUSE_PWC_EV12V,
671 EFUSE_FEN_ELDR,
672 EFUSE_LOADER_CLK_EN,
673 EFUSE_ANA8M,
674 EFUSE_HWSET_MAX_SIZE,
675 EFUSE_MAX_SECTION_MAP,
676 EFUSE_REAL_CONTENT_SIZE,
677 EFUSE_OOB_PROTECT_BYTES_LEN,
678 EFUSE_ACCESS,
679
680 /*CAM map */
681 RWCAM,
682 WCAMI,
683 RCAMO,
684 CAMDBG,
685 SECR,
686 SEC_CAM_NONE,
687 SEC_CAM_WEP40,
688 SEC_CAM_TKIP,
689 SEC_CAM_AES,
690 SEC_CAM_WEP104,
691
692 /*IMR map */
693 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
694 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
695 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
696 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
697 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
698 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
699 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrupt 8 */
700 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrupt 7 */
701 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrupt 6 */
702 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrupt 5 */
703 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrupt 4 */
704 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrupt 3 */
705 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrupt 2 */
706 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrupt 1 */
707 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
708 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
709 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
710 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
711 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
712 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
713 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
714 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
715 RTL_IMR_H2CDOK, /*H2C Queue DMA OK Interrupt */
716 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrupt */
717 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
718 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
719 RTL_IMR_TBDOK, /*Transmit Beacon OK interrupt */
720 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
721 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
722 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
723 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
724 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
725 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
726 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
727 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
728 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
729 * RTL_IMR_TBDER)
730 */
731 RTL_IMR_C2HCMD, /*fw interrupt*/
732
733 /*CCK Rates, TxHT = 0 */
734 RTL_RC_CCK_RATE1M,
735 RTL_RC_CCK_RATE2M,
736 RTL_RC_CCK_RATE5_5M,
737 RTL_RC_CCK_RATE11M,
738
739 /*OFDM Rates, TxHT = 0 */
740 RTL_RC_OFDM_RATE6M,
741 RTL_RC_OFDM_RATE9M,
742 RTL_RC_OFDM_RATE12M,
743 RTL_RC_OFDM_RATE18M,
744 RTL_RC_OFDM_RATE24M,
745 RTL_RC_OFDM_RATE36M,
746 RTL_RC_OFDM_RATE48M,
747 RTL_RC_OFDM_RATE54M,
748
749 RTL_RC_HT_RATEMCS7,
750 RTL_RC_HT_RATEMCS15,
751
752 RTL_RC_VHT_RATE_1SS_MCS7,
753 RTL_RC_VHT_RATE_1SS_MCS8,
754 RTL_RC_VHT_RATE_1SS_MCS9,
755 RTL_RC_VHT_RATE_2SS_MCS7,
756 RTL_RC_VHT_RATE_2SS_MCS8,
757 RTL_RC_VHT_RATE_2SS_MCS9,
758
759 /*keep it last */
760 RTL_VAR_MAP_MAX,
761 };
762
763 /*Firmware PS mode for control LPS.*/
764 enum _fw_ps_mode {
765 FW_PS_ACTIVE_MODE = 0,
766 FW_PS_MIN_MODE = 1,
767 FW_PS_MAX_MODE = 2,
768 FW_PS_DTIM_MODE = 3,
769 FW_PS_VOIP_MODE = 4,
770 FW_PS_UAPSD_WMM_MODE = 5,
771 FW_PS_UAPSD_MODE = 6,
772 FW_PS_IBSS_MODE = 7,
773 FW_PS_WWLAN_MODE = 8,
774 FW_PS_PM_RADIO_OFF = 9,
775 FW_PS_PM_CARD_DISABLE = 10,
776 };
777
778 enum rt_psmode {
779 EACTIVE, /*Active/Continuous access. */
780 EMAXPS, /*Max power save mode. */
781 EFASTPS, /*Fast power save mode. */
782 EAUTOPS, /*Auto power save mode. */
783 };
784
785 /*LED related.*/
786 enum led_ctl_mode {
787 LED_CTL_POWER_ON = 1,
788 LED_CTL_LINK = 2,
789 LED_CTL_NO_LINK = 3,
790 LED_CTL_TX = 4,
791 LED_CTL_RX = 5,
792 LED_CTL_SITE_SURVEY = 6,
793 LED_CTL_POWER_OFF = 7,
794 LED_CTL_START_TO_LINK = 8,
795 LED_CTL_START_WPS = 9,
796 LED_CTL_STOP_WPS = 10,
797 };
798
799 enum rtl_led_pin {
800 LED_PIN_GPIO0,
801 LED_PIN_LED0,
802 LED_PIN_LED1,
803 LED_PIN_LED2
804 };
805
806 /* QoS related.*/
807 /* acm implementation method.*/
808 enum acm_method {
809 EACMWAY0_SWANDHW = 0,
810 EACMWAY1_HW = 1,
811 EACMWAY2_SW = 2,
812 };
813
814 enum macphy_mode {
815 SINGLEMAC_SINGLEPHY = 0,
816 DUALMAC_DUALPHY,
817 DUALMAC_SINGLEPHY,
818 };
819
820 enum band_type {
821 BAND_ON_2_4G = 0,
822 BAND_ON_5G,
823 BAND_ON_BOTH,
824 BANDMAX
825 };
826
827 /* aci/aifsn Field.
828 * Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
829 */
830 union aci_aifsn {
831 u8 char_data;
832
833 struct {
834 u8 aifsn:4;
835 u8 acm:1;
836 u8 aci:2;
837 u8 reserved:1;
838 } f; /* Field */
839 };
840
841 /*mlme related.*/
842 enum wireless_mode {
843 WIRELESS_MODE_UNKNOWN = 0x00,
844 WIRELESS_MODE_A = 0x01,
845 WIRELESS_MODE_B = 0x02,
846 WIRELESS_MODE_G = 0x04,
847 WIRELESS_MODE_AUTO = 0x08,
848 WIRELESS_MODE_N_24G = 0x10,
849 WIRELESS_MODE_N_5G = 0x20,
850 WIRELESS_MODE_AC_5G = 0x40,
851 WIRELESS_MODE_AC_24G = 0x80,
852 WIRELESS_MODE_AC_ONLY = 0x100,
853 WIRELESS_MODE_MAX = 0x800
854 };
855
856 #define IS_WIRELESS_MODE_A(wirelessmode) \
857 (wirelessmode == WIRELESS_MODE_A)
858 #define IS_WIRELESS_MODE_B(wirelessmode) \
859 (wirelessmode == WIRELESS_MODE_B)
860 #define IS_WIRELESS_MODE_G(wirelessmode) \
861 (wirelessmode == WIRELESS_MODE_G)
862 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
863 (wirelessmode == WIRELESS_MODE_N_24G)
864 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
865 (wirelessmode == WIRELESS_MODE_N_5G)
866
867 enum ratr_table_mode {
868 RATR_INX_WIRELESS_NGB = 0,
869 RATR_INX_WIRELESS_NG = 1,
870 RATR_INX_WIRELESS_NB = 2,
871 RATR_INX_WIRELESS_N = 3,
872 RATR_INX_WIRELESS_GB = 4,
873 RATR_INX_WIRELESS_G = 5,
874 RATR_INX_WIRELESS_B = 6,
875 RATR_INX_WIRELESS_MC = 7,
876 RATR_INX_WIRELESS_A = 8,
877 RATR_INX_WIRELESS_AC_5N = 8,
878 RATR_INX_WIRELESS_AC_24N = 9,
879 };
880
881 enum ratr_table_mode_new {
882 RATEID_IDX_BGN_40M_2SS = 0,
883 RATEID_IDX_BGN_40M_1SS = 1,
884 RATEID_IDX_BGN_20M_2SS_BN = 2,
885 RATEID_IDX_BGN_20M_1SS_BN = 3,
886 RATEID_IDX_GN_N2SS = 4,
887 RATEID_IDX_GN_N1SS = 5,
888 RATEID_IDX_BG = 6,
889 RATEID_IDX_G = 7,
890 RATEID_IDX_B = 8,
891 RATEID_IDX_VHT_2SS = 9,
892 RATEID_IDX_VHT_1SS = 10,
893 RATEID_IDX_MIX1 = 11,
894 RATEID_IDX_MIX2 = 12,
895 RATEID_IDX_VHT_3SS = 13,
896 RATEID_IDX_BGN_3SS = 14,
897 };
898
899 enum rtl_link_state {
900 MAC80211_NOLINK = 0,
901 MAC80211_LINKING = 1,
902 MAC80211_LINKED = 2,
903 MAC80211_LINKED_SCANNING = 3,
904 };
905
906 enum act_category {
907 ACT_CAT_QOS = 1,
908 ACT_CAT_DLS = 2,
909 ACT_CAT_BA = 3,
910 ACT_CAT_HT = 7,
911 ACT_CAT_WMM = 17,
912 };
913
914 enum ba_action {
915 ACT_ADDBAREQ = 0,
916 ACT_ADDBARSP = 1,
917 ACT_DELBA = 2,
918 };
919
920 enum rt_polarity_ctl {
921 RT_POLARITY_LOW_ACT = 0,
922 RT_POLARITY_HIGH_ACT = 1,
923 };
924
925 /* After 8188E, we use V2 reason define. 88C/8723A use V1 reason. */
926 enum fw_wow_reason_v2 {
927 FW_WOW_V2_PTK_UPDATE_EVENT = 0x01,
928 FW_WOW_V2_GTK_UPDATE_EVENT = 0x02,
929 FW_WOW_V2_DISASSOC_EVENT = 0x04,
930 FW_WOW_V2_DEAUTH_EVENT = 0x08,
931 FW_WOW_V2_FW_DISCONNECT_EVENT = 0x10,
932 FW_WOW_V2_MAGIC_PKT_EVENT = 0x21,
933 FW_WOW_V2_UNICAST_PKT_EVENT = 0x22,
934 FW_WOW_V2_PATTERN_PKT_EVENT = 0x23,
935 FW_WOW_V2_RTD3_SSID_MATCH_EVENT = 0x24,
936 FW_WOW_V2_REALWOW_V2_WAKEUPPKT = 0x30,
937 FW_WOW_V2_REALWOW_V2_ACKLOST = 0x31,
938 FW_WOW_V2_REASON_MAX = 0xff,
939 };
940
941 enum wolpattern_type {
942 UNICAST_PATTERN = 0,
943 MULTICAST_PATTERN = 1,
944 BROADCAST_PATTERN = 2,
945 DONT_CARE_DA = 3,
946 UNKNOWN_TYPE = 4,
947 };
948
949 enum package_type {
950 PACKAGE_DEFAULT,
951 PACKAGE_QFN68,
952 PACKAGE_TFBGA90,
953 PACKAGE_TFBGA80,
954 PACKAGE_TFBGA79
955 };
956
957 enum rtl_spec_ver {
958 RTL_SPEC_NEW_RATEID = BIT(0), /* use ratr_table_mode_new */
959 RTL_SPEC_SUPPORT_VHT = BIT(1), /* support VHT */
960 RTL_SPEC_NEW_FW_C2H = BIT(2), /* new FW C2H (e.g. TX REPORT) */
961 };
962
963 struct octet_string {
964 u8 *octet;
965 u16 length;
966 };
967
968 struct rtl_hdr_3addr {
969 __le16 frame_ctl;
970 __le16 duration_id;
971 u8 addr1[ETH_ALEN];
972 u8 addr2[ETH_ALEN];
973 u8 addr3[ETH_ALEN];
974 __le16 seq_ctl;
975 u8 payload[0];
976 } __packed;
977
978 struct rtl_info_element {
979 u8 id;
980 u8 len;
981 u8 data[0];
982 } __packed;
983
984 struct rtl_probe_rsp {
985 struct rtl_hdr_3addr header;
986 u32 time_stamp[2];
987 __le16 beacon_interval;
988 __le16 capability;
989 /* SSID, supported rates, FH params, DS params,
990 * CF params, IBSS params, TIM (if beacon), RSN
991 */
992 struct rtl_info_element info_element[0];
993 } __packed;
994
995 struct rtl_beacon_keys {
996 /*u8 ssid[32];*/
997 /*u32 ssid_len;*/
998 u8 bcn_channel;
999 __le16 ht_cap_info;
1000 u8 ht_info_infos_0_sco; /* bit0 & bit1 in infos[0] is 2nd ch offset */
1001 bool valid;
1002 };
1003
1004 /*LED related.*/
1005 /*ledpin Identify how to implement this SW led.*/
1006 struct rtl_led {
1007 void *hw;
1008 enum rtl_led_pin ledpin;
1009 bool ledon;
1010 };
1011
1012 struct rtl_led_ctl {
1013 bool led_opendrain;
1014 struct rtl_led sw_led0;
1015 struct rtl_led sw_led1;
1016 };
1017
1018 struct rtl_qos_parameters {
1019 __le16 cw_min;
1020 __le16 cw_max;
1021 u8 aifs;
1022 u8 flag;
1023 __le16 tx_op;
1024 } __packed;
1025
1026 struct rt_smooth_data {
1027 u32 elements[100]; /*array to store values */
1028 u32 index; /*index to current array to store */
1029 u32 total_num; /*num of valid elements */
1030 u32 total_val; /*sum of valid elements */
1031 };
1032
1033 struct false_alarm_statistics {
1034 u32 cnt_parity_fail;
1035 u32 cnt_rate_illegal;
1036 u32 cnt_crc8_fail;
1037 u32 cnt_mcs_fail;
1038 u32 cnt_fast_fsync_fail;
1039 u32 cnt_sb_search_fail;
1040 u32 cnt_ofdm_fail;
1041 u32 cnt_cck_fail;
1042 u32 cnt_all;
1043 u32 cnt_ofdm_cca;
1044 u32 cnt_cck_cca;
1045 u32 cnt_cca_all;
1046 u32 cnt_bw_usc;
1047 u32 cnt_bw_lsc;
1048 };
1049
1050 struct init_gain {
1051 u8 xaagccore1;
1052 u8 xbagccore1;
1053 u8 xcagccore1;
1054 u8 xdagccore1;
1055 u8 cca;
1056
1057 };
1058
1059 struct wireless_stats {
1060 u64 txbytesunicast;
1061 u64 txbytesmulticast;
1062 u64 txbytesbroadcast;
1063 u64 rxbytesunicast;
1064
1065 u64 txbytesunicast_inperiod;
1066 u64 rxbytesunicast_inperiod;
1067 u32 txbytesunicast_inperiod_tp;
1068 u32 rxbytesunicast_inperiod_tp;
1069 u64 txbytesunicast_last;
1070 u64 rxbytesunicast_last;
1071
1072 long rx_snr_db[4];
1073 /* Correct smoothed ss in Dbm, only used
1074 * in driver to report real power now.
1075 */
1076 long recv_signal_power;
1077 long signal_quality;
1078 long last_sigstrength_inpercent;
1079
1080 u32 rssi_calculate_cnt;
1081 u32 pwdb_all_cnt;
1082
1083 /* Transformed, in dbm. Beautified signal
1084 * strength for UI, not correct.
1085 */
1086 long signal_strength;
1087
1088 u8 rx_rssi_percentage[4];
1089 u8 rx_evm_dbm[4];
1090 u8 rx_evm_percentage[2];
1091
1092 u16 rx_cfo_short[4];
1093 u16 rx_cfo_tail[4];
1094
1095 struct rt_smooth_data ui_rssi;
1096 struct rt_smooth_data ui_link_quality;
1097 };
1098
1099 struct rate_adaptive {
1100 u8 rate_adaptive_disabled;
1101 u8 ratr_state;
1102 u16 reserve;
1103
1104 u32 high_rssi_thresh_for_ra;
1105 u32 high2low_rssi_thresh_for_ra;
1106 u8 low2high_rssi_thresh_for_ra40m;
1107 u32 low_rssi_thresh_for_ra40m;
1108 u8 low2high_rssi_thresh_for_ra20m;
1109 u32 low_rssi_thresh_for_ra20m;
1110 u32 upper_rssi_threshold_ratr;
1111 u32 middleupper_rssi_threshold_ratr;
1112 u32 middle_rssi_threshold_ratr;
1113 u32 middlelow_rssi_threshold_ratr;
1114 u32 low_rssi_threshold_ratr;
1115 u32 ultralow_rssi_threshold_ratr;
1116 u32 low_rssi_threshold_ratr_40m;
1117 u32 low_rssi_threshold_ratr_20m;
1118 u8 ping_rssi_enable;
1119 u32 ping_rssi_ratr;
1120 u32 ping_rssi_thresh_for_ra;
1121 u32 last_ratr;
1122 u8 pre_ratr_state;
1123 u8 ldpc_thres;
1124 bool use_ldpc;
1125 bool lower_rts_rate;
1126 bool is_special_data;
1127 };
1128
1129 struct regd_pair_mapping {
1130 u16 reg_dmnenum;
1131 u16 reg_5ghz_ctl;
1132 u16 reg_2ghz_ctl;
1133 };
1134
1135 struct dynamic_primary_cca {
1136 u8 pricca_flag;
1137 u8 intf_flag;
1138 u8 intf_type;
1139 u8 dup_rts_flag;
1140 u8 monitor_flag;
1141 u8 ch_offset;
1142 u8 mf_state;
1143 };
1144
1145 struct rtl_regulatory {
1146 s8 alpha2[2];
1147 u16 country_code;
1148 u16 max_power_level;
1149 u32 tp_scale;
1150 u16 current_rd;
1151 u16 current_rd_ext;
1152 s16 power_limit;
1153 struct regd_pair_mapping *regpair;
1154 };
1155
1156 struct rtl_rfkill {
1157 bool rfkill_state; /*0 is off, 1 is on */
1158 };
1159
1160 /*for P2P PS**/
1161 #define P2P_MAX_NOA_NUM 2
1162
1163 enum p2p_role {
1164 P2P_ROLE_DISABLE = 0,
1165 P2P_ROLE_DEVICE = 1,
1166 P2P_ROLE_CLIENT = 2,
1167 P2P_ROLE_GO = 3
1168 };
1169
1170 enum p2p_ps_state {
1171 P2P_PS_DISABLE = 0,
1172 P2P_PS_ENABLE = 1,
1173 P2P_PS_SCAN = 2,
1174 P2P_PS_SCAN_DONE = 3,
1175 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1176 };
1177
1178 enum p2p_ps_mode {
1179 P2P_PS_NONE = 0,
1180 P2P_PS_CTWINDOW = 1,
1181 P2P_PS_NOA = 2,
1182 P2P_PS_MIX = 3, /* CTWindow and NoA */
1183 };
1184
1185 struct rtl_p2p_ps_info {
1186 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1187 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1188 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1189 /* Client traffic window. A period of time in TU after TBTT. */
1190 u8 ctwindow;
1191 u8 opp_ps; /* opportunistic power save. */
1192 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1193 /* Count for owner, Type of client. */
1194 u8 noa_count_type[P2P_MAX_NOA_NUM];
1195 /* Max duration for owner, preferred or min acceptable duration
1196 * for client.
1197 */
1198 u32 noa_duration[P2P_MAX_NOA_NUM];
1199 /* Length of interval for owner, preferred or max acceptable intervali
1200 * of client.
1201 */
1202 u32 noa_interval[P2P_MAX_NOA_NUM];
1203 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1204 u32 noa_start_time[P2P_MAX_NOA_NUM];
1205 };
1206
1207 struct p2p_ps_offload_t {
1208 u8 offload_en:1;
1209 u8 role:1; /* 1: Owner, 0: Client */
1210 u8 ctwindow_en:1;
1211 u8 noa0_en:1;
1212 u8 noa1_en:1;
1213 u8 allstasleep:1;
1214 u8 discovery:1;
1215 u8 reserved:1;
1216 };
1217
1218 #define IQK_MATRIX_REG_NUM 8
1219 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1220
1221 struct iqk_matrix_regs {
1222 bool iqk_done;
1223 long value[1][IQK_MATRIX_REG_NUM];
1224 };
1225
1226 struct phy_parameters {
1227 u16 length;
1228 u32 *pdata;
1229 };
1230
1231 enum hw_param_tab_index {
1232 PHY_REG_2T,
1233 PHY_REG_1T,
1234 PHY_REG_PG,
1235 RADIOA_2T,
1236 RADIOB_2T,
1237 RADIOA_1T,
1238 RADIOB_1T,
1239 MAC_REG,
1240 AGCTAB_2T,
1241 AGCTAB_1T,
1242 MAX_TAB
1243 };
1244
1245 struct rtl_phy {
1246 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1247 struct init_gain initgain_backup;
1248 enum io_type current_io_type;
1249
1250 u8 rf_mode;
1251 u8 rf_type;
1252 u8 current_chan_bw;
1253 u8 max_ht_chan_bw;
1254 u8 max_vht_chan_bw;
1255 u8 set_bwmode_inprogress;
1256 u8 sw_chnl_inprogress;
1257 u8 sw_chnl_stage;
1258 u8 sw_chnl_step;
1259 u8 current_channel;
1260 u8 h2c_box_num;
1261 u8 set_io_inprogress;
1262 u8 lck_inprogress;
1263
1264 /* record for power tracking */
1265 s32 reg_e94;
1266 s32 reg_e9c;
1267 s32 reg_ea4;
1268 s32 reg_eac;
1269 s32 reg_eb4;
1270 s32 reg_ebc;
1271 s32 reg_ec4;
1272 s32 reg_ecc;
1273 u8 rfpienable;
1274 u8 reserve_0;
1275 u16 reserve_1;
1276 u32 reg_c04, reg_c08, reg_874;
1277 u32 adda_backup[16];
1278 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1279 u32 iqk_bb_backup[10];
1280 bool iqk_initialized;
1281
1282 bool rfpath_rx_enable[MAX_RF_PATH];
1283 u8 reg_837;
1284 /* Dual mac */
1285 bool need_iqk;
1286 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1287
1288 bool rfpi_enable;
1289 bool iqk_in_progress;
1290
1291 u8 pwrgroup_cnt;
1292 u8 cck_high_power;
1293 /* this is for 88E & 8723A */
1294 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1295 /* MAX_PG_GROUP groups of pwr diff by rates */
1296 u32 mcs_offset[MAX_PG_GROUP][16];
1297 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1298 [TX_PWR_BY_RATE_NUM_RF]
1299 [TX_PWR_BY_RATE_NUM_RF]
1300 [TX_PWR_BY_RATE_NUM_RATE];
1301 /* compatible with TX_PWR_BY_RATE_NUM_SECTION*/
1302 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1303 [TX_PWR_BY_RATE_NUM_RF]
1304 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1305 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1306 [TX_PWR_BY_RATE_NUM_RF]
1307 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1308 u8 default_initialgain[4];
1309
1310 /* the current Tx power level */
1311 u8 cur_cck_txpwridx;
1312 u8 cur_ofdm24g_txpwridx;
1313 u8 cur_bw20_txpwridx;
1314 u8 cur_bw40_txpwridx;
1315
1316 s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
1317 [MAX_2_4G_BANDWIDTH_NUM]
1318 [MAX_RATE_SECTION_NUM]
1319 [CHANNEL_MAX_NUMBER_2G]
1320 [MAX_RF_PATH_NUM];
1321 s8 txpwr_limit_5g[MAX_REGULATION_NUM]
1322 [MAX_5G_BANDWIDTH_NUM]
1323 [MAX_RATE_SECTION_NUM]
1324 [CHANNEL_MAX_NUMBER_5G]
1325 [MAX_RF_PATH_NUM];
1326
1327 u32 rfreg_chnlval[2];
1328 bool apk_done;
1329 u32 reg_rf3c[2]; /* pathA / pathB */
1330
1331 u32 backup_rf_0x1a;/*92ee*/
1332 /* bfsync */
1333 u8 framesync;
1334 u32 framesync_c34;
1335
1336 u8 num_total_rfpath;
1337 struct phy_parameters hwparam_tables[MAX_TAB];
1338 u16 rf_pathmap;
1339
1340 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1341 enum rt_polarity_ctl polarity_ctl;
1342 };
1343
1344 #define MAX_TID_COUNT 9
1345 #define RTL_AGG_STOP 0
1346 #define RTL_AGG_PROGRESS 1
1347 #define RTL_AGG_START 2
1348 #define RTL_AGG_OPERATIONAL 3
1349 #define RTL_AGG_OFF 0
1350 #define RTL_AGG_ON 1
1351 #define RTL_RX_AGG_START 1
1352 #define RTL_RX_AGG_STOP 0
1353 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1354 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1355
1356 struct rtl_ht_agg {
1357 u16 txq_id;
1358 u16 wait_for_ba;
1359 u16 start_idx;
1360 u64 bitmap;
1361 u32 rate_n_flags;
1362 u8 agg_state;
1363 u8 rx_agg_state;
1364 };
1365
1366 struct rssi_sta {
1367 /* for old dm */
1368 long undec_sm_pwdb;
1369 long undec_sm_cck;
1370
1371 /* for new phydm_mod */
1372 s32 undecorated_smoothed_pwdb;
1373 s32 undecorated_smoothed_cck;
1374 s32 undecorated_smoothed_ofdm;
1375 u8 ofdm_pkt;
1376 u8 cck_pkt;
1377 u16 cck_sum_power;
1378 u8 is_send_rssi;
1379 u64 packet_map;
1380 u8 valid_bit;
1381 };
1382
1383 struct rtl_tid_data {
1384 u16 seq_number;
1385 struct rtl_ht_agg agg;
1386 };
1387
1388 struct rtl_sta_info {
1389 struct list_head list;
1390 struct rtl_tid_data tids[MAX_TID_COUNT];
1391 /* just used for ap adhoc or mesh*/
1392 struct rssi_sta rssi_stat;
1393 u8 rssi_level;
1394 u16 wireless_mode;
1395 u8 ratr_index;
1396 u8 mimo_ps;
1397 u8 mac_addr[ETH_ALEN];
1398 } __packed;
1399
1400 struct rtl_priv;
1401 struct rtl_io {
1402 struct device *dev;
1403 struct mutex bb_mutex;
1404
1405 /*PCI MEM map */
1406 unsigned long pci_mem_end; /*shared mem end */
1407 unsigned long pci_mem_start; /*shared mem start */
1408
1409 /*PCI IO map */
1410 unsigned long pci_base_addr; /*device I/O address */
1411
1412 void (*write8_async)(struct rtl_priv *rtlpriv, u32 addr, u8 val);
1413 void (*write16_async)(struct rtl_priv *rtlpriv, u32 addr, u16 val);
1414 void (*write32_async)(struct rtl_priv *rtlpriv, u32 addr, u32 val);
1415 void (*writeN_sync)(struct rtl_priv *rtlpriv, u32 addr, void *buf,
1416 u16 len);
1417
1418 u8 (*read8_sync)(struct rtl_priv *rtlpriv, u32 addr);
1419 u16 (*read16_sync)(struct rtl_priv *rtlpriv, u32 addr);
1420 u32 (*read32_sync)(struct rtl_priv *rtlpriv, u32 addr);
1421
1422 };
1423
1424 struct rtl_mac {
1425 u8 mac_addr[ETH_ALEN];
1426 u8 mac80211_registered;
1427 u8 beacon_enabled;
1428
1429 u32 tx_ss_num;
1430 u32 rx_ss_num;
1431
1432 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1433 struct ieee80211_hw *hw;
1434 struct ieee80211_vif *vif;
1435 enum nl80211_iftype opmode;
1436
1437 /*Probe Beacon management */
1438 struct rtl_tid_data tids[MAX_TID_COUNT];
1439 enum rtl_link_state link_state;
1440 struct rtl_beacon_keys cur_beacon_keys;
1441 u8 new_beacon_cnt;
1442
1443 int n_channels;
1444 int n_bitrates;
1445
1446 bool offchan_delay;
1447 u8 p2p; /*using p2p role*/
1448 bool p2p_in_use;
1449
1450 /*filters */
1451 u32 rx_conf;
1452 u16 rx_mgt_filter;
1453 u16 rx_ctrl_filter;
1454 u16 rx_data_filter;
1455
1456 bool act_scanning;
1457 u8 cnt_after_linked;
1458 bool skip_scan;
1459
1460 /* early mode */
1461 /* skb wait queue */
1462 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1463
1464 u8 ht_stbc_cap;
1465 u8 ht_cur_stbc;
1466
1467 /*vht support*/
1468 u8 vht_enable;
1469 u8 bw_80;
1470 u8 vht_cur_ldpc;
1471 u8 vht_cur_stbc;
1472 u8 vht_stbc_cap;
1473 u8 vht_ldpc_cap;
1474
1475 /*RDG*/
1476 bool rdg_en;
1477
1478 /*AP*/
1479 u8 bssid[ETH_ALEN] __aligned(2);
1480 u32 vendor;
1481 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1482 u32 basic_rates; /* b/g rates */
1483 u8 ht_enable;
1484 u8 sgi_40;
1485 u8 sgi_20;
1486 u8 bw_40;
1487 u16 mode; /* wireless mode */
1488 u8 slot_time;
1489 u8 short_preamble;
1490 u8 use_cts_protect;
1491 u8 cur_40_prime_sc;
1492 u8 cur_40_prime_sc_bk;
1493 u8 cur_80_prime_sc;
1494 u64 tsf;
1495 u8 retry_short;
1496 u8 retry_long;
1497 u16 assoc_id;
1498 bool hiddenssid;
1499
1500 /*IBSS*/
1501 int beacon_interval;
1502
1503 /*AMPDU*/
1504 u8 min_space_cfg; /*For Min spacing configurations */
1505 u8 max_mss_density;
1506 u8 current_ampdu_factor;
1507 u8 current_ampdu_density;
1508
1509 /*QOS & EDCA */
1510 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1511 struct rtl_qos_parameters ac[AC_MAX];
1512
1513 /* counters */
1514 u64 last_txok_cnt;
1515 u64 last_rxok_cnt;
1516 u32 last_bt_edca_ul;
1517 u32 last_bt_edca_dl;
1518 };
1519
1520 struct btdm_8723 {
1521 bool all_off;
1522 bool agc_table_en;
1523 bool adc_back_off_on;
1524 bool b2_ant_hid_en;
1525 bool low_penalty_rate_adaptive;
1526 bool rf_rx_lpf_shrink;
1527 bool reject_aggre_pkt;
1528 bool tra_tdma_on;
1529 u8 tra_tdma_nav;
1530 u8 tra_tdma_ant;
1531 bool tdma_on;
1532 u8 tdma_ant;
1533 u8 tdma_nav;
1534 u8 tdma_dac_swing;
1535 u8 fw_dac_swing_lvl;
1536 bool ps_tdma_on;
1537 u8 ps_tdma_byte[5];
1538 bool pta_on;
1539 u32 val_0x6c0;
1540 u32 val_0x6c8;
1541 u32 val_0x6cc;
1542 bool sw_dac_swing_on;
1543 u32 sw_dac_swing_lvl;
1544 u32 wlan_act_hi;
1545 u32 wlan_act_lo;
1546 u32 bt_retry_index;
1547 bool dec_bt_pwr;
1548 bool ignore_wlan_act;
1549 };
1550
1551 struct bt_coexist_8723 {
1552 u32 high_priority_tx;
1553 u32 high_priority_rx;
1554 u32 low_priority_tx;
1555 u32 low_priority_rx;
1556 u8 c2h_bt_info;
1557 bool c2h_bt_info_req_sent;
1558 bool c2h_bt_inquiry_page;
1559 u32 bt_inq_page_start_time;
1560 u8 bt_retry_cnt;
1561 u8 c2h_bt_info_original;
1562 u8 bt_inquiry_page_cnt;
1563 struct btdm_8723 btdm;
1564 };
1565
1566 struct rtl_hal {
1567 struct ieee80211_hw *hw;
1568 bool driver_is_goingto_unload;
1569 bool up_first_time;
1570 bool first_init;
1571 bool being_init_adapter;
1572 bool bbrf_ready;
1573 bool mac_func_enable;
1574 bool pre_edcca_enable;
1575 struct bt_coexist_8723 hal_coex_8723;
1576
1577 enum intf_type interface;
1578 u16 hw_type; /*92c or 92d or 92s and so on */
1579 u8 ic_class;
1580 u8 oem_id;
1581 u32 version; /*version of chip */
1582 u8 state; /*stop 0, start 1 */
1583 u8 board_type;
1584 u8 package_type;
1585 u8 external_pa;
1586
1587 u8 pa_mode;
1588 u8 pa_type_2g;
1589 u8 pa_type_5g;
1590 u8 lna_type_2g;
1591 u8 lna_type_5g;
1592 u8 external_pa_2g;
1593 u8 external_lna_2g;
1594 u8 external_pa_5g;
1595 u8 external_lna_5g;
1596 u8 type_glna;
1597 u8 type_gpa;
1598 u8 type_alna;
1599 u8 type_apa;
1600 u8 rfe_type;
1601
1602 /*firmware */
1603 u32 fwsize;
1604 u8 *pfirmware;
1605 u16 fw_version;
1606 u16 fw_subversion;
1607 bool h2c_setinprogress;
1608 u8 last_hmeboxnum;
1609 bool fw_ready;
1610 /*Reserve page start offset except beacon in TxQ. */
1611 u8 fw_rsvdpage_startoffset;
1612 u8 h2c_txcmd_seq;
1613 u8 current_ra_rate;
1614
1615 /* FW Cmd IO related */
1616 u16 fwcmd_iomap;
1617 u32 fwcmd_ioparam;
1618 bool set_fwcmd_inprogress;
1619 u8 current_fwcmd_io;
1620
1621 struct p2p_ps_offload_t p2p_ps_offload;
1622 bool fw_clk_change_in_progress;
1623 bool allow_sw_to_change_hwclc;
1624 u8 fw_ps_state;
1625 /**/
1626 bool driver_going2unload;
1627
1628 /*AMPDU init min space*/
1629 u8 minspace_cfg; /*For Min spacing configurations */
1630
1631 /* Dual mac */
1632 enum macphy_mode macphymode;
1633 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1634 enum band_type current_bandtypebackup;
1635 enum band_type bandset;
1636 /* dual MAC 0--Mac0 1--Mac1 */
1637 u32 interfaceindex;
1638 /* just for DualMac S3S4 */
1639 u8 macphyctl_reg;
1640 bool earlymode_enable;
1641 u8 max_earlymode_num;
1642 /* Dual mac*/
1643 bool during_mac0init_radiob;
1644 bool during_mac1init_radioa;
1645 bool reloadtxpowerindex;
1646 /* True if IMR or IQK have done
1647 * for 2.4G in scan progress
1648 */
1649 bool load_imrandiqk_setting_for2g;
1650
1651 bool disable_amsdu_8k;
1652 bool master_of_dmsp;
1653 bool slave_of_dmsp;
1654
1655 u16 rx_tag;/*for 92ee*/
1656 u8 rts_en;
1657
1658 /*for wowlan*/
1659 bool wow_enable;
1660 bool enter_pnp_sleep;
1661 bool wake_from_pnp_sleep;
1662 bool wow_enabled;
1663 time64_t last_suspend_sec;
1664 u32 wowlan_fwsize;
1665 u8 *wowlan_firmware;
1666
1667 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1668
1669 bool real_wow_v2_enable;
1670 bool re_init_llt_table;
1671 };
1672
1673 struct rtl_security {
1674 /*default 0 */
1675 bool use_sw_sec;
1676
1677 bool being_setkey;
1678 bool use_defaultkey;
1679 /*Encryption Algorithm for Unicast Packet */
1680 enum rt_enc_alg pairwise_enc_algorithm;
1681 /*Encryption Algorithm for Brocast/Multicast */
1682 enum rt_enc_alg group_enc_algorithm;
1683 /*Cam Entry Bitmap */
1684 u32 hwsec_cam_bitmap;
1685 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1686 /* local Key buffer, indx 0 is for
1687 * pairwise key 1-4 is for agoup key.
1688 */
1689 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1690 u8 key_len[KEY_BUF_SIZE];
1691
1692 /* The pointer of Pairwise Key,
1693 * it always points to KeyBuf[4]
1694 */
1695 u8 *pairwise_key;
1696 };
1697
1698 #define ASSOCIATE_ENTRY_NUM 33
1699
1700 struct fast_ant_training {
1701 u8 bssid[6];
1702 u8 antsel_rx_keep_0;
1703 u8 antsel_rx_keep_1;
1704 u8 antsel_rx_keep_2;
1705 u32 ant_sum[7];
1706 u32 ant_cnt[7];
1707 u32 ant_ave[7];
1708 u8 fat_state;
1709 u32 train_idx;
1710 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1711 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1712 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1713 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1714 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1715 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1716 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1717 u8 rx_idle_ant;
1718 bool becomelinked;
1719 };
1720
1721 struct dm_phy_dbg_info {
1722 s8 rx_snrdb[4];
1723 u64 num_qry_phy_status;
1724 u64 num_qry_phy_status_cck;
1725 u64 num_qry_phy_status_ofdm;
1726 u16 num_qry_beacon_pkt;
1727 u16 num_non_be_pkt;
1728 s32 rx_evm[4];
1729 };
1730
1731 struct rtl_dm {
1732 /*PHY status for Dynamic Management */
1733 long entry_min_undec_sm_pwdb;
1734 long undec_sm_cck;
1735 long undec_sm_pwdb; /*out dm */
1736 long entry_max_undec_sm_pwdb;
1737 s32 ofdm_pkt_cnt;
1738 bool dm_initialgain_enable;
1739 bool dynamic_txpower_enable;
1740 bool current_turbo_edca;
1741 bool is_any_nonbepkts; /*out dm */
1742 bool is_cur_rdlstate;
1743 bool txpower_trackinginit;
1744 bool disable_framebursting;
1745 bool cck_inch14;
1746 bool txpower_tracking;
1747 bool useramask;
1748 bool rfpath_rxenable[4];
1749 bool inform_fw_driverctrldm;
1750 bool current_mrc_switch;
1751 u8 txpowercount;
1752 u8 powerindex_backup[6];
1753
1754 u8 thermalvalue_rxgain;
1755 u8 thermalvalue_iqk;
1756 u8 thermalvalue_lck;
1757 u8 thermalvalue;
1758 u8 last_dtp_lvl;
1759 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1760 u8 thermalvalue_avg_index;
1761 u8 tm_trigger;
1762 bool done_txpower;
1763 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1764 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1765 u8 dm_flag_tmp;
1766 u8 dm_type;
1767 u8 dm_rssi_sel;
1768 u8 txpower_track_control;
1769 bool interrupt_migration;
1770 bool disable_tx_int;
1771 s8 ofdm_index[MAX_RF_PATH];
1772 u8 default_ofdm_index;
1773 u8 default_cck_index;
1774 s8 cck_index;
1775 s8 delta_power_index[MAX_RF_PATH];
1776 s8 delta_power_index_last[MAX_RF_PATH];
1777 s8 power_index_offset[MAX_RF_PATH];
1778 s8 absolute_ofdm_swing_idx[MAX_RF_PATH];
1779 s8 remnant_ofdm_swing_idx[MAX_RF_PATH];
1780 s8 remnant_cck_idx;
1781 bool modify_txagc_flag_path_a;
1782 bool modify_txagc_flag_path_b;
1783
1784 bool one_entry_only;
1785 struct dm_phy_dbg_info dbginfo;
1786
1787 /* Dynamic ATC switch */
1788 bool atc_status;
1789 bool large_cfo_hit;
1790 bool is_freeze;
1791 int cfo_tail[2];
1792 int cfo_ave_pre;
1793 int crystal_cap;
1794 u8 cfo_threshold;
1795 u32 packet_count;
1796 u32 packet_count_pre;
1797 u8 tx_rate;
1798
1799 /*88e tx power tracking*/
1800 u8 swing_idx_ofdm[MAX_RF_PATH];
1801 u8 swing_idx_ofdm_cur;
1802 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1803 bool swing_flag_ofdm;
1804 u8 swing_idx_cck;
1805 u8 swing_idx_cck_cur;
1806 u8 swing_idx_cck_base;
1807 bool swing_flag_cck;
1808
1809 s8 swing_diff_2g;
1810 s8 swing_diff_5g;
1811
1812 /* DMSP */
1813 bool supp_phymode_switch;
1814
1815 /* DulMac */
1816 struct fast_ant_training fat_table;
1817
1818 u8 resp_tx_path;
1819 u8 path_sel;
1820 u32 patha_sum;
1821 u32 pathb_sum;
1822 u32 patha_cnt;
1823 u32 pathb_cnt;
1824
1825 u8 pre_channel;
1826 u8 *p_channel;
1827 u8 linked_interval;
1828
1829 u64 last_tx_ok_cnt;
1830 u64 last_rx_ok_cnt;
1831 };
1832
1833 #define EFUSE_MAX_LOGICAL_SIZE 512
1834
1835 struct rtl_efuse {
1836 bool autoload_ok;
1837 bool bootfromefuse;
1838 u16 max_physical_size;
1839
1840 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1841 u16 efuse_usedbytes;
1842 u8 efuse_usedpercentage;
1843
1844 u8 autoload_failflag;
1845 u8 autoload_status;
1846
1847 short epromtype;
1848 u16 eeprom_vid;
1849 u16 eeprom_did;
1850 u16 eeprom_svid;
1851 u16 eeprom_smid;
1852 u8 eeprom_oemid;
1853 u16 eeprom_channelplan;
1854 u8 eeprom_version;
1855 u8 board_type;
1856 u8 external_pa;
1857
1858 u8 dev_addr[6];
1859 u8 wowlan_enable;
1860 u8 antenna_div_cfg;
1861 u8 antenna_div_type;
1862
1863 bool txpwr_fromeprom;
1864 u8 eeprom_crystalcap;
1865 u8 eeprom_tssi[2];
1866 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1867 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1868 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1869 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1870 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1871 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1872
1873 u8 internal_pa_5g[2]; /* pathA / pathB */
1874 u8 eeprom_c9;
1875 u8 eeprom_cc;
1876
1877 /*For power group */
1878 u8 eeprom_pwrgroup[2][3];
1879 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1880 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1881
1882 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1883 /*For HT 40MHZ pwr */
1884 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1885 /*For HT 40MHZ pwr */
1886 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1887
1888 /*--------------------------------------------------------*
1889 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1890 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1891 * define new arrays in Windows code.
1892 * BUT, in linux code, we use the same array for all ICs.
1893 *
1894 * The Correspondance relation between two arrays is:
1895 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1896 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1897 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1898 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1899 *
1900 * Sizes of these arrays are decided by the larger ones.
1901 */
1902 s8 txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1903 s8 txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1904 s8 txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1905 s8 txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1906
1907 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1908 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1909 s8 txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1910 s8 txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1911 s8 txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1912 s8 txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1913
1914 u8 txpwr_safetyflag; /* Band edge enable flag */
1915 u16 eeprom_txpowerdiff;
1916 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1917 u8 antenna_txpwdiff[3];
1918
1919 u8 eeprom_regulatory;
1920 u8 eeprom_thermalmeter;
1921 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1922 u16 tssi_13dbm;
1923 u8 crystalcap; /* CrystalCap. */
1924 u8 delta_iqk;
1925 u8 delta_lck;
1926
1927 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1928 bool apk_thermalmeterignore;
1929
1930 bool b1x1_recvcombine;
1931 bool b1ss_support;
1932
1933 /*channel plan */
1934 u8 channel_plan;
1935 };
1936
1937 struct rtl_tx_report {
1938 atomic_t sn;
1939 u16 last_sent_sn;
1940 unsigned long last_sent_time;
1941 u16 last_recv_sn;
1942 };
1943
1944 struct rtl_ps_ctl {
1945 bool pwrdomain_protect;
1946 bool in_powersavemode;
1947 bool rfchange_inprogress;
1948 bool swrf_processing;
1949 bool hwradiooff;
1950 /* just for PCIE ASPM
1951 * If it supports ASPM, Offset[560h] = 0x40,
1952 * otherwise Offset[560h] = 0x00.
1953 */
1954 bool support_aspm;
1955 bool support_backdoor;
1956
1957 /*for LPS */
1958 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1959 bool swctrl_lps;
1960 bool leisure_ps;
1961 bool fwctrl_lps;
1962 u8 fwctrl_psmode;
1963 /*For Fw control LPS mode */
1964 u8 reg_fwctrl_lps;
1965 /*Record Fw PS mode status. */
1966 bool fw_current_inpsmode;
1967 u8 reg_max_lps_awakeintvl;
1968 bool report_linked;
1969 bool low_power_enable;/*for 32k*/
1970
1971 /*for IPS */
1972 bool inactiveps;
1973
1974 u32 rfoff_reason;
1975
1976 /*RF OFF Level */
1977 u32 cur_ps_level;
1978 u32 reg_rfps_level;
1979
1980 /*just for PCIE ASPM */
1981 u8 const_amdpci_aspm;
1982 bool pwrdown_mode;
1983
1984 enum rf_pwrstate inactive_pwrstate;
1985 enum rf_pwrstate rfpwr_state; /*cur power state */
1986
1987 /* for SW LPS*/
1988 bool sw_ps_enabled;
1989 bool state;
1990 bool state_inap;
1991 bool multi_buffered;
1992 u16 nullfunc_seq;
1993 unsigned int dtim_counter;
1994 unsigned int sleep_ms;
1995 unsigned long last_sleep_jiffies;
1996 unsigned long last_awake_jiffies;
1997 unsigned long last_delaylps_stamp_jiffies;
1998 unsigned long last_dtim;
1999 unsigned long last_beacon;
2000 unsigned long last_action;
2001 unsigned long last_slept;
2002
2003 /*For P2P PS */
2004 struct rtl_p2p_ps_info p2p_ps_info;
2005 u8 pwr_mode;
2006 u8 smart_ps;
2007
2008 /* wake up on line */
2009 u8 wo_wlan_mode;
2010 u8 arp_offload_enable;
2011 u8 gtk_offload_enable;
2012 /* Used for WOL, indicates the reason for waking event.*/
2013 u32 wakeup_reason;
2014 /* Record the last waking time for comparison with setting key. */
2015 u64 last_wakeup_time;
2016 };
2017
2018 struct rtl_stats {
2019 u8 psaddr[ETH_ALEN];
2020 u32 mac_time[2];
2021 s8 rssi;
2022 u8 signal;
2023 u8 noise;
2024 u8 rate; /* hw desc rate */
2025 u8 received_channel;
2026 u8 control;
2027 u8 mask;
2028 u8 freq;
2029 u16 len;
2030 u64 tsf;
2031 u32 beacon_time;
2032 u8 nic_type;
2033 u16 length;
2034 u8 signalquality; /*in 0-100 index. */
2035 /*
2036 * Real power in dBm for this packet,
2037 * no beautification and aggregation.
2038 */
2039 s32 recvsignalpower;
2040 s8 rxpower; /*in dBm Translate from PWdB */
2041 u8 signalstrength; /*in 0-100 index. */
2042 u16 hwerror:1;
2043 u16 crc:1;
2044 u16 icv:1;
2045 u16 shortpreamble:1;
2046 u16 antenna:1;
2047 u16 decrypted:1;
2048 u16 wakeup:1;
2049 u32 timestamp_low;
2050 u32 timestamp_high;
2051 bool shift;
2052
2053 u8 rx_drvinfo_size;
2054 u8 rx_bufshift;
2055 bool isampdu;
2056 bool isfirst_ampdu;
2057 bool rx_is40mhzpacket;
2058 u8 rx_packet_bw;
2059 u32 rx_pwdb_all;
2060 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
2061 s8 rx_mimo_signalquality[4];
2062 u8 rx_mimo_evm_dbm[4];
2063 u16 cfo_short[4]; /* per-path's Cfo_short */
2064 u16 cfo_tail[4];
2065
2066 s8 rx_mimo_sig_qual[4];
2067 u8 rx_pwr[4]; /* per-path's pwdb */
2068 u8 rx_snr[4]; /* per-path's SNR */
2069 u8 bandwidth;
2070 u8 bt_coex_pwr_adjust;
2071 bool packet_matchbssid;
2072 bool is_cck;
2073 bool is_ht;
2074 bool packet_toself;
2075 bool packet_beacon; /*for rssi */
2076 s8 cck_adc_pwdb[4]; /*for rx path selection */
2077
2078 bool is_vht;
2079 bool is_short_gi;
2080 u8 vht_nss;
2081
2082 u8 packet_report_type;
2083
2084 u32 macid;
2085 u8 wake_match;
2086 u32 bt_rx_rssi_percentage;
2087 u32 macid_valid_entry[2];
2088 };
2089
2090 struct rt_link_detect {
2091 /* count for roaming */
2092 u32 bcn_rx_inperiod;
2093 u32 roam_times;
2094
2095 u32 num_tx_in4period[4];
2096 u32 num_rx_in4period[4];
2097
2098 u32 num_tx_inperiod;
2099 u32 num_rx_inperiod;
2100
2101 bool busytraffic;
2102 bool tx_busy_traffic;
2103 bool rx_busy_traffic;
2104 bool higher_busytraffic;
2105 bool higher_busyrxtraffic;
2106
2107 u32 tidtx_in4period[MAX_TID_COUNT][4];
2108 u32 tidtx_inperiod[MAX_TID_COUNT];
2109 bool higher_busytxtraffic[MAX_TID_COUNT];
2110 };
2111
2112 struct rtl_tcb_desc {
2113 u8 packet_bw:2;
2114 u8 multicast:1;
2115 u8 broadcast:1;
2116
2117 u8 rts_stbc:1;
2118 u8 rts_enable:1;
2119 u8 cts_enable:1;
2120 u8 rts_use_shortpreamble:1;
2121 u8 rts_use_shortgi:1;
2122 u8 rts_sc:1;
2123 u8 rts_bw:1;
2124 u8 rts_rate;
2125
2126 u8 use_shortgi:1;
2127 u8 use_shortpreamble:1;
2128 u8 use_driver_rate:1;
2129 u8 disable_ratefallback:1;
2130
2131 u8 use_spe_rpt:1;
2132
2133 u8 ratr_index;
2134 u8 mac_id;
2135 u8 hw_rate;
2136
2137 u8 last_inipkt:1;
2138 u8 cmd_or_init:1;
2139 u8 queue_index;
2140
2141 /* early mode */
2142 u8 empkt_num;
2143 /* The max value by HW */
2144 u32 empkt_len[10];
2145 bool tx_enable_sw_calc_duration;
2146 };
2147
2148 struct rtl_wow_pattern {
2149 u8 type;
2150 u16 crc;
2151 u32 mask[4];
2152 };
2153
2154 struct rtl_hal_ops {
2155 int (*init_sw_vars)(struct ieee80211_hw *hw);
2156 void (*deinit_sw_vars)(struct ieee80211_hw *hw);
2157 void (*read_chip_version)(struct ieee80211_hw *hw);
2158 void (*read_eeprom_info)(struct ieee80211_hw *hw);
2159 void (*interrupt_recognized)(struct ieee80211_hw *hw,
2160 u32 *p_inta, u32 *p_intb,
2161 u32 *p_intc, u32 *p_intd);
2162 int (*hw_init)(struct ieee80211_hw *hw);
2163 void (*hw_disable)(struct ieee80211_hw *hw);
2164 void (*hw_suspend)(struct ieee80211_hw *hw);
2165 void (*hw_resume)(struct ieee80211_hw *hw);
2166 void (*enable_interrupt)(struct ieee80211_hw *hw);
2167 void (*disable_interrupt)(struct ieee80211_hw *hw);
2168 int (*set_network_type)(struct ieee80211_hw *hw,
2169 enum nl80211_iftype type);
2170 void (*set_chk_bssid)(struct ieee80211_hw *hw,
2171 bool check_bssid);
2172 void (*set_bw_mode)(struct ieee80211_hw *hw,
2173 enum nl80211_channel_type ch_type);
2174 u8 (*switch_channel)(struct ieee80211_hw *hw);
2175 void (*set_qos)(struct ieee80211_hw *hw, int aci);
2176 void (*set_bcn_reg)(struct ieee80211_hw *hw);
2177 void (*set_bcn_intv)(struct ieee80211_hw *hw);
2178 void (*update_interrupt_mask)(struct ieee80211_hw *hw,
2179 u32 add_msr, u32 rm_msr);
2180 void (*get_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2181 void (*set_hw_reg)(struct ieee80211_hw *hw, u8 variable, u8 *val);
2182 void (*update_rate_tbl)(struct ieee80211_hw *hw,
2183 struct ieee80211_sta *sta, u8 rssi_leve,
2184 bool update_bw);
2185 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2186 u8 *desc, u8 queue_index,
2187 struct sk_buff *skb, dma_addr_t addr);
2188 void (*update_rate_mask)(struct ieee80211_hw *hw, u8 rssi_level);
2189 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2190 u8 queue_index);
2191 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2192 u8 queue_index);
2193 void (*fill_tx_desc)(struct ieee80211_hw *hw,
2194 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2195 u8 *pbd_desc_tx,
2196 struct ieee80211_tx_info *info,
2197 struct ieee80211_sta *sta,
2198 struct sk_buff *skb, u8 hw_queue,
2199 struct rtl_tcb_desc *ptcb_desc);
2200 void (*fill_fake_txdesc)(struct ieee80211_hw *hw, u8 *pdesc,
2201 u32 buffer_len, bool bispspoll);
2202 void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc,
2203 bool firstseg, bool lastseg,
2204 struct sk_buff *skb);
2205 void (*fill_tx_special_desc)(struct ieee80211_hw *hw,
2206 u8 *pdesc, u8 *pbd_desc,
2207 struct sk_buff *skb, u8 hw_queue);
2208 bool (*query_rx_desc)(struct ieee80211_hw *hw,
2209 struct rtl_stats *stats,
2210 struct ieee80211_rx_status *rx_status,
2211 u8 *pdesc, struct sk_buff *skb);
2212 void (*set_channel_access)(struct ieee80211_hw *hw);
2213 bool (*radio_onoff_checking)(struct ieee80211_hw *hw, u8 *valid);
2214 void (*dm_watchdog)(struct ieee80211_hw *hw);
2215 void (*scan_operation_backup)(struct ieee80211_hw *hw, u8 operation);
2216 bool (*set_rf_power_state)(struct ieee80211_hw *hw,
2217 enum rf_pwrstate rfpwr_state);
2218 void (*led_control)(struct ieee80211_hw *hw,
2219 enum led_ctl_mode ledaction);
2220 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2221 u8 desc_name, u8 *val);
2222 u64 (*get_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2223 u8 desc_name);
2224 bool (*is_tx_desc_closed)(struct ieee80211_hw *hw,
2225 u8 hw_queue, u16 index);
2226 void (*tx_polling)(struct ieee80211_hw *hw, u8 hw_queue);
2227 void (*enable_hw_sec)(struct ieee80211_hw *hw);
2228 void (*set_key)(struct ieee80211_hw *hw, u32 key_index,
2229 u8 *macaddr, bool is_group, u8 enc_algo,
2230 bool is_wepkey, bool clear_all);
2231 void (*init_sw_leds)(struct ieee80211_hw *hw);
2232 void (*deinit_sw_leds)(struct ieee80211_hw *hw);
2233 u32 (*get_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2234 void (*set_bbreg)(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2235 u32 data);
2236 u32 (*get_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2237 u32 regaddr, u32 bitmask);
2238 void (*set_rfreg)(struct ieee80211_hw *hw, enum radio_path rfpath,
2239 u32 regaddr, u32 bitmask, u32 data);
2240 void (*linked_set_reg)(struct ieee80211_hw *hw);
2241 void (*chk_switch_dmdp)(struct ieee80211_hw *hw);
2242 void (*dualmac_easy_concurrent)(struct ieee80211_hw *hw);
2243 void (*dualmac_switch_to_dmdp)(struct ieee80211_hw *hw);
2244 bool (*phy_rf6052_config)(struct ieee80211_hw *hw);
2245 void (*phy_rf6052_set_cck_txpower)(struct ieee80211_hw *hw,
2246 u8 *powerlevel);
2247 void (*phy_rf6052_set_ofdm_txpower)(struct ieee80211_hw *hw,
2248 u8 *ppowerlevel, u8 channel);
2249 bool (*config_bb_with_headerfile)(struct ieee80211_hw *hw,
2250 u8 configtype);
2251 bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw,
2252 u8 configtype);
2253 void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t);
2254 void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw);
2255 void (*dm_dynamic_txpower)(struct ieee80211_hw *hw);
2256 void (*c2h_command_handle)(struct ieee80211_hw *hw);
2257 void (*bt_wifi_media_status_notify)(struct ieee80211_hw *hw,
2258 bool mstate);
2259 void (*bt_coex_off_before_lps)(struct ieee80211_hw *hw);
2260 void (*fill_h2c_cmd)(struct ieee80211_hw *hw, u8 element_id,
2261 u32 cmd_len, u8 *p_cmdbuffer);
2262 void (*set_default_port_id_cmd)(struct ieee80211_hw *hw);
2263 bool (*get_btc_status)(void);
2264 bool (*is_fw_header)(struct rtlwifi_firmware_header *hdr);
2265 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2266 const struct rtl_stats *status,
2267 struct sk_buff *skb);
2268 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2269 struct rtl_wow_pattern *rtl_pattern,
2270 u8 index);
2271 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2272 void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
2273 u8 *val);
2274 /* ops for halmac cb */
2275 bool (*halmac_cb_init_mac_register)(struct rtl_priv *rtlpriv);
2276 bool (*halmac_cb_init_bb_rf_register)(struct rtl_priv *rtlpriv);
2277 bool (*halmac_cb_write_data_rsvd_page)(struct rtl_priv *rtlpriv,
2278 u8 *buf, u32 size);
2279 bool (*halmac_cb_write_data_h2c)(struct rtl_priv *rtlpriv, u8 *buf,
2280 u32 size);
2281 /* ops for phydm cb */
2282 u8 (*get_txpower_index)(struct ieee80211_hw *hw, u8 path,
2283 u8 rate, u8 bandwidth, u8 channel);
2284 void (*set_tx_power_index_by_rs)(struct ieee80211_hw *hw,
2285 u8 channel, u8 path,
2286 enum rate_section rs);
2287 void (*store_tx_power_by_rate)(struct ieee80211_hw *hw,
2288 u32 band, u32 rfpath,
2289 u32 txnum, u32 regaddr,
2290 u32 bitmask, u32 data);
2291 void (*phy_set_txpower_limit)(struct ieee80211_hw *hw, u8 *pregulation,
2292 u8 *pband, u8 *pbandwidth,
2293 u8 *prate_section, u8 *prf_path,
2294 u8 *pchannel, u8 *ppower_limit);
2295 };
2296
2297 struct rtl_intf_ops {
2298 /*com */
2299 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2300 int (*adapter_start)(struct ieee80211_hw *hw);
2301 void (*adapter_stop)(struct ieee80211_hw *hw);
2302 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2303 struct rtl_priv **buddy_priv);
2304
2305 int (*adapter_tx)(struct ieee80211_hw *hw,
2306 struct ieee80211_sta *sta,
2307 struct sk_buff *skb,
2308 struct rtl_tcb_desc *ptcb_desc);
2309 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2310 int (*reset_trx_ring)(struct ieee80211_hw *hw);
2311 bool (*waitq_insert)(struct ieee80211_hw *hw,
2312 struct ieee80211_sta *sta,
2313 struct sk_buff *skb);
2314
2315 /*pci */
2316 void (*disable_aspm)(struct ieee80211_hw *hw);
2317 void (*enable_aspm)(struct ieee80211_hw *hw);
2318
2319 /*usb */
2320 };
2321
2322 struct rtl_mod_params {
2323 /* default: 0,0 */
2324 u64 debug_mask;
2325 /* default: 0 = using hardware encryption */
2326 bool sw_crypto;
2327
2328 /* default: 0 = DBG_EMERG (0)*/
2329 int debug_level;
2330
2331 /* default: 1 = using no linked power save */
2332 bool inactiveps;
2333
2334 /* default: 1 = using linked sw power save */
2335 bool swctrl_lps;
2336
2337 /* default: 1 = using linked fw power save */
2338 bool fwctrl_lps;
2339
2340 /* default: 0 = not using MSI interrupts mode
2341 * submodules should set their own default value
2342 */
2343 bool msi_support;
2344
2345 /* default: 0 = dma 32 */
2346 bool dma64;
2347
2348 /* default: 1 = enable aspm */
2349 int aspm_support;
2350
2351 /* default 0: 1 means disable */
2352 bool disable_watchdog;
2353
2354 /* default 0: 1 means do not disable interrupts */
2355 bool int_clear;
2356
2357 /* select antenna */
2358 int ant_sel;
2359 };
2360
2361 struct rtl_hal_usbint_cfg {
2362 /* data - rx */
2363 u32 in_ep_num;
2364 u32 rx_urb_num;
2365 u32 rx_max_size;
2366
2367 /* op - rx */
2368 void (*usb_rx_hdl)(struct ieee80211_hw *hw, struct sk_buff *skb);
2369 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *hw,
2370 struct sk_buff *skb,
2371 struct sk_buff_head *skbh);
2372
2373 /* tx */
2374 void (*usb_tx_cleanup)(struct ieee80211_hw *hw, struct sk_buff *skb);
2375 int (*usb_tx_post_hdl)(struct ieee80211_hw *hw, struct urb *urb,
2376 struct sk_buff *skb);
2377 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *hw,
2378 struct sk_buff_head *skbh);
2379
2380 /* endpoint mapping */
2381 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2382 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2383 };
2384
2385 struct rtl_hal_cfg {
2386 u8 bar_id;
2387 bool write_readback;
2388 char *name;
2389 char *alt_fw_name;
2390 struct rtl_hal_ops *ops;
2391 struct rtl_mod_params *mod_params;
2392 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2393 enum rtl_spec_ver spec_ver;
2394
2395 /* this map used for some registers or vars
2396 * defined int HAL but used in MAIN
2397 */
2398 u32 maps[RTL_VAR_MAP_MAX];
2399
2400 };
2401
2402 struct rtl_locks {
2403 /* mutex */
2404 struct mutex conf_mutex;
2405 struct mutex ips_mutex; /* mutex for enter/leave IPS */
2406 struct mutex lps_mutex; /* mutex for enter/leave LPS */
2407
2408 /*spin lock */
2409 spinlock_t irq_th_lock;
2410 spinlock_t h2c_lock;
2411 spinlock_t rf_ps_lock;
2412 spinlock_t rf_lock;
2413 spinlock_t waitq_lock;
2414 spinlock_t entry_list_lock;
2415 spinlock_t usb_lock;
2416 spinlock_t c2hcmd_lock;
2417 spinlock_t scan_list_lock; /* lock for the scan list */
2418
2419 /*FW clock change */
2420 spinlock_t fw_ps_lock;
2421
2422 /*Dual mac*/
2423 spinlock_t cck_and_rw_pagea_lock;
2424
2425 spinlock_t iqk_lock;
2426 };
2427
2428 struct rtl_works {
2429 struct ieee80211_hw *hw;
2430
2431 /*timer */
2432 struct timer_list watchdog_timer;
2433 struct timer_list dualmac_easyconcurrent_retrytimer;
2434 struct timer_list fw_clockoff_timer;
2435 struct timer_list fast_antenna_training_timer;
2436 /*task */
2437 struct tasklet_struct irq_tasklet;
2438 struct tasklet_struct irq_prepare_bcn_tasklet;
2439
2440 /*work queue */
2441 struct workqueue_struct *rtl_wq;
2442 struct delayed_work watchdog_wq;
2443 struct delayed_work ips_nic_off_wq;
2444 struct delayed_work c2hcmd_wq;
2445
2446 /* For SW LPS */
2447 struct delayed_work ps_work;
2448 struct delayed_work ps_rfon_wq;
2449 struct delayed_work fwevt_wq;
2450
2451 struct work_struct lps_change_work;
2452 struct work_struct fill_h2c_cmd;
2453 };
2454
2455 struct rtl_debug {
2456 /* add for debug */
2457 struct dentry *debugfs_dir;
2458 char debugfs_name[20];
2459
2460 char *msg_buf;
2461 };
2462
2463 #define MIMO_PS_STATIC 0
2464 #define MIMO_PS_DYNAMIC 1
2465 #define MIMO_PS_NOLIMIT 3
2466
2467 struct rtl_dualmac_easy_concurrent_ctl {
2468 enum band_type currentbandtype_backfordmdp;
2469 bool close_bbandrf_for_dmsp;
2470 bool change_to_dmdp;
2471 bool change_to_dmsp;
2472 bool switch_in_process;
2473 };
2474
2475 struct rtl_dmsp_ctl {
2476 bool activescan_for_slaveofdmsp;
2477 bool scan_for_anothermac_fordmsp;
2478 bool scan_for_itself_fordmsp;
2479 bool writedig_for_anothermacofdmsp;
2480 u32 curdigvalue_for_anothermacofdmsp;
2481 bool changecckpdstate_for_anothermacofdmsp;
2482 u8 curcckpdstate_for_anothermacofdmsp;
2483 bool changetxhighpowerlvl_for_anothermacofdmsp;
2484 u8 curtxhighlvl_for_anothermacofdmsp;
2485 long rssivalmin_for_anothermacofdmsp;
2486 };
2487
2488 struct ps_t {
2489 u8 pre_ccastate;
2490 u8 cur_ccasate;
2491 u8 pre_rfstate;
2492 u8 cur_rfstate;
2493 u8 initialize;
2494 long rssi_val_min;
2495 };
2496
2497 struct dig_t {
2498 u32 rssi_lowthresh;
2499 u32 rssi_highthresh;
2500 u32 fa_lowthresh;
2501 u32 fa_highthresh;
2502 long last_min_undec_pwdb_for_dm;
2503 long rssi_highpower_lowthresh;
2504 long rssi_highpower_highthresh;
2505 u32 recover_cnt;
2506 u32 pre_igvalue;
2507 u32 cur_igvalue;
2508 long rssi_val;
2509 u8 dig_enable_flag;
2510 u8 dig_ext_port_stage;
2511 u8 dig_algorithm;
2512 u8 dig_twoport_algorithm;
2513 u8 dig_dbgmode;
2514 u8 dig_slgorithm_switch;
2515 u8 cursta_cstate;
2516 u8 presta_cstate;
2517 u8 curmultista_cstate;
2518 u8 stop_dig;
2519 s8 back_val;
2520 s8 back_range_max;
2521 s8 back_range_min;
2522 u8 rx_gain_max;
2523 u8 rx_gain_min;
2524 u8 min_undec_pwdb_for_dm;
2525 u8 rssi_val_min;
2526 u8 pre_cck_cca_thres;
2527 u8 cur_cck_cca_thres;
2528 u8 pre_cck_pd_state;
2529 u8 cur_cck_pd_state;
2530 u8 pre_cck_fa_state;
2531 u8 cur_cck_fa_state;
2532 u8 pre_ccastate;
2533 u8 cur_ccasate;
2534 u8 large_fa_hit;
2535 u8 forbidden_igi;
2536 u8 dig_state;
2537 u8 dig_highpwrstate;
2538 u8 cur_sta_cstate;
2539 u8 pre_sta_cstate;
2540 u8 cur_ap_cstate;
2541 u8 pre_ap_cstate;
2542 u8 cur_pd_thstate;
2543 u8 pre_pd_thstate;
2544 u8 cur_cs_ratiostate;
2545 u8 pre_cs_ratiostate;
2546 u8 backoff_enable_flag;
2547 s8 backoffval_range_max;
2548 s8 backoffval_range_min;
2549 u8 dig_min_0;
2550 u8 dig_min_1;
2551 u8 bt30_cur_igi;
2552 bool media_connect_0;
2553 bool media_connect_1;
2554
2555 u32 antdiv_rssi_max;
2556 u32 rssi_max;
2557 };
2558
2559 struct rtl_global_var {
2560 /* from this list we can get
2561 * other adapter's rtl_priv
2562 */
2563 struct list_head glb_priv_list;
2564 spinlock_t glb_list_lock;
2565 };
2566
2567 #define IN_4WAY_TIMEOUT_TIME (30 * MSEC_PER_SEC) /* 30 seconds */
2568
2569 struct rtl_btc_info {
2570 u8 bt_type;
2571 u8 btcoexist;
2572 u8 ant_num;
2573 u8 single_ant_path;
2574
2575 u8 ap_num;
2576 bool in_4way;
2577 unsigned long in_4way_ts;
2578 };
2579
2580 struct bt_coexist_info {
2581 struct rtl_btc_ops *btc_ops;
2582 struct rtl_btc_info btc_info;
2583 /* btc context */
2584 void *btc_context;
2585 void *wifi_only_context;
2586 /* EEPROM BT info. */
2587 u8 eeprom_bt_coexist;
2588 u8 eeprom_bt_type;
2589 u8 eeprom_bt_ant_num;
2590 u8 eeprom_bt_ant_isol;
2591 u8 eeprom_bt_radio_shared;
2592
2593 u8 bt_coexistence;
2594 u8 bt_ant_num;
2595 u8 bt_coexist_type;
2596 u8 bt_state;
2597 u8 bt_cur_state; /* 0:on, 1:off */
2598 u8 bt_ant_isolation; /* 0:good, 1:bad */
2599 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2600 u8 bt_service;
2601 u8 bt_radio_shared_type;
2602 u8 bt_rfreg_origin_1e;
2603 u8 bt_rfreg_origin_1f;
2604 u8 bt_rssi_state;
2605 u32 ratio_tx;
2606 u32 ratio_pri;
2607 u32 bt_edca_ul;
2608 u32 bt_edca_dl;
2609
2610 bool init_set;
2611 bool bt_busy_traffic;
2612 bool bt_traffic_mode_set;
2613 bool bt_non_traffic_mode_set;
2614
2615 bool fw_coexist_all_off;
2616 bool sw_coexist_all_off;
2617 bool hw_coexist_all_off;
2618 u32 cstate;
2619 u32 previous_state;
2620 u32 cstate_h;
2621 u32 previous_state_h;
2622
2623 u8 bt_pre_rssi_state;
2624 u8 bt_pre_rssi_state1;
2625
2626 u8 reg_bt_iso;
2627 u8 reg_bt_sco;
2628 bool balance_on;
2629 u8 bt_active_zero_cnt;
2630 bool cur_bt_disabled;
2631 bool pre_bt_disabled;
2632
2633 u8 bt_profile_case;
2634 u8 bt_profile_action;
2635 bool bt_busy;
2636 bool hold_for_bt_operation;
2637 u8 lps_counter;
2638 };
2639
2640 struct rtl_btc_ops {
2641 void (*btc_init_variables)(struct rtl_priv *rtlpriv);
2642 void (*btc_init_variables_wifi_only)(struct rtl_priv *rtlpriv);
2643 void (*btc_deinit_variables)(struct rtl_priv *rtlpriv);
2644 void (*btc_init_hal_vars)(struct rtl_priv *rtlpriv);
2645 void (*btc_power_on_setting)(struct rtl_priv *rtlpriv);
2646 void (*btc_init_hw_config)(struct rtl_priv *rtlpriv);
2647 void (*btc_init_hw_config_wifi_only)(struct rtl_priv *rtlpriv);
2648 void (*btc_ips_notify)(struct rtl_priv *rtlpriv, u8 type);
2649 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2650 void (*btc_scan_notify)(struct rtl_priv *rtlpriv, u8 scantype);
2651 void (*btc_scan_notify_wifi_only)(struct rtl_priv *rtlpriv,
2652 u8 scantype);
2653 void (*btc_connect_notify)(struct rtl_priv *rtlpriv, u8 action);
2654 void (*btc_mediastatus_notify)(struct rtl_priv *rtlpriv,
2655 enum rt_media_status mstatus);
2656 void (*btc_periodical)(struct rtl_priv *rtlpriv);
2657 void (*btc_halt_notify)(struct rtl_priv *rtlpriv);
2658 void (*btc_btinfo_notify)(struct rtl_priv *rtlpriv,
2659 u8 *tmp_buf, u8 length);
2660 void (*btc_btmpinfo_notify)(struct rtl_priv *rtlpriv,
2661 u8 *tmp_buf, u8 length);
2662 bool (*btc_is_limited_dig)(struct rtl_priv *rtlpriv);
2663 bool (*btc_is_disable_edca_turbo)(struct rtl_priv *rtlpriv);
2664 bool (*btc_is_bt_disabled)(struct rtl_priv *rtlpriv);
2665 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2666 u8 pkt_type);
2667 void (*btc_switch_band_notify)(struct rtl_priv *rtlpriv, u8 type,
2668 bool scanning);
2669 void (*btc_switch_band_notify_wifi_only)(struct rtl_priv *rtlpriv,
2670 u8 type, bool scanning);
2671 void (*btc_display_bt_coex_info)(struct rtl_priv *rtlpriv,
2672 struct seq_file *m);
2673 void (*btc_record_pwr_mode)(struct rtl_priv *rtlpriv, u8 *buf, u8 len);
2674 u8 (*btc_get_lps_val)(struct rtl_priv *rtlpriv);
2675 u8 (*btc_get_rpwm_val)(struct rtl_priv *rtlpriv);
2676 bool (*btc_is_bt_ctrl_lps)(struct rtl_priv *rtlpriv);
2677 void (*btc_get_ampdu_cfg)(struct rtl_priv *rtlpriv, u8 *reject_agg,
2678 u8 *ctrl_agg_size, u8 *agg_size);
2679 bool (*btc_is_bt_lps_on)(struct rtl_priv *rtlpriv);
2680 };
2681
2682 struct rtl_halmac_ops {
2683 int (*halmac_init_adapter)(struct rtl_priv *rtlpriv);
2684 int (*halmac_deinit_adapter)(struct rtl_priv *rtlpriv);
2685 int (*halmac_init_hal)(struct rtl_priv *rtlpriv);
2686 int (*halmac_deinit_hal)(struct rtl_priv *rtlpriv);
2687 int (*halmac_poweron)(struct rtl_priv *rtlpriv);
2688 int (*halmac_poweroff)(struct rtl_priv *rtlpriv);
2689
2690 int (*halmac_phy_power_switch)(struct rtl_priv *rtlpriv, u8 enable);
2691 int (*halmac_set_mac_address)(struct rtl_priv *rtlpriv, u8 hwport,
2692 u8 *addr);
2693 int (*halmac_set_bssid)(struct rtl_priv *rtlpriv, u8 hwport, u8 *addr);
2694
2695 int (*halmac_get_physical_efuse_size)(struct rtl_priv *rtlpriv,
2696 u32 *size);
2697 int (*halmac_read_physical_efuse_map)(struct rtl_priv *rtlpriv,
2698 u8 *map, u32 size);
2699 int (*halmac_get_logical_efuse_size)(struct rtl_priv *rtlpriv,
2700 u32 *size);
2701 int (*halmac_read_logical_efuse_map)(struct rtl_priv *rtlpriv, u8 *map,
2702 u32 size);
2703
2704 int (*halmac_set_bandwidth)(struct rtl_priv *rtlpriv, u8 channel,
2705 u8 pri_ch_idx, u8 bw);
2706
2707 int (*halmac_c2h_handle)(struct rtl_priv *rtlpriv, u8 *c2h, u32 size);
2708
2709 int (*halmac_chk_txdesc)(struct rtl_priv *rtlpriv, u8 *txdesc,
2710 u32 size);
2711 };
2712
2713 struct rtl_halmac_indicator {
2714 struct completion *comp;
2715 u32 wait_ms;
2716
2717 u8 *buffer;
2718 u32 buf_size;
2719 u32 ret_size;
2720 u32 status;
2721 };
2722
2723 struct rtl_halmac {
2724 struct rtl_halmac_ops *ops; /* halmac ops (halmac.ko own this object) */
2725 void *internal; /* internal context of halmac, i.e. PHALMAC_ADAPTER */
2726 struct rtl_halmac_indicator *indicator; /* size=10 */
2727
2728 /* flags */
2729 /*
2730 * send_general_info
2731 * 0: no need to call halmac_send_general_info()
2732 * 1: need to call halmac_send_general_info()
2733 */
2734 u8 send_general_info;
2735 };
2736
2737 struct rtl_phydm_params {
2738 u8 mp_chip; /* 1: MP chip, 0: test chip */
2739 u8 fab_ver; /* 0: TSMC, 1: UMC, ...*/
2740 u8 cut_ver; /* 0: A, 1: B, ..., 10: K */
2741 u8 efuse0x3d7; /* default: 0xff */
2742 u8 efuse0x3d8; /* default: 0xff */
2743 };
2744
2745 struct rtl_phydm_ops {
2746 /* init/deinit priv */
2747 int (*phydm_init_priv)(struct rtl_priv *rtlpriv,
2748 struct rtl_phydm_params *params);
2749 int (*phydm_deinit_priv)(struct rtl_priv *rtlpriv);
2750 bool (*phydm_load_txpower_by_rate)(struct rtl_priv *rtlpriv);
2751 bool (*phydm_load_txpower_limit)(struct rtl_priv *rtlpriv);
2752
2753 /* init hw */
2754 int (*phydm_init_dm)(struct rtl_priv *rtlpriv);
2755 int (*phydm_deinit_dm)(struct rtl_priv *rtlpriv);
2756 int (*phydm_reset_dm)(struct rtl_priv *rtlpriv);
2757 bool (*phydm_parameter_init)(struct rtl_priv *rtlpriv, bool post);
2758 bool (*phydm_phy_bb_config)(struct rtl_priv *rtlpriv);
2759 bool (*phydm_phy_rf_config)(struct rtl_priv *rtlpriv);
2760 bool (*phydm_phy_mac_config)(struct rtl_priv *rtlpriv);
2761 bool (*phydm_trx_mode)(struct rtl_priv *rtlpriv,
2762 enum radio_mask tx_path, enum radio_mask rx_path,
2763 bool is_tx2_path);
2764 /* watchdog */
2765 bool (*phydm_watchdog)(struct rtl_priv *rtlpriv);
2766
2767 /* channel */
2768 bool (*phydm_switch_band)(struct rtl_priv *rtlpriv, u8 central_ch);
2769 bool (*phydm_switch_channel)(struct rtl_priv *rtlpriv, u8 central_ch);
2770 bool (*phydm_switch_bandwidth)(struct rtl_priv *rtlpriv,
2771 u8 primary_ch_idx,
2772 enum ht_channel_width width);
2773 bool (*phydm_iq_calibrate)(struct rtl_priv *rtlpriv);
2774 bool (*phydm_clear_txpowertracking_state)(struct rtl_priv *rtlpriv);
2775 bool (*phydm_pause_dig)(struct rtl_priv *rtlpriv, bool pause);
2776
2777 /* read/write reg */
2778 u32 (*phydm_read_rf_reg)(struct rtl_priv *rtlpriv,
2779 enum radio_path rfpath,
2780 u32 addr, u32 mask);
2781 bool (*phydm_write_rf_reg)(struct rtl_priv *rtlpriv,
2782 enum radio_path rfpath,
2783 u32 addr, u32 mask, u32 data);
2784 u8 (*phydm_read_txagc)(struct rtl_priv *rtlpriv,
2785 enum radio_path rfpath, u8 hw_rate);
2786 bool (*phydm_write_txagc)(struct rtl_priv *rtlpriv, u32 power_index,
2787 enum radio_path rfpath, u8 hw_rate);
2788
2789 /* RX */
2790 bool (*phydm_c2h_content_parsing)(struct rtl_priv *rtlpriv, u8 cmd_id,
2791 u8 cmd_len, u8 *content);
2792 bool (*phydm_query_phy_status)(struct rtl_priv *rtlpriv, u8 *phystrpt,
2793 struct ieee80211_hdr *hdr,
2794 struct rtl_stats *pstatus);
2795
2796 /* TX */
2797 u8 (*phydm_rate_id_mapping)(struct rtl_priv *rtlpriv,
2798 enum wireless_mode wireless_mode,
2799 enum rf_type rf_type,
2800 enum ht_channel_width bw);
2801 bool (*phydm_get_ra_bitmap)(struct rtl_priv *rtlpriv,
2802 enum wireless_mode wireless_mode,
2803 enum rf_type rf_type,
2804 enum ht_channel_width bw,
2805 u8 tx_rate_level, /* 0~6 */
2806 u32 *tx_bitmap_msb,
2807 u32 *tx_bitmap_lsb);
2808
2809 /* STA */
2810 bool (*phydm_add_sta)(struct rtl_priv *rtlpriv,
2811 struct ieee80211_sta *sta);
2812 bool (*phydm_del_sta)(struct rtl_priv *rtlpriv,
2813 struct ieee80211_sta *sta);
2814
2815 /* BTC */
2816 u32 (*phydm_get_version)(struct rtl_priv *rtlpriv);
2817 bool (*phydm_modify_ra_pcr_threshold)(struct rtl_priv *rtlpriv,
2818 u8 ra_offset_direction,
2819 u8 ra_threshold_offset);
2820 u32 (*phydm_query_counter)(struct rtl_priv *rtlpriv,
2821 const char *info_type);
2822
2823 /* debug */
2824 bool (*phydm_debug_cmd)(struct rtl_priv *rtlpriv, char *in, u32 in_len,
2825 char *out, u32 out_len);
2826
2827 };
2828
2829 struct rtl_phydm {
2830 struct rtl_phydm_ops *ops;/* phydm ops (phydm_mod.ko own this object) */
2831 void *internal; /* internal context of phydm, i.e. PHY_DM_STRUCT */
2832
2833 u8 adaptivity_en;
2834 /* debug */
2835 u16 forced_data_rate;
2836 u8 forced_igi_lb;
2837 u8 antenna_test;
2838 };
2839
2840 struct proxim {
2841 bool proxim_on;
2842
2843 void *proximity_priv;
2844 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2845 struct sk_buff *skb);
2846 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2847 };
2848
2849 struct rtl_c2hcmd {
2850 struct list_head list;
2851 u8 tag;
2852 u8 len;
2853 u8 *val;
2854 };
2855
2856 struct rtl_bssid_entry {
2857 struct list_head list;
2858 u8 bssid[ETH_ALEN];
2859 u32 age;
2860 };
2861
2862 struct rtl_scan_list {
2863 int num;
2864 struct list_head list; /* sort by age */
2865 };
2866
2867 struct rtl_priv {
2868 struct ieee80211_hw *hw;
2869 struct completion firmware_loading_complete;
2870 struct list_head list;
2871 struct rtl_priv *buddy_priv;
2872 struct rtl_global_var *glb_var;
2873 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2874 struct rtl_dmsp_ctl dmsp_ctl;
2875 struct rtl_locks locks;
2876 struct rtl_works works;
2877 struct rtl_mac mac80211;
2878 struct rtl_hal rtlhal;
2879 struct rtl_regulatory regd;
2880 struct rtl_rfkill rfkill;
2881 struct rtl_io io;
2882 struct rtl_phy phy;
2883 struct rtl_dm dm;
2884 struct rtl_security sec;
2885 struct rtl_efuse efuse;
2886 struct rtl_led_ctl ledctl;
2887 struct rtl_tx_report tx_report;
2888 struct rtl_scan_list scan_list;
2889 struct rtl_ps_ctl psc;
2890 struct rate_adaptive ra;
2891 struct dynamic_primary_cca primarycca;
2892 struct wireless_stats stats;
2893 struct rt_link_detect link_info;
2894 struct false_alarm_statistics falsealm_cnt;
2895 struct rtl_rate_priv *rate_priv;
2896 /* sta entry list for ap adhoc or mesh */
2897 struct list_head entry_list;
2898 /* c2hcmd list for kthread level access */
2899 struct list_head c2hcmd_list;
2900 struct rtl_debug dbg;
2901 int max_fw_size;
2902
2903 /*hal_cfg : for diff cards
2904 *intf_ops : for diff interface usb/pcie
2905 */
2906 struct rtl_hal_cfg *cfg;
2907 const struct rtl_intf_ops *intf_ops;
2908
2909 /* this var will be set by set_bit,
2910 * and was used to indicate status of
2911 * interface or hardware
2912 */
2913 unsigned long status;
2914
2915 /* tables for dm */
2916 struct dig_t dm_digtable;
2917 struct ps_t dm_pstable;
2918
2919 u32 reg_874;
2920 u32 reg_c70;
2921 u32 reg_85c;
2922 u32 reg_a74;
2923 bool reg_init; /* true if regs saved */
2924 bool bt_operation_on;
2925 __le32 *usb_data;
2926 int usb_data_index;
2927 bool initialized;
2928 bool enter_ps; /* true when entering PS */
2929 u8 rate_mask[5];
2930
2931 /* intel Proximity, should be alloc mem
2932 * in intel Proximity module and can only
2933 * be used in intel Proximity mode
2934 */
2935 struct proxim proximity;
2936
2937 /*for bt coexist use*/
2938 struct bt_coexist_info btcoexist;
2939
2940 /* halmac for newer IC. (e.g. 8822B) */
2941 struct rtl_halmac halmac;
2942
2943 /* phydm for newer IC. (e.g. 8822B) */
2944 struct rtl_phydm phydm;
2945
2946 /* separate 92ee from other ICs,
2947 * 92ee use new trx flow.
2948 */
2949 bool use_new_trx_flow;
2950
2951 #ifdef CONFIG_PM
2952 struct wiphy_wowlan_support wowlan;
2953 #endif
2954 /* This must be the last item so
2955 * that it points to the data allocated
2956 * beyond this structure like:
2957 * rtl_pci_priv or rtl_usb_priv
2958 */
2959 u8 priv[0] __aligned(sizeof(void *));
2960 };
2961
2962 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2963 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2964 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2965 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2966 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2967
2968 /***************************************
2969 * Bluetooth Co-existence Related
2970 ***************************************/
2971
2972 enum bt_ant_num {
2973 ANT_X2 = 0,
2974 ANT_X1 = 1,
2975 };
2976
2977 enum bt_co_type {
2978 BT_2WIRE = 0,
2979 BT_ISSC_3WIRE = 1,
2980 BT_ACCEL = 2,
2981 BT_CSR_BC4 = 3,
2982 BT_CSR_BC8 = 4,
2983 BT_RTL8756 = 5,
2984 BT_RTL8723A = 6,
2985 BT_RTL8821A = 7,
2986 BT_RTL8723B = 8,
2987 BT_RTL8192E = 9,
2988 BT_RTL8812A = 11,
2989 BT_RTL8822B = 12,
2990 };
2991
2992 enum bt_total_ant_num {
2993 ANT_TOTAL_X2 = 0,
2994 ANT_TOTAL_X1 = 1
2995 };
2996
2997 enum bt_cur_state {
2998 BT_OFF = 0,
2999 BT_ON = 1,
3000 };
3001
3002 enum bt_service_type {
3003 BT_SCO = 0,
3004 BT_A2DP = 1,
3005 BT_HID = 2,
3006 BT_HID_IDLE = 3,
3007 BT_SCAN = 4,
3008 BT_IDLE = 5,
3009 BT_OTHER_ACTION = 6,
3010 BT_BUSY = 7,
3011 BT_OTHERBUSY = 8,
3012 BT_PAN = 9,
3013 };
3014
3015 enum bt_radio_shared {
3016 BT_RADIO_SHARED = 0,
3017 BT_RADIO_INDIVIDUAL = 1,
3018 };
3019
3020 /****************************************
3021 * mem access macro define start
3022 * Call endian free function when
3023 * 1. Read/write packet content.
3024 * 2. Before write integer to IO.
3025 * 3. After read integer from IO.
3026 ***************************************/
3027 /* Convert little data endian to host ordering */
3028 #define EF1BYTE(_val) \
3029 ((u8)(_val))
3030 #define EF2BYTE(_val) \
3031 (le16_to_cpu(_val))
3032 #define EF4BYTE(_val) \
3033 (le32_to_cpu(_val))
3034
3035 /* Read data from memory */
3036 #define READEF1BYTE(_ptr) \
3037 EF1BYTE(*((u8 *)(_ptr)))
3038 /* Read le16 data from memory and convert to host ordering */
3039 #define READEF2BYTE(_ptr) \
3040 EF2BYTE(*(_ptr))
3041 #define READEF4BYTE(_ptr) \
3042 EF4BYTE(*(_ptr))
3043
3044 /* Create a bit mask
3045 * Examples:
3046 * BIT_LEN_MASK_32(0) => 0x00000000
3047 * BIT_LEN_MASK_32(1) => 0x00000001
3048 * BIT_LEN_MASK_32(2) => 0x00000003
3049 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
3050 */
3051 #define BIT_LEN_MASK_32(__bitlen) \
3052 (0xFFFFFFFF >> (32 - (__bitlen)))
3053 #define BIT_LEN_MASK_16(__bitlen) \
3054 (0xFFFF >> (16 - (__bitlen)))
3055 #define BIT_LEN_MASK_8(__bitlen) \
3056 (0xFF >> (8 - (__bitlen)))
3057
3058 /* Create an offset bit mask
3059 * Examples:
3060 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
3061 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
3062 */
3063 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
3064 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
3065 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
3066 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
3067 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
3068 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
3069
3070 /*Description:
3071 * Return 4-byte value in host byte ordering from
3072 * 4-byte pointer in little-endian system.
3073 */
3074 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
3075 (EF4BYTE(*((__le32 *)(__pstart))))
3076 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
3077 (EF2BYTE(*((__le16 *)(__pstart))))
3078 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
3079 (EF1BYTE(*((u8 *)(__pstart))))
3080
3081 /* Description:
3082 * Translate subfield (continuous bits in little-endian) of 4-byte
3083 * value to host byte ordering.
3084 */
3085 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
3086 ( \
3087 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
3088 BIT_LEN_MASK_32(__bitlen) \
3089 )
3090 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
3091 ( \
3092 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
3093 BIT_LEN_MASK_16(__bitlen) \
3094 )
3095 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
3096 ( \
3097 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
3098 BIT_LEN_MASK_8(__bitlen) \
3099 )
3100
3101 /* Description:
3102 * Mask subfield (continuous bits in little-endian) of 4-byte value
3103 * and return the result in 4-byte value in host byte ordering.
3104 */
3105 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
3106 ( \
3107 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
3108 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
3109 )
3110 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
3111 ( \
3112 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
3113 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
3114 )
3115 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
3116 ( \
3117 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
3118 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
3119 )
3120
3121 /* Description:
3122 * Set subfield of little-endian 4-byte value to specified value.
3123 */
3124 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
3125 (*((__le32 *)(__pstart)) = \
3126 cpu_to_le32( \
3127 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
3128 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
3129 ))
3130 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
3131 (*((__le16 *)(__pstart)) = \
3132 cpu_to_le16( \
3133 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
3134 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
3135 ))
3136 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
3137 (*((u8 *)(__pstart)) = EF1BYTE \
3138 ( \
3139 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
3140 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
3141 ))
3142
3143 #define N_BYTE_ALIGNMENT(__value, __alignment) ((__alignment == 1) ? \
3144 (__value) : (((__value + __alignment - 1) / \
3145 __alignment) * __alignment))
3146
3147 /****************************************
3148 * mem access macro define end
3149 ****************************************/
3150
3151 #define byte(x, n) ((x >> (8 * n)) & 0xff)
3152
3153 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
3154 #define RTL_WATCH_DOG_TIME 2000
3155 #define MSECS(t) msecs_to_jiffies(t)
3156 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
3157 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
3158 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
3159 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
3160 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
3161
3162 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
3163 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
3164 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
3165 /*NIC halt, re-initialize hw parameters*/
3166 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
3167 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
3168 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
3169 /*Always enable ASPM and Clock Req in initialization.*/
3170 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
3171 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
3172 #define RT_PS_LEVEL_ASPM BIT(7)
3173 /*When LPS is on, disable 2R if no packet is received or transmitted.*/
3174 #define RT_RF_LPS_DISALBE_2R BIT(30)
3175 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
3176 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
3177 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
3178 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
3179 (ppsc->cur_ps_level &= (~(_ps_flg)))
3180 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
3181 (ppsc->cur_ps_level |= _ps_flg)
3182
3183 #define container_of_dwork_rtl(x, y, z) \
3184 container_of(to_delayed_work(x), y, z)
3185
3186 #define FILL_OCTET_STRING(_os, _octet, _len) \
3187 (_os).octet = (u8 *)(_octet); \
3188 (_os).length = (_len)
3189
3190 #define CP_MACADDR(des, src) \
3191 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
3192 (des)[2] = (src)[2], (des)[3] = (src)[3],\
3193 (des)[4] = (src)[4], (des)[5] = (src)[5])
3194
3195 #define LDPC_HT_ENABLE_RX BIT(0)
3196 #define LDPC_HT_ENABLE_TX BIT(1)
3197 #define LDPC_HT_TEST_TX_ENABLE BIT(2)
3198 #define LDPC_HT_CAP_TX BIT(3)
3199
3200 #define STBC_HT_ENABLE_RX BIT(0)
3201 #define STBC_HT_ENABLE_TX BIT(1)
3202 #define STBC_HT_TEST_TX_ENABLE BIT(2)
3203 #define STBC_HT_CAP_TX BIT(3)
3204
3205 #define LDPC_VHT_ENABLE_RX BIT(0)
3206 #define LDPC_VHT_ENABLE_TX BIT(1)
3207 #define LDPC_VHT_TEST_TX_ENABLE BIT(2)
3208 #define LDPC_VHT_CAP_TX BIT(3)
3209
3210 #define STBC_VHT_ENABLE_RX BIT(0)
3211 #define STBC_VHT_ENABLE_TX BIT(1)
3212 #define STBC_VHT_TEST_TX_ENABLE BIT(2)
3213 #define STBC_VHT_CAP_TX BIT(3)
3214
3215 extern u8 channel5g[CHANNEL_MAX_NUMBER_5G];
3216
3217 extern u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M];
3218
3219 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
3220 {
3221 return rtlpriv->io.read8_sync(rtlpriv, addr);
3222 }
3223
3224 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
3225 {
3226 return rtlpriv->io.read16_sync(rtlpriv, addr);
3227 }
3228
3229 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
3230 {
3231 return rtlpriv->io.read32_sync(rtlpriv, addr);
3232 }
3233
3234 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
3235 {
3236 rtlpriv->io.write8_async(rtlpriv, addr, val8);
3237
3238 if (rtlpriv->cfg->write_readback)
3239 rtlpriv->io.read8_sync(rtlpriv, addr);
3240 }
3241
3242 static inline void rtl_write_byte_with_val32(struct ieee80211_hw *hw,
3243 u32 addr, u32 val8)
3244 {
3245 struct rtl_priv *rtlpriv = rtl_priv(hw);
3246
3247 rtl_write_byte(rtlpriv, addr, (u8)val8);
3248 }
3249
3250 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
3251 {
3252 rtlpriv->io.write16_async(rtlpriv, addr, val16);
3253
3254 if (rtlpriv->cfg->write_readback)
3255 rtlpriv->io.read16_sync(rtlpriv, addr);
3256 }
3257
3258 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
3259 u32 addr, u32 val32)
3260 {
3261 rtlpriv->io.write32_async(rtlpriv, addr, val32);
3262
3263 if (rtlpriv->cfg->write_readback)
3264 rtlpriv->io.read32_sync(rtlpriv, addr);
3265 }
3266
3267 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
3268 u32 regaddr, u32 bitmask)
3269 {
3270 struct rtl_priv *rtlpriv = hw->priv;
3271
3272 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
3273 }
3274
3275 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
3276 u32 bitmask, u32 data)
3277 {
3278 struct rtl_priv *rtlpriv = hw->priv;
3279
3280 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
3281 }
3282
3283 static inline void rtl_set_bbreg_with_dwmask(struct ieee80211_hw *hw,
3284 u32 regaddr, u32 data)
3285 {
3286 rtl_set_bbreg(hw, regaddr, 0xffffffff, data);
3287 }
3288
3289 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
3290 enum radio_path rfpath, u32 regaddr,
3291 u32 bitmask)
3292 {
3293 struct rtl_priv *rtlpriv = hw->priv;
3294
3295 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
3296 }
3297
3298 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
3299 enum radio_path rfpath, u32 regaddr,
3300 u32 bitmask, u32 data)
3301 {
3302 struct rtl_priv *rtlpriv = hw->priv;
3303
3304 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
3305 }
3306
3307 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
3308 {
3309 return (rtlhal->state == _HAL_STATE_STOP);
3310 }
3311
3312 static inline void set_hal_start(struct rtl_hal *rtlhal)
3313 {
3314 rtlhal->state = _HAL_STATE_START;
3315 }
3316
3317 static inline void set_hal_stop(struct rtl_hal *rtlhal)
3318 {
3319 rtlhal->state = _HAL_STATE_STOP;
3320 }
3321
3322 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
3323 {
3324 return rtlphy->rf_type;
3325 }
3326
3327 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
3328 {
3329 return (struct ieee80211_hdr *)(skb->data);
3330 }
3331
3332 static inline __le16 rtl_get_fc(struct sk_buff *skb)
3333 {
3334 return rtl_get_hdr(skb)->frame_control;
3335 }
3336
3337 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
3338 {
3339 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
3340 }
3341
3342 static inline u16 rtl_get_tid(struct sk_buff *skb)
3343 {
3344 return rtl_get_tid_h(rtl_get_hdr(skb));
3345 }
3346
3347 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
3348 struct ieee80211_vif *vif,
3349 const u8 *bssid)
3350 {
3351 return ieee80211_find_sta(vif, bssid);
3352 }
3353
3354 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
3355 u8 *mac_addr)
3356 {
3357 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3358
3359 return ieee80211_find_sta(mac->vif, mac_addr);
3360 }
3361
3362 #endif
Linux with added FPC-III support