2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
8 * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
9 * Copyright 1999 Hewlett Packard Co.
14 #include <linux/ptrace.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/interrupt.h>
18 #include <linux/extable.h>
19 #include <linux/uaccess.h>
20 #include <linux/hugetlb.h>
21 #include <linux/perf_event.h>
23 #include <asm/traps.h>
25 /* Various important other fields */
26 #define bit22set(x) (x & 0x00000200)
27 #define bits23_25set(x) (x & 0x000001c0)
28 #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
29 /* extended opcode is 0x6a */
31 #define BITSSET 0x1c0 /* for identifying LDCW */
34 int show_unhandled_signals
= 1;
37 * parisc_acctyp(unsigned int inst) --
38 * Given a PA-RISC memory access instruction, determine if the
39 * the instruction would perform a memory read or memory write
42 * This function assumes that the given instruction is a memory access
43 * instruction (i.e. you should really only call it if you know that
44 * the instruction has generated some sort of a memory access fault).
47 * VM_READ if read operation
48 * VM_WRITE if write operation
49 * VM_EXEC if execute operation
52 parisc_acctyp(unsigned long code
, unsigned int inst
)
54 if (code
== 6 || code
== 16)
57 switch (inst
& 0xf0000000) {
58 case 0x40000000: /* load */
59 case 0x50000000: /* new load */
62 case 0x60000000: /* store */
63 case 0x70000000: /* new store */
66 case 0x20000000: /* coproc */
67 case 0x30000000: /* coproc2 */
72 case 0x0: /* indexed/memory management */
75 * Check for the 'Graphics Flush Read' instruction.
76 * It resembles an FDC instruction, except for bits
77 * 20 and 21. Any combination other than zero will
78 * utilize the block mover functionality on some
79 * older PA-RISC platforms. The case where a block
80 * move is performed from VM to graphics IO space
81 * should be treated as a READ.
83 * The significance of bits 20,21 in the FDC
86 * 00 Flush data cache (normal instruction behavior)
87 * 01 Graphics flush write (IO space -> VM)
88 * 10 Graphics flush read (VM -> IO space)
89 * 11 Graphics flush read/write (VM <-> IO space)
91 if (isGraphicsFlushRead(inst
))
96 * Check for LDCWX and LDCWS (semaphore instructions).
97 * If bits 23 through 25 are all 1's it is one of
98 * the above two instructions and is a write.
100 * Note: With the limited bits we are looking at,
101 * this will also catch PROBEW and PROBEWI. However,
102 * these should never get in here because they don't
103 * generate exceptions of the type:
104 * Data TLB miss fault/data page fault
105 * Data memory protection trap
107 if (bits23_25set(inst
) == BITSSET
)
110 return VM_READ
; /* Default */
112 return VM_READ
; /* Default */
117 #undef isGraphicsFlushRead
122 /* This is the treewalk to find a vma which is the highest that has
123 * a start < addr. We're using find_vma_prev instead right now, but
124 * we might want to use this at some point in the future. Probably
125 * not, but I want it committed to CVS so I don't lose it :-)
127 while (tree
!= vm_avl_empty
) {
128 if (tree
->vm_start
> addr
) {
129 tree
= tree
->vm_avl_left
;
132 if (prev
->vm_next
== NULL
)
134 if (prev
->vm_next
->vm_start
> addr
)
136 tree
= tree
->vm_avl_right
;
141 int fixup_exception(struct pt_regs
*regs
)
143 const struct exception_table_entry
*fix
;
145 fix
= search_exception_tables(regs
->iaoq
[0]);
148 * Fix up get_user() and put_user().
149 * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
150 * bit in the relative address of the fixup routine to indicate
151 * that %r8 should be loaded with -EFAULT to report a userspace
154 if (fix
->fixup
& 1) {
155 regs
->gr
[8] = -EFAULT
;
157 /* zero target register for get_user() */
158 if (parisc_acctyp(0, regs
->iir
) == VM_READ
) {
159 int treg
= regs
->iir
& 0x1f;
165 regs
->iaoq
[0] = (unsigned long)&fix
->fixup
+ fix
->fixup
;
168 * NOTE: In some cases the faulting instruction
169 * may be in the delay slot of a branch. We
170 * don't want to take the branch, so we don't
171 * increment iaoq[1], instead we set it to be
172 * iaoq[0]+4, and clear the B bit in the PSW
174 regs
->iaoq
[1] = regs
->iaoq
[0] + 4;
175 regs
->gr
[0] &= ~PSW_B
; /* IPSW in gr[0] */
184 * parisc hardware trap list
186 * Documented in section 3 "Addressing and Access Control" of the
187 * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
188 * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
190 * For implementation see handle_interruption() in traps.c
192 static const char * const trap_description
[] = {
193 [1] "High-priority machine check (HPMC)",
194 [2] "Power failure interrupt",
195 [3] "Recovery counter trap",
196 [5] "Low-priority machine check",
197 [6] "Instruction TLB miss fault",
198 [7] "Instruction access rights / protection trap",
199 [8] "Illegal instruction trap",
200 [9] "Break instruction trap",
201 [10] "Privileged operation trap",
202 [11] "Privileged register trap",
203 [12] "Overflow trap",
204 [13] "Conditional trap",
205 [14] "FP Assist Exception trap",
206 [15] "Data TLB miss fault",
207 [16] "Non-access ITLB miss fault",
208 [17] "Non-access DTLB miss fault",
209 [18] "Data memory protection/unaligned access trap",
210 [19] "Data memory break trap",
211 [20] "TLB dirty bit trap",
212 [21] "Page reference trap",
213 [22] "Assist emulation trap",
214 [25] "Taken branch trap",
215 [26] "Data memory access rights trap",
216 [27] "Data memory protection ID trap",
217 [28] "Unaligned data reference trap",
220 const char *trap_name(unsigned long code
)
222 const char *t
= NULL
;
224 if (code
< ARRAY_SIZE(trap_description
))
225 t
= trap_description
[code
];
227 return t
? t
: "Unknown trap";
231 * Print out info about fatal segfaults, if the show_unhandled_signals
235 show_signal_msg(struct pt_regs
*regs
, unsigned long code
,
236 unsigned long address
, struct task_struct
*tsk
,
237 struct vm_area_struct
*vma
)
239 if (!unhandled_signal(tsk
, SIGSEGV
))
242 if (!printk_ratelimit())
246 pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
247 tsk
->comm
, code
, address
);
248 print_vma_addr(KERN_CONT
" in ", regs
->iaoq
[0]);
250 pr_cont("\ntrap #%lu: %s%c", code
, trap_name(code
),
254 pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
255 vma
->vm_start
, vma
->vm_end
);
260 void do_page_fault(struct pt_regs
*regs
, unsigned long code
,
261 unsigned long address
)
263 struct vm_area_struct
*vma
, *prev_vma
;
264 struct task_struct
*tsk
;
265 struct mm_struct
*mm
;
266 unsigned long acc_type
;
267 vm_fault_t fault
= 0;
270 if (faulthandler_disabled())
278 flags
= FAULT_FLAG_DEFAULT
;
280 flags
|= FAULT_FLAG_USER
;
282 acc_type
= parisc_acctyp(code
, regs
->iir
);
283 if (acc_type
& VM_WRITE
)
284 flags
|= FAULT_FLAG_WRITE
;
285 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS
, 1, regs
, address
);
288 vma
= find_vma_prev(mm
, address
, &prev_vma
);
289 if (!vma
|| address
< vma
->vm_start
)
290 goto check_expansion
;
292 * Ok, we have a good vm_area for this memory access. We still need to
293 * check the access permissions.
298 if ((vma
->vm_flags
& acc_type
) != acc_type
)
302 * If for any reason at all we couldn't handle the fault, make
303 * sure we exit gracefully rather than endlessly redo the
307 fault
= handle_mm_fault(vma
, address
, flags
, regs
);
309 if (fault_signal_pending(fault
, regs
))
312 if (unlikely(fault
& VM_FAULT_ERROR
)) {
314 * We hit a shared mapping outside of the file, or some
315 * other thing happened to us that made us unable to
316 * handle the page fault gracefully.
318 if (fault
& VM_FAULT_OOM
)
320 else if (fault
& VM_FAULT_SIGSEGV
)
322 else if (fault
& (VM_FAULT_SIGBUS
|VM_FAULT_HWPOISON
|
323 VM_FAULT_HWPOISON_LARGE
))
327 if (flags
& FAULT_FLAG_ALLOW_RETRY
) {
328 if (fault
& VM_FAULT_RETRY
) {
330 * No need to mmap_read_unlock(mm) as we would
331 * have already released it in __lock_page_or_retry
334 flags
|= FAULT_FLAG_TRIED
;
338 mmap_read_unlock(mm
);
343 if (vma
&& (expand_stack(vma
, address
) == 0))
347 * Something tried to access memory that isn't in our memory map..
350 mmap_read_unlock(mm
);
352 if (user_mode(regs
)) {
356 case 15: /* Data TLB miss fault/Data page fault */
357 /* send SIGSEGV when outside of vma */
359 address
< vma
->vm_start
|| address
>= vma
->vm_end
) {
361 si_code
= SEGV_MAPERR
;
365 /* send SIGSEGV for wrong permissions */
366 if ((vma
->vm_flags
& acc_type
) != acc_type
) {
368 si_code
= SEGV_ACCERR
;
372 /* probably address is outside of mapped file */
374 case 17: /* NA data TLB miss / page fault */
375 case 18: /* Unaligned access - PCXS only */
377 si_code
= (code
== 18) ? BUS_ADRALN
: BUS_ADRERR
;
379 case 16: /* Non-access instruction TLB miss fault */
380 case 26: /* PCXL: Data memory access rights trap */
383 si_code
= (code
== 26) ? SEGV_ACCERR
: SEGV_MAPERR
;
386 #ifdef CONFIG_MEMORY_FAILURE
387 if (fault
& (VM_FAULT_HWPOISON
|VM_FAULT_HWPOISON_LARGE
)) {
388 unsigned int lsb
= 0;
390 "MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
391 tsk
->comm
, tsk
->pid
, address
);
393 * Either small page or large page may be poisoned.
394 * In other words, VM_FAULT_HWPOISON_LARGE and
395 * VM_FAULT_HWPOISON are mutually exclusive.
397 if (fault
& VM_FAULT_HWPOISON_LARGE
)
398 lsb
= hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault
));
399 else if (fault
& VM_FAULT_HWPOISON
)
402 force_sig_mceerr(BUS_MCEERR_AR
, (void __user
*) address
,
407 show_signal_msg(regs
, code
, address
, tsk
, vma
);
409 force_sig_fault(signo
, si_code
, (void __user
*) address
);
415 if (!user_mode(regs
) && fixup_exception(regs
)) {
419 parisc_terminate("Bad Address (null pointer deref?)", regs
, code
, address
);
422 mmap_read_unlock(mm
);
423 if (!user_mode(regs
))
425 pagefault_out_of_memory();