drivers/clk/at91/at91sam9g45.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/clk-provider.h>
   3 #include <linux/mfd/syscon.h>
   4 #include <linux/slab.h>
   5
   6 #include <dt-bindings/clock/at91.h>
   7
   8 #include "pmc.h"
   9
  10 static DEFINE_SPINLOCK(at91sam9g45_mck_lock);
  11
  12 static const struct clk_master_characteristics mck_characteristics = {
  13         .output = { .min = 0, .max = 133333333 },
  14         .divisors = { 1, 2, 4, 3 },
  15 };
  16
  17 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
  18
  19 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
  20
  21 static const struct clk_range plla_outputs[] = {
  22         { .min = 745000000, .max = 800000000 },
  23         { .min = 695000000, .max = 750000000 },
  24         { .min = 645000000, .max = 700000000 },
  25         { .min = 595000000, .max = 650000000 },
  26         { .min = 545000000, .max = 600000000 },
  27         { .min = 495000000, .max = 555000000 },
  28         { .min = 445000000, .max = 500000000 },
  29         { .min = 400000000, .max = 450000000 },
  30 };
  31
  32 static const struct clk_pll_characteristics plla_characteristics = {
  33         .input = { .min = 2000000, .max = 32000000 },
  34         .num_output = ARRAY_SIZE(plla_outputs),
  35         .output = plla_outputs,
  36         .icpll = plla_icpll,
  37         .out = plla_out,
  38 };
  39
  40 static const struct {
  41         char *n;
  42         char *p;
  43         u8 id;
  44 } at91sam9g45_systemck[] = {
  45         { .n = "ddrck", .p = "masterck_div", .id = 2 },
  46         { .n = "uhpck", .p = "usbck",        .id = 6 },
  47         { .n = "pck0",  .p = "prog0",        .id = 8 },
  48         { .n = "pck1",  .p = "prog1",        .id = 9 },
  49 };
  50
  51 struct pck {
  52         char *n;
  53         u8 id;
  54 };
  55
  56 static const struct pck at91sam9g45_periphck[] = {
  57         { .n = "pioA_clk",       .id = 2, },
  58         { .n = "pioB_clk",       .id = 3, },
  59         { .n = "pioC_clk",       .id = 4, },
  60         { .n = "pioDE_clk",      .id = 5, },
  61         { .n = "trng_clk",       .id = 6, },
  62         { .n = "usart0_clk",     .id = 7, },
  63         { .n = "usart1_clk",     .id = 8, },
  64         { .n = "usart2_clk",     .id = 9, },
  65         { .n = "usart3_clk",     .id = 10, },
  66         { .n = "mci0_clk",       .id = 11, },
  67         { .n = "twi0_clk",       .id = 12, },
  68         { .n = "twi1_clk",       .id = 13, },
  69         { .n = "spi0_clk",       .id = 14, },
  70         { .n = "spi1_clk",       .id = 15, },
  71         { .n = "ssc0_clk",       .id = 16, },
  72         { .n = "ssc1_clk",       .id = 17, },
  73         { .n = "tcb0_clk",       .id = 18, },
  74         { .n = "pwm_clk",        .id = 19, },
  75         { .n = "adc_clk",        .id = 20, },
  76         { .n = "dma0_clk",       .id = 21, },
  77         { .n = "uhphs_clk",      .id = 22, },
  78         { .n = "lcd_clk",        .id = 23, },
  79         { .n = "ac97_clk",       .id = 24, },
  80         { .n = "macb0_clk",      .id = 25, },
  81         { .n = "isi_clk",        .id = 26, },
  82         { .n = "udphs_clk",      .id = 27, },
  83         { .n = "aestdessha_clk", .id = 28, },
  84         { .n = "mci1_clk",       .id = 29, },
  85         { .n = "vdec_clk",       .id = 30, },
  86 };
  87
  88 static void __init at91sam9g45_pmc_setup(struct device_node *np)
  89 {
  90         const char *slck_name, *mainxtal_name;
  91         struct pmc_data *at91sam9g45_pmc;
  92         const char *parent_names[6];
  93         struct regmap *regmap;
  94         struct clk_hw *hw;
  95         int i;
  96         bool bypass;
  97
  98         i = of_property_match_string(np, "clock-names", "slow_clk");
  99         if (i < 0)
 100                 return;
 101
 102         slck_name = of_clk_get_parent_name(np, i);
 103
 104         i = of_property_match_string(np, "clock-names", "main_xtal");
 105         if (i < 0)
 106                 return;
 107         mainxtal_name = of_clk_get_parent_name(np, i);
 108
 109         regmap = device_node_to_regmap(np);
 110         if (IS_ERR(regmap))
 111                 return;
 112
 113         at91sam9g45_pmc = pmc_data_allocate(PMC_PLLACK + 1,
 114                                             nck(at91sam9g45_systemck),
 115                                             nck(at91sam9g45_periphck), 0, 2);
 116         if (!at91sam9g45_pmc)
 117                 return;
 118
 119         bypass = of_property_read_bool(np, "atmel,osc-bypass");
 120
 121         hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
 122                                         bypass);
 123         if (IS_ERR(hw))
 124                 goto err_free;
 125
 126         hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
 127         if (IS_ERR(hw))
 128                 goto err_free;
 129
 130         at91sam9g45_pmc->chws[PMC_MAIN] = hw;
 131
 132         hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
 133                                    &at91rm9200_pll_layout, &plla_characteristics);
 134         if (IS_ERR(hw))
 135                 goto err_free;
 136
 137         hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
 138         if (IS_ERR(hw))
 139                 goto err_free;
 140
 141         at91sam9g45_pmc->chws[PMC_PLLACK] = hw;
 142
 143         hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
 144         if (IS_ERR(hw))
 145                 goto err_free;
 146
 147         at91sam9g45_pmc->chws[PMC_UTMI] = hw;
 148
 149         parent_names[0] = slck_name;
 150         parent_names[1] = "mainck";
 151         parent_names[2] = "plladivck";
 152         parent_names[3] = "utmick";
 153         hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
 154                                            parent_names,
 155                                            &at91rm9200_master_layout,
 156                                            &mck_characteristics,
 157                                            &at91sam9g45_mck_lock,
 158                                            CLK_SET_RATE_GATE, INT_MIN);
 159         if (IS_ERR(hw))
 160                 goto err_free;
 161
 162         hw = at91_clk_register_master_div(regmap, "masterck_div",
 163                                           "masterck_pres",
 164                                           &at91rm9200_master_layout,
 165                                           &mck_characteristics,
 166                                           &at91sam9g45_mck_lock,
 167                                           CLK_SET_RATE_GATE);
 168         if (IS_ERR(hw))
 169                 goto err_free;
 170
 171         at91sam9g45_pmc->chws[PMC_MCK] = hw;
 172
 173         parent_names[0] = "plladivck";
 174         parent_names[1] = "utmick";
 175         hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
 176         if (IS_ERR(hw))
 177                 goto err_free;
 178
 179         parent_names[0] = slck_name;
 180         parent_names[1] = "mainck";
 181         parent_names[2] = "plladivck";
 182         parent_names[3] = "utmick";
 183         parent_names[4] = "masterck_div";
 184         for (i = 0; i < 2; i++) {
 185                 char name[6];
 186
 187                 snprintf(name, sizeof(name), "prog%d", i);
 188
 189                 hw = at91_clk_register_programmable(regmap, name,
 190                                                     parent_names, 5, i,
 191                                                     &at91sam9g45_programmable_layout,
 192                                                     NULL);
 193                 if (IS_ERR(hw))
 194                         goto err_free;
 195
 196                 at91sam9g45_pmc->pchws[i] = hw;
 197         }
 198
 199         for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) {
 200                 hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n,
 201                                               at91sam9g45_systemck[i].p,
 202                                               at91sam9g45_systemck[i].id);
 203                 if (IS_ERR(hw))
 204                         goto err_free;
 205
 206                 at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw;
 207         }
 208
 209         for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {
 210                 hw = at91_clk_register_peripheral(regmap,
 211                                                   at91sam9g45_periphck[i].n,
 212                                                   "masterck_div",
 213                                                   at91sam9g45_periphck[i].id);
 214                 if (IS_ERR(hw))
 215                         goto err_free;
 216
 217                 at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw;
 218         }
 219
 220         of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc);
 221
 222         return;
 223
 224 err_free:
 225         kfree(at91sam9g45_pmc);
 226 }
 227 /*
 228  * The TCB is used as the clocksource so its clock is needed early. This means
 229  * this can't be a platform driver.
 230  */
 231 CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc",
 232                       at91sam9g45_pmc_setup);