drivers/clk/at91/at91sam9x5.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/clk-provider.h>
   3 #include <linux/mfd/syscon.h>
   4 #include <linux/slab.h>
   5
   6 #include <dt-bindings/clock/at91.h>
   7
   8 #include "pmc.h"
   9
  10 static DEFINE_SPINLOCK(mck_lock);
  11
  12 static const struct clk_master_characteristics mck_characteristics = {
  13         .output = { .min = 0, .max = 133333333 },
  14         .divisors = { 1, 2, 4, 3 },
  15         .have_div3_pres = 1,
  16 };
  17
  18 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
  19
  20 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
  21
  22 static const struct clk_range plla_outputs[] = {
  23         { .min = 745000000, .max = 800000000 },
  24         { .min = 695000000, .max = 750000000 },
  25         { .min = 645000000, .max = 700000000 },
  26         { .min = 595000000, .max = 650000000 },
  27         { .min = 545000000, .max = 600000000 },
  28         { .min = 495000000, .max = 555000000 },
  29         { .min = 445000000, .max = 500000000 },
  30         { .min = 400000000, .max = 450000000 },
  31 };
  32
  33 static const struct clk_pll_characteristics plla_characteristics = {
  34         .input = { .min = 2000000, .max = 32000000 },
  35         .num_output = ARRAY_SIZE(plla_outputs),
  36         .output = plla_outputs,
  37         .icpll = plla_icpll,
  38         .out = plla_out,
  39 };
  40
  41 static const struct {
  42         char *n;
  43         char *p;
  44         u8 id;
  45 } at91sam9x5_systemck[] = {
  46         { .n = "ddrck", .p = "masterck_div", .id = 2 },
  47         { .n = "smdck", .p = "smdclk",   .id = 4 },
  48         { .n = "uhpck", .p = "usbck",    .id = 6 },
  49         { .n = "udpck", .p = "usbck",    .id = 7 },
  50         { .n = "pck0",  .p = "prog0",    .id = 8 },
  51         { .n = "pck1",  .p = "prog1",    .id = 9 },
  52 };
  53
  54 static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
  55         .offset = 0x10c,
  56         .cmd = BIT(12),
  57         .pid_mask = GENMASK(5, 0),
  58         .div_mask = GENMASK(17, 16),
  59 };
  60
  61 struct pck {
  62         char *n;
  63         u8 id;
  64 };
  65
  66 static const struct pck at91sam9x5_periphck[] = {
  67         { .n = "pioAB_clk",  .id = 2, },
  68         { .n = "pioCD_clk",  .id = 3, },
  69         { .n = "smd_clk",    .id = 4, },
  70         { .n = "usart0_clk", .id = 5, },
  71         { .n = "usart1_clk", .id = 6, },
  72         { .n = "usart2_clk", .id = 7, },
  73         { .n = "twi0_clk",   .id = 9, },
  74         { .n = "twi1_clk",   .id = 10, },
  75         { .n = "twi2_clk",   .id = 11, },
  76         { .n = "mci0_clk",   .id = 12, },
  77         { .n = "spi0_clk",   .id = 13, },
  78         { .n = "spi1_clk",   .id = 14, },
  79         { .n = "uart0_clk",  .id = 15, },
  80         { .n = "uart1_clk",  .id = 16, },
  81         { .n = "tcb0_clk",   .id = 17, },
  82         { .n = "pwm_clk",    .id = 18, },
  83         { .n = "adc_clk",    .id = 19, },
  84         { .n = "dma0_clk",   .id = 20, },
  85         { .n = "dma1_clk",   .id = 21, },
  86         { .n = "uhphs_clk",  .id = 22, },
  87         { .n = "udphs_clk",  .id = 23, },
  88         { .n = "mci1_clk",   .id = 26, },
  89         { .n = "ssc0_clk",   .id = 28, },
  90 };
  91
  92 static const struct pck at91sam9g15_periphck[] = {
  93         { .n = "lcdc_clk", .id = 25, },
  94         { /* sentinel */}
  95 };
  96
  97 static const struct pck at91sam9g25_periphck[] = {
  98         { .n = "usart3_clk", .id = 8, },
  99         { .n = "macb0_clk", .id = 24, },
 100         { .n = "isi_clk", .id = 25, },
 101         { /* sentinel */}
 102 };
 103
 104 static const struct pck at91sam9g35_periphck[] = {
 105         { .n = "macb0_clk", .id = 24, },
 106         { .n = "lcdc_clk", .id = 25, },
 107         { /* sentinel */}
 108 };
 109
 110 static const struct pck at91sam9x25_periphck[] = {
 111         { .n = "usart3_clk", .id = 8, },
 112         { .n = "macb0_clk", .id = 24, },
 113         { .n = "macb1_clk", .id = 27, },
 114         { .n = "can0_clk", .id = 29, },
 115         { .n = "can1_clk", .id = 30, },
 116         { /* sentinel */}
 117 };
 118
 119 static const struct pck at91sam9x35_periphck[] = {
 120         { .n = "macb0_clk", .id = 24, },
 121         { .n = "lcdc_clk", .id = 25, },
 122         { .n = "can0_clk", .id = 29, },
 123         { .n = "can1_clk", .id = 30, },
 124         { /* sentinel */}
 125 };
 126
 127 static void __init at91sam9x5_pmc_setup(struct device_node *np,
 128                                         const struct pck *extra_pcks,
 129                                         bool has_lcdck)
 130 {
 131         struct clk_range range = CLK_RANGE(0, 0);
 132         const char *slck_name, *mainxtal_name;
 133         struct pmc_data *at91sam9x5_pmc;
 134         const char *parent_names[6];
 135         struct regmap *regmap;
 136         struct clk_hw *hw;
 137         int i;
 138         bool bypass;
 139
 140         i = of_property_match_string(np, "clock-names", "slow_clk");
 141         if (i < 0)
 142                 return;
 143
 144         slck_name = of_clk_get_parent_name(np, i);
 145
 146         i = of_property_match_string(np, "clock-names", "main_xtal");
 147         if (i < 0)
 148                 return;
 149         mainxtal_name = of_clk_get_parent_name(np, i);
 150
 151         regmap = device_node_to_regmap(np);
 152         if (IS_ERR(regmap))
 153                 return;
 154
 155         at91sam9x5_pmc = pmc_data_allocate(PMC_PLLACK + 1,
 156                                            nck(at91sam9x5_systemck), 31, 0, 2);
 157         if (!at91sam9x5_pmc)
 158                 return;
 159
 160         hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
 161                                            50000000);
 162         if (IS_ERR(hw))
 163                 goto err_free;
 164
 165         bypass = of_property_read_bool(np, "atmel,osc-bypass");
 166
 167         hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
 168                                         bypass);
 169         if (IS_ERR(hw))
 170                 goto err_free;
 171
 172         parent_names[0] = "main_rc_osc";
 173         parent_names[1] = "main_osc";
 174         hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
 175         if (IS_ERR(hw))
 176                 goto err_free;
 177
 178         at91sam9x5_pmc->chws[PMC_MAIN] = hw;
 179
 180         hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
 181                                    &at91rm9200_pll_layout, &plla_characteristics);
 182         if (IS_ERR(hw))
 183                 goto err_free;
 184
 185         hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
 186         if (IS_ERR(hw))
 187                 goto err_free;
 188
 189         at91sam9x5_pmc->chws[PMC_PLLACK] = hw;
 190
 191         hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
 192         if (IS_ERR(hw))
 193                 goto err_free;
 194
 195         at91sam9x5_pmc->chws[PMC_UTMI] = hw;
 196
 197         parent_names[0] = slck_name;
 198         parent_names[1] = "mainck";
 199         parent_names[2] = "plladivck";
 200         parent_names[3] = "utmick";
 201         hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
 202                                            parent_names,
 203                                            &at91sam9x5_master_layout,
 204                                            &mck_characteristics, &mck_lock,
 205                                            CLK_SET_RATE_GATE, INT_MIN);
 206         if (IS_ERR(hw))
 207                 goto err_free;
 208
 209         hw = at91_clk_register_master_div(regmap, "masterck_div",
 210                                           "masterck_pres",
 211                                           &at91sam9x5_master_layout,
 212                                           &mck_characteristics, &mck_lock,
 213                                           CLK_SET_RATE_GATE);
 214         if (IS_ERR(hw))
 215                 goto err_free;
 216
 217         at91sam9x5_pmc->chws[PMC_MCK] = hw;
 218
 219         parent_names[0] = "plladivck";
 220         parent_names[1] = "utmick";
 221         hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
 222         if (IS_ERR(hw))
 223                 goto err_free;
 224
 225         hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
 226         if (IS_ERR(hw))
 227                 goto err_free;
 228
 229         parent_names[0] = slck_name;
 230         parent_names[1] = "mainck";
 231         parent_names[2] = "plladivck";
 232         parent_names[3] = "utmick";
 233         parent_names[4] = "masterck_div";
 234         for (i = 0; i < 2; i++) {
 235                 char name[6];
 236
 237                 snprintf(name, sizeof(name), "prog%d", i);
 238
 239                 hw = at91_clk_register_programmable(regmap, name,
 240                                                     parent_names, 5, i,
 241                                                     &at91sam9x5_programmable_layout,
 242                                                     NULL);
 243                 if (IS_ERR(hw))
 244                         goto err_free;
 245
 246                 at91sam9x5_pmc->pchws[i] = hw;
 247         }
 248
 249         for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
 250                 hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
 251                                               at91sam9x5_systemck[i].p,
 252                                               at91sam9x5_systemck[i].id);
 253                 if (IS_ERR(hw))
 254                         goto err_free;
 255
 256                 at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
 257         }
 258
 259         if (has_lcdck) {
 260                 hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", 3);
 261                 if (IS_ERR(hw))
 262                         goto err_free;
 263
 264                 at91sam9x5_pmc->shws[3] = hw;
 265         }
 266
 267         for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
 268                 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
 269                                                          &at91sam9x5_pcr_layout,
 270                                                          at91sam9x5_periphck[i].n,
 271                                                          "masterck_div",
 272                                                          at91sam9x5_periphck[i].id,
 273                                                          &range, INT_MIN);
 274                 if (IS_ERR(hw))
 275                         goto err_free;
 276
 277                 at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
 278         }
 279
 280         for (i = 0; extra_pcks[i].id; i++) {
 281                 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
 282                                                          &at91sam9x5_pcr_layout,
 283                                                          extra_pcks[i].n,
 284                                                          "masterck_div",
 285                                                          extra_pcks[i].id,
 286                                                          &range, INT_MIN);
 287                 if (IS_ERR(hw))
 288                         goto err_free;
 289
 290                 at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
 291         }
 292
 293         of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
 294
 295         return;
 296
 297 err_free:
 298         kfree(at91sam9x5_pmc);
 299 }
 300
 301 static void __init at91sam9g15_pmc_setup(struct device_node *np)
 302 {
 303         at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
 304 }
 305 CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
 306                       at91sam9g15_pmc_setup);
 307
 308 static void __init at91sam9g25_pmc_setup(struct device_node *np)
 309 {
 310         at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
 311 }
 312 CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
 313                       at91sam9g25_pmc_setup);
 314
 315 static void __init at91sam9g35_pmc_setup(struct device_node *np)
 316 {
 317         at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
 318 }
 319 CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
 320                       at91sam9g35_pmc_setup);
 321
 322 static void __init at91sam9x25_pmc_setup(struct device_node *np)
 323 {
 324         at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
 325 }
 326 CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
 327                       at91sam9x25_pmc_setup);
 328
 329 static void __init at91sam9x35_pmc_setup(struct device_node *np)
 330 {
 331         at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
 332 }
 333 CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
 334                       at91sam9x35_pmc_setup);