1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
5 #include <linux/mfd/syscon.h>
6 #include <linux/regmap.h>
7 #include <linux/slab.h>
11 #define MASTER_SOURCE_MAX 4
13 #define PERIPHERAL_AT91RM9200 0
14 #define PERIPHERAL_AT91SAM9X5 1
16 #define PERIPHERAL_MAX 64
18 #define PERIPHERAL_ID_MIN 2
20 #define PROG_SOURCE_MAX 5
23 #define SYSTEM_MAX_ID 31
25 #define GCK_INDEX_DT_AUDIO_PLL 5
27 static DEFINE_SPINLOCK(mck_lock
);
29 #ifdef CONFIG_HAVE_AT91_AUDIO_PLL
30 static void __init
of_sama5d2_clk_audio_pll_frac_setup(struct device_node
*np
)
33 const char *name
= np
->name
;
34 const char *parent_name
;
35 struct regmap
*regmap
;
37 regmap
= syscon_node_to_regmap(of_get_parent(np
));
41 parent_name
= of_clk_get_parent_name(np
, 0);
43 hw
= at91_clk_register_audio_pll_frac(regmap
, name
, parent_name
);
47 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
49 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup
,
50 "atmel,sama5d2-clk-audio-pll-frac",
51 of_sama5d2_clk_audio_pll_frac_setup
);
53 static void __init
of_sama5d2_clk_audio_pll_pad_setup(struct device_node
*np
)
56 const char *name
= np
->name
;
57 const char *parent_name
;
58 struct regmap
*regmap
;
60 regmap
= syscon_node_to_regmap(of_get_parent(np
));
64 parent_name
= of_clk_get_parent_name(np
, 0);
66 hw
= at91_clk_register_audio_pll_pad(regmap
, name
, parent_name
);
70 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
72 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup
,
73 "atmel,sama5d2-clk-audio-pll-pad",
74 of_sama5d2_clk_audio_pll_pad_setup
);
76 static void __init
of_sama5d2_clk_audio_pll_pmc_setup(struct device_node
*np
)
79 const char *name
= np
->name
;
80 const char *parent_name
;
81 struct regmap
*regmap
;
83 regmap
= syscon_node_to_regmap(of_get_parent(np
));
87 parent_name
= of_clk_get_parent_name(np
, 0);
89 hw
= at91_clk_register_audio_pll_pmc(regmap
, name
, parent_name
);
93 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
95 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup
,
96 "atmel,sama5d2-clk-audio-pll-pmc",
97 of_sama5d2_clk_audio_pll_pmc_setup
);
98 #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
100 static const struct clk_pcr_layout dt_pcr_layout
= {
103 .pid_mask
= GENMASK(5, 0),
104 .div_mask
= GENMASK(17, 16),
105 .gckcss_mask
= GENMASK(10, 8),
108 #ifdef CONFIG_HAVE_AT91_GENERATED_CLK
109 #define GENERATED_SOURCE_MAX 6
111 #define GCK_ID_I2S0 54
112 #define GCK_ID_I2S1 55
113 #define GCK_ID_CLASSD 59
115 static void __init
of_sama5d2_clk_generated_setup(struct device_node
*np
)
121 unsigned int num_parents
;
122 const char *parent_names
[GENERATED_SOURCE_MAX
];
123 struct device_node
*gcknp
;
124 struct clk_range range
= CLK_RANGE(0, 0);
125 struct regmap
*regmap
;
127 num_parents
= of_clk_get_parent_count(np
);
128 if (num_parents
== 0 || num_parents
> GENERATED_SOURCE_MAX
)
131 of_clk_parent_fill(np
, parent_names
, num_parents
);
133 num
= of_get_child_count(np
);
134 if (!num
|| num
> PERIPHERAL_MAX
)
137 regmap
= syscon_node_to_regmap(of_get_parent(np
));
141 for_each_child_of_node(np
, gcknp
) {
142 int chg_pid
= INT_MIN
;
144 if (of_property_read_u32(gcknp
, "reg", &id
))
147 if (id
< PERIPHERAL_ID_MIN
|| id
>= PERIPHERAL_MAX
)
150 if (of_property_read_string(np
, "clock-output-names", &name
))
153 of_at91_get_clk_range(gcknp
, "atmel,clk-output-range",
156 if (of_device_is_compatible(np
, "atmel,sama5d2-clk-generated") &&
157 (id
== GCK_ID_I2S0
|| id
== GCK_ID_I2S1
||
158 id
== GCK_ID_CLASSD
))
159 chg_pid
= GCK_INDEX_DT_AUDIO_PLL
;
161 hw
= at91_clk_register_generated(regmap
, &pmc_pcr_lock
,
162 &dt_pcr_layout
, name
,
164 num_parents
, id
, &range
,
169 of_clk_add_hw_provider(gcknp
, of_clk_hw_simple_get
, hw
);
172 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup
, "atmel,sama5d2-clk-generated",
173 of_sama5d2_clk_generated_setup
);
174 #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
176 #ifdef CONFIG_HAVE_AT91_H32MX
177 static void __init
of_sama5d4_clk_h32mx_setup(struct device_node
*np
)
180 const char *name
= np
->name
;
181 const char *parent_name
;
182 struct regmap
*regmap
;
184 regmap
= syscon_node_to_regmap(of_get_parent(np
));
188 parent_name
= of_clk_get_parent_name(np
, 0);
190 hw
= at91_clk_register_h32mx(regmap
, name
, parent_name
);
194 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
196 CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup
, "atmel,sama5d4-clk-h32mx",
197 of_sama5d4_clk_h32mx_setup
);
198 #endif /* CONFIG_HAVE_AT91_H32MX */
200 #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
203 static void __init
of_sama5d2_clk_i2s_mux_setup(struct device_node
*np
)
205 struct regmap
*regmap_sfr
;
207 const char *parent_names
[2];
208 struct device_node
*i2s_mux_np
;
212 regmap_sfr
= syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
213 if (IS_ERR(regmap_sfr
))
216 for_each_child_of_node(np
, i2s_mux_np
) {
217 if (of_property_read_u8(i2s_mux_np
, "reg", &bus_id
))
220 if (bus_id
> I2S_BUS_NR
)
223 ret
= of_clk_parent_fill(i2s_mux_np
, parent_names
, 2);
227 hw
= at91_clk_i2s_mux_register(regmap_sfr
, i2s_mux_np
->name
,
228 parent_names
, 2, bus_id
);
232 of_clk_add_hw_provider(i2s_mux_np
, of_clk_hw_simple_get
, hw
);
235 CLK_OF_DECLARE(sama5d2_clk_i2s_mux
, "atmel,sama5d2-clk-i2s-mux",
236 of_sama5d2_clk_i2s_mux_setup
);
237 #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
239 static void __init
of_at91rm9200_clk_main_osc_setup(struct device_node
*np
)
242 const char *name
= np
->name
;
243 const char *parent_name
;
244 struct regmap
*regmap
;
247 of_property_read_string(np
, "clock-output-names", &name
);
248 bypass
= of_property_read_bool(np
, "atmel,osc-bypass");
249 parent_name
= of_clk_get_parent_name(np
, 0);
251 regmap
= syscon_node_to_regmap(of_get_parent(np
));
255 hw
= at91_clk_register_main_osc(regmap
, name
, parent_name
, bypass
);
259 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
261 CLK_OF_DECLARE(at91rm9200_clk_main_osc
, "atmel,at91rm9200-clk-main-osc",
262 of_at91rm9200_clk_main_osc_setup
);
264 static void __init
of_at91sam9x5_clk_main_rc_osc_setup(struct device_node
*np
)
269 const char *name
= np
->name
;
270 struct regmap
*regmap
;
272 of_property_read_string(np
, "clock-output-names", &name
);
273 of_property_read_u32(np
, "clock-frequency", &frequency
);
274 of_property_read_u32(np
, "clock-accuracy", &accuracy
);
276 regmap
= syscon_node_to_regmap(of_get_parent(np
));
280 hw
= at91_clk_register_main_rc_osc(regmap
, name
, frequency
, accuracy
);
284 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
286 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc
, "atmel,at91sam9x5-clk-main-rc-osc",
287 of_at91sam9x5_clk_main_rc_osc_setup
);
289 static void __init
of_at91rm9200_clk_main_setup(struct device_node
*np
)
292 const char *parent_name
;
293 const char *name
= np
->name
;
294 struct regmap
*regmap
;
296 parent_name
= of_clk_get_parent_name(np
, 0);
297 of_property_read_string(np
, "clock-output-names", &name
);
299 regmap
= syscon_node_to_regmap(of_get_parent(np
));
303 hw
= at91_clk_register_rm9200_main(regmap
, name
, parent_name
);
307 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
309 CLK_OF_DECLARE(at91rm9200_clk_main
, "atmel,at91rm9200-clk-main",
310 of_at91rm9200_clk_main_setup
);
312 static void __init
of_at91sam9x5_clk_main_setup(struct device_node
*np
)
315 const char *parent_names
[2];
316 unsigned int num_parents
;
317 const char *name
= np
->name
;
318 struct regmap
*regmap
;
320 num_parents
= of_clk_get_parent_count(np
);
321 if (num_parents
== 0 || num_parents
> 2)
324 of_clk_parent_fill(np
, parent_names
, num_parents
);
325 regmap
= syscon_node_to_regmap(of_get_parent(np
));
329 of_property_read_string(np
, "clock-output-names", &name
);
331 hw
= at91_clk_register_sam9x5_main(regmap
, name
, parent_names
,
336 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
338 CLK_OF_DECLARE(at91sam9x5_clk_main
, "atmel,at91sam9x5-clk-main",
339 of_at91sam9x5_clk_main_setup
);
341 static struct clk_master_characteristics
* __init
342 of_at91_clk_master_get_characteristics(struct device_node
*np
)
344 struct clk_master_characteristics
*characteristics
;
346 characteristics
= kzalloc(sizeof(*characteristics
), GFP_KERNEL
);
347 if (!characteristics
)
350 if (of_at91_get_clk_range(np
, "atmel,clk-output-range", &characteristics
->output
))
351 goto out_free_characteristics
;
353 of_property_read_u32_array(np
, "atmel,clk-divisors",
354 characteristics
->divisors
, 4);
356 characteristics
->have_div3_pres
=
357 of_property_read_bool(np
, "atmel,master-clk-have-div3-pres");
359 return characteristics
;
361 out_free_characteristics
:
362 kfree(characteristics
);
367 of_at91_clk_master_setup(struct device_node
*np
,
368 const struct clk_master_layout
*layout
)
371 unsigned int num_parents
;
372 const char *parent_names
[MASTER_SOURCE_MAX
];
373 const char *name
= np
->name
;
374 struct clk_master_characteristics
*characteristics
;
375 struct regmap
*regmap
;
377 num_parents
= of_clk_get_parent_count(np
);
378 if (num_parents
== 0 || num_parents
> MASTER_SOURCE_MAX
)
381 of_clk_parent_fill(np
, parent_names
, num_parents
);
383 of_property_read_string(np
, "clock-output-names", &name
);
385 characteristics
= of_at91_clk_master_get_characteristics(np
);
386 if (!characteristics
)
389 regmap
= syscon_node_to_regmap(of_get_parent(np
));
393 hw
= at91_clk_register_master_pres(regmap
, "masterck_pres", num_parents
,
394 parent_names
, layout
,
395 characteristics
, &mck_lock
,
396 CLK_SET_RATE_GATE
, INT_MIN
);
398 goto out_free_characteristics
;
400 hw
= at91_clk_register_master_div(regmap
, name
, "masterck_pres",
401 layout
, characteristics
,
402 &mck_lock
, CLK_SET_RATE_GATE
);
404 goto out_free_characteristics
;
406 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
409 out_free_characteristics
:
410 kfree(characteristics
);
413 static void __init
of_at91rm9200_clk_master_setup(struct device_node
*np
)
415 of_at91_clk_master_setup(np
, &at91rm9200_master_layout
);
417 CLK_OF_DECLARE(at91rm9200_clk_master
, "atmel,at91rm9200-clk-master",
418 of_at91rm9200_clk_master_setup
);
420 static void __init
of_at91sam9x5_clk_master_setup(struct device_node
*np
)
422 of_at91_clk_master_setup(np
, &at91sam9x5_master_layout
);
424 CLK_OF_DECLARE(at91sam9x5_clk_master
, "atmel,at91sam9x5-clk-master",
425 of_at91sam9x5_clk_master_setup
);
428 of_at91_clk_periph_setup(struct device_node
*np
, u8 type
)
433 const char *parent_name
;
435 struct device_node
*periphclknp
;
436 struct regmap
*regmap
;
438 parent_name
= of_clk_get_parent_name(np
, 0);
442 num
= of_get_child_count(np
);
443 if (!num
|| num
> PERIPHERAL_MAX
)
446 regmap
= syscon_node_to_regmap(of_get_parent(np
));
450 for_each_child_of_node(np
, periphclknp
) {
451 if (of_property_read_u32(periphclknp
, "reg", &id
))
454 if (id
>= PERIPHERAL_MAX
)
457 if (of_property_read_string(np
, "clock-output-names", &name
))
458 name
= periphclknp
->name
;
460 if (type
== PERIPHERAL_AT91RM9200
) {
461 hw
= at91_clk_register_peripheral(regmap
, name
,
464 struct clk_range range
= CLK_RANGE(0, 0);
466 of_at91_get_clk_range(periphclknp
,
467 "atmel,clk-output-range",
470 hw
= at91_clk_register_sam9x5_peripheral(regmap
,
482 of_clk_add_hw_provider(periphclknp
, of_clk_hw_simple_get
, hw
);
486 static void __init
of_at91rm9200_clk_periph_setup(struct device_node
*np
)
488 of_at91_clk_periph_setup(np
, PERIPHERAL_AT91RM9200
);
490 CLK_OF_DECLARE(at91rm9200_clk_periph
, "atmel,at91rm9200-clk-peripheral",
491 of_at91rm9200_clk_periph_setup
);
493 static void __init
of_at91sam9x5_clk_periph_setup(struct device_node
*np
)
495 of_at91_clk_periph_setup(np
, PERIPHERAL_AT91SAM9X5
);
497 CLK_OF_DECLARE(at91sam9x5_clk_periph
, "atmel,at91sam9x5-clk-peripheral",
498 of_at91sam9x5_clk_periph_setup
);
500 static struct clk_pll_characteristics
* __init
501 of_at91_clk_pll_get_characteristics(struct device_node
*np
)
508 struct clk_range input
;
509 struct clk_range
*output
;
512 struct clk_pll_characteristics
*characteristics
;
514 if (of_at91_get_clk_range(np
, "atmel,clk-input-range", &input
))
517 if (of_property_read_u32(np
, "#atmel,pll-clk-output-range-cells",
521 if (num_cells
< 2 || num_cells
> 4)
524 if (!of_get_property(np
, "atmel,pll-clk-output-ranges", &tmp
))
526 num_output
= tmp
/ (sizeof(u32
) * num_cells
);
528 characteristics
= kzalloc(sizeof(*characteristics
), GFP_KERNEL
);
529 if (!characteristics
)
532 output
= kcalloc(num_output
, sizeof(*output
), GFP_KERNEL
);
534 goto out_free_characteristics
;
537 out
= kcalloc(num_output
, sizeof(*out
), GFP_KERNEL
);
539 goto out_free_output
;
543 icpll
= kcalloc(num_output
, sizeof(*icpll
), GFP_KERNEL
);
545 goto out_free_output
;
548 for (i
= 0; i
< num_output
; i
++) {
549 offset
= i
* num_cells
;
550 if (of_property_read_u32_index(np
,
551 "atmel,pll-clk-output-ranges",
553 goto out_free_output
;
555 if (of_property_read_u32_index(np
,
556 "atmel,pll-clk-output-ranges",
558 goto out_free_output
;
564 if (of_property_read_u32_index(np
,
565 "atmel,pll-clk-output-ranges",
567 goto out_free_output
;
573 if (of_property_read_u32_index(np
,
574 "atmel,pll-clk-output-ranges",
576 goto out_free_output
;
580 characteristics
->input
= input
;
581 characteristics
->num_output
= num_output
;
582 characteristics
->output
= output
;
583 characteristics
->out
= out
;
584 characteristics
->icpll
= icpll
;
585 return characteristics
;
591 out_free_characteristics
:
592 kfree(characteristics
);
597 of_at91_clk_pll_setup(struct device_node
*np
,
598 const struct clk_pll_layout
*layout
)
602 struct regmap
*regmap
;
603 const char *parent_name
;
604 const char *name
= np
->name
;
605 struct clk_pll_characteristics
*characteristics
;
607 if (of_property_read_u32(np
, "reg", &id
))
610 parent_name
= of_clk_get_parent_name(np
, 0);
612 of_property_read_string(np
, "clock-output-names", &name
);
614 regmap
= syscon_node_to_regmap(of_get_parent(np
));
618 characteristics
= of_at91_clk_pll_get_characteristics(np
);
619 if (!characteristics
)
622 hw
= at91_clk_register_pll(regmap
, name
, parent_name
, id
, layout
,
625 goto out_free_characteristics
;
627 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
630 out_free_characteristics
:
631 kfree(characteristics
);
634 static void __init
of_at91rm9200_clk_pll_setup(struct device_node
*np
)
636 of_at91_clk_pll_setup(np
, &at91rm9200_pll_layout
);
638 CLK_OF_DECLARE(at91rm9200_clk_pll
, "atmel,at91rm9200-clk-pll",
639 of_at91rm9200_clk_pll_setup
);
641 static void __init
of_at91sam9g45_clk_pll_setup(struct device_node
*np
)
643 of_at91_clk_pll_setup(np
, &at91sam9g45_pll_layout
);
645 CLK_OF_DECLARE(at91sam9g45_clk_pll
, "atmel,at91sam9g45-clk-pll",
646 of_at91sam9g45_clk_pll_setup
);
648 static void __init
of_at91sam9g20_clk_pllb_setup(struct device_node
*np
)
650 of_at91_clk_pll_setup(np
, &at91sam9g20_pllb_layout
);
652 CLK_OF_DECLARE(at91sam9g20_clk_pllb
, "atmel,at91sam9g20-clk-pllb",
653 of_at91sam9g20_clk_pllb_setup
);
655 static void __init
of_sama5d3_clk_pll_setup(struct device_node
*np
)
657 of_at91_clk_pll_setup(np
, &sama5d3_pll_layout
);
659 CLK_OF_DECLARE(sama5d3_clk_pll
, "atmel,sama5d3-clk-pll",
660 of_sama5d3_clk_pll_setup
);
663 of_at91sam9x5_clk_plldiv_setup(struct device_node
*np
)
666 const char *parent_name
;
667 const char *name
= np
->name
;
668 struct regmap
*regmap
;
670 parent_name
= of_clk_get_parent_name(np
, 0);
672 of_property_read_string(np
, "clock-output-names", &name
);
674 regmap
= syscon_node_to_regmap(of_get_parent(np
));
678 hw
= at91_clk_register_plldiv(regmap
, name
, parent_name
);
682 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
684 CLK_OF_DECLARE(at91sam9x5_clk_plldiv
, "atmel,at91sam9x5-clk-plldiv",
685 of_at91sam9x5_clk_plldiv_setup
);
688 of_at91_clk_prog_setup(struct device_node
*np
,
689 const struct clk_programmable_layout
*layout
,
695 unsigned int num_parents
;
696 const char *parent_names
[PROG_SOURCE_MAX
];
698 struct device_node
*progclknp
;
699 struct regmap
*regmap
;
701 num_parents
= of_clk_get_parent_count(np
);
702 if (num_parents
== 0 || num_parents
> PROG_SOURCE_MAX
)
705 of_clk_parent_fill(np
, parent_names
, num_parents
);
707 num
= of_get_child_count(np
);
708 if (!num
|| num
> (PROG_ID_MAX
+ 1))
711 regmap
= syscon_node_to_regmap(of_get_parent(np
));
715 for_each_child_of_node(np
, progclknp
) {
716 if (of_property_read_u32(progclknp
, "reg", &id
))
719 if (of_property_read_string(np
, "clock-output-names", &name
))
720 name
= progclknp
->name
;
722 hw
= at91_clk_register_programmable(regmap
, name
,
723 parent_names
, num_parents
,
724 id
, layout
, mux_table
);
728 of_clk_add_hw_provider(progclknp
, of_clk_hw_simple_get
, hw
);
732 static void __init
of_at91rm9200_clk_prog_setup(struct device_node
*np
)
734 of_at91_clk_prog_setup(np
, &at91rm9200_programmable_layout
, NULL
);
736 CLK_OF_DECLARE(at91rm9200_clk_prog
, "atmel,at91rm9200-clk-programmable",
737 of_at91rm9200_clk_prog_setup
);
739 static void __init
of_at91sam9g45_clk_prog_setup(struct device_node
*np
)
741 of_at91_clk_prog_setup(np
, &at91sam9g45_programmable_layout
, NULL
);
743 CLK_OF_DECLARE(at91sam9g45_clk_prog
, "atmel,at91sam9g45-clk-programmable",
744 of_at91sam9g45_clk_prog_setup
);
746 static void __init
of_at91sam9x5_clk_prog_setup(struct device_node
*np
)
748 of_at91_clk_prog_setup(np
, &at91sam9x5_programmable_layout
, NULL
);
750 CLK_OF_DECLARE(at91sam9x5_clk_prog
, "atmel,at91sam9x5-clk-programmable",
751 of_at91sam9x5_clk_prog_setup
);
753 static void __init
of_at91sam9260_clk_slow_setup(struct device_node
*np
)
756 const char *parent_names
[2];
757 unsigned int num_parents
;
758 const char *name
= np
->name
;
759 struct regmap
*regmap
;
761 num_parents
= of_clk_get_parent_count(np
);
762 if (num_parents
!= 2)
765 of_clk_parent_fill(np
, parent_names
, num_parents
);
766 regmap
= syscon_node_to_regmap(of_get_parent(np
));
770 of_property_read_string(np
, "clock-output-names", &name
);
772 hw
= at91_clk_register_sam9260_slow(regmap
, name
, parent_names
,
777 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
779 CLK_OF_DECLARE(at91sam9260_clk_slow
, "atmel,at91sam9260-clk-slow",
780 of_at91sam9260_clk_slow_setup
);
782 #ifdef CONFIG_HAVE_AT91_SMD
783 #define SMD_SOURCE_MAX 2
785 static void __init
of_at91sam9x5_clk_smd_setup(struct device_node
*np
)
788 unsigned int num_parents
;
789 const char *parent_names
[SMD_SOURCE_MAX
];
790 const char *name
= np
->name
;
791 struct regmap
*regmap
;
793 num_parents
= of_clk_get_parent_count(np
);
794 if (num_parents
== 0 || num_parents
> SMD_SOURCE_MAX
)
797 of_clk_parent_fill(np
, parent_names
, num_parents
);
799 of_property_read_string(np
, "clock-output-names", &name
);
801 regmap
= syscon_node_to_regmap(of_get_parent(np
));
805 hw
= at91sam9x5_clk_register_smd(regmap
, name
, parent_names
,
810 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
812 CLK_OF_DECLARE(at91sam9x5_clk_smd
, "atmel,at91sam9x5-clk-smd",
813 of_at91sam9x5_clk_smd_setup
);
814 #endif /* CONFIG_HAVE_AT91_SMD */
816 static void __init
of_at91rm9200_clk_sys_setup(struct device_node
*np
)
822 struct device_node
*sysclknp
;
823 const char *parent_name
;
824 struct regmap
*regmap
;
826 num
= of_get_child_count(np
);
827 if (num
> (SYSTEM_MAX_ID
+ 1))
830 regmap
= syscon_node_to_regmap(of_get_parent(np
));
834 for_each_child_of_node(np
, sysclknp
) {
835 if (of_property_read_u32(sysclknp
, "reg", &id
))
838 if (of_property_read_string(np
, "clock-output-names", &name
))
839 name
= sysclknp
->name
;
841 parent_name
= of_clk_get_parent_name(sysclknp
, 0);
843 hw
= at91_clk_register_system(regmap
, name
, parent_name
, id
);
847 of_clk_add_hw_provider(sysclknp
, of_clk_hw_simple_get
, hw
);
850 CLK_OF_DECLARE(at91rm9200_clk_sys
, "atmel,at91rm9200-clk-system",
851 of_at91rm9200_clk_sys_setup
);
853 #ifdef CONFIG_HAVE_AT91_USB_CLK
854 #define USB_SOURCE_MAX 2
856 static void __init
of_at91sam9x5_clk_usb_setup(struct device_node
*np
)
859 unsigned int num_parents
;
860 const char *parent_names
[USB_SOURCE_MAX
];
861 const char *name
= np
->name
;
862 struct regmap
*regmap
;
864 num_parents
= of_clk_get_parent_count(np
);
865 if (num_parents
== 0 || num_parents
> USB_SOURCE_MAX
)
868 of_clk_parent_fill(np
, parent_names
, num_parents
);
870 of_property_read_string(np
, "clock-output-names", &name
);
872 regmap
= syscon_node_to_regmap(of_get_parent(np
));
876 hw
= at91sam9x5_clk_register_usb(regmap
, name
, parent_names
,
881 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
883 CLK_OF_DECLARE(at91sam9x5_clk_usb
, "atmel,at91sam9x5-clk-usb",
884 of_at91sam9x5_clk_usb_setup
);
886 static void __init
of_at91sam9n12_clk_usb_setup(struct device_node
*np
)
889 const char *parent_name
;
890 const char *name
= np
->name
;
891 struct regmap
*regmap
;
893 parent_name
= of_clk_get_parent_name(np
, 0);
897 of_property_read_string(np
, "clock-output-names", &name
);
899 regmap
= syscon_node_to_regmap(of_get_parent(np
));
903 hw
= at91sam9n12_clk_register_usb(regmap
, name
, parent_name
);
907 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
909 CLK_OF_DECLARE(at91sam9n12_clk_usb
, "atmel,at91sam9n12-clk-usb",
910 of_at91sam9n12_clk_usb_setup
);
912 static void __init
of_at91rm9200_clk_usb_setup(struct device_node
*np
)
915 const char *parent_name
;
916 const char *name
= np
->name
;
917 u32 divisors
[4] = {0, 0, 0, 0};
918 struct regmap
*regmap
;
920 parent_name
= of_clk_get_parent_name(np
, 0);
924 of_property_read_u32_array(np
, "atmel,clk-divisors", divisors
, 4);
928 of_property_read_string(np
, "clock-output-names", &name
);
930 regmap
= syscon_node_to_regmap(of_get_parent(np
));
933 hw
= at91rm9200_clk_register_usb(regmap
, name
, parent_name
, divisors
);
937 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
939 CLK_OF_DECLARE(at91rm9200_clk_usb
, "atmel,at91rm9200-clk-usb",
940 of_at91rm9200_clk_usb_setup
);
941 #endif /* CONFIG_HAVE_AT91_USB_CLK */
943 #ifdef CONFIG_HAVE_AT91_UTMI
944 static void __init
of_at91sam9x5_clk_utmi_setup(struct device_node
*np
)
947 const char *parent_name
;
948 const char *name
= np
->name
;
949 struct regmap
*regmap_pmc
, *regmap_sfr
;
951 parent_name
= of_clk_get_parent_name(np
, 0);
953 of_property_read_string(np
, "clock-output-names", &name
);
955 regmap_pmc
= syscon_node_to_regmap(of_get_parent(np
));
956 if (IS_ERR(regmap_pmc
))
960 * If the device supports different mainck rates, this value has to be
961 * set in the UTMI Clock Trimming register.
962 * - 9x5: mainck supports several rates but it is indicated that a
963 * 12 MHz is needed in case of USB.
964 * - sama5d3 and sama5d2: mainck supports several rates. Configuring
965 * the FREQ field of the UTMI Clock Trimming register is mandatory.
966 * - sama5d4: mainck is at 12 MHz.
968 * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
970 regmap_sfr
= syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
971 if (IS_ERR(regmap_sfr
)) {
972 regmap_sfr
= syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
973 if (IS_ERR(regmap_sfr
))
977 hw
= at91_clk_register_utmi(regmap_pmc
, regmap_sfr
, name
, parent_name
);
981 of_clk_add_hw_provider(np
, of_clk_hw_simple_get
, hw
);
983 CLK_OF_DECLARE(at91sam9x5_clk_utmi
, "atmel,at91sam9x5-clk-utmi",
984 of_at91sam9x5_clk_utmi_setup
);
985 #endif /* CONFIG_HAVE_AT91_UTMI */