drivers/clk/axs10x/pll_clock.c

   1 /*
   2  * Synopsys AXS10X SDP Generic PLL clock driver
   3  *
   4  * Copyright (C) 2017 Synopsys
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/module.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/device.h>
  17 #include <linux/io.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/slab.h>
  21 #include <linux/of.h>
  22
  23 /* PLL registers addresses */
  24 #define PLL_REG_IDIV    0x0
  25 #define PLL_REG_FBDIV   0x4
  26 #define PLL_REG_ODIV    0x8
  27
  28 /*
  29  * Bit fields of the PLL IDIV/FBDIV/ODIV registers:
  30  *  ________________________________________________________________________
  31  * |31                15|    14    |   13   |  12  |11         6|5         0|
  32  * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
  33  * |____________________|__________|________|______|____________|___________|
  34  *
  35  * Following macros determine the way of access to these registers
  36  * They should be set up only using the macros.
  37  * reg should be an u32 variable.
  38  */
  39
  40 #define PLL_REG_GET_LOW(reg)                    \
  41         (((reg) & (0x3F << 0)) >> 0)
  42 #define PLL_REG_GET_HIGH(reg)                   \
  43         (((reg) & (0x3F << 6)) >> 6)
  44 #define PLL_REG_GET_EDGE(reg)                   \
  45         (((reg) & (BIT(12))) ? 1 : 0)
  46 #define PLL_REG_GET_BYPASS(reg)                 \
  47         (((reg) & (BIT(13))) ? 1 : 0)
  48 #define PLL_REG_GET_NOUPD(reg)                  \
  49         (((reg) & (BIT(14))) ? 1 : 0)
  50 #define PLL_REG_GET_PAD(reg)                    \
  51         (((reg) & (0x1FFFF << 15)) >> 15)
  52
  53 #define PLL_REG_SET_LOW(reg, value)             \
  54         { reg |= (((value) & 0x3F) << 0); }
  55 #define PLL_REG_SET_HIGH(reg, value)            \
  56         { reg |= (((value) & 0x3F) << 6); }
  57 #define PLL_REG_SET_EDGE(reg, value)            \
  58         { reg |= (((value) & 0x01) << 12); }
  59 #define PLL_REG_SET_BYPASS(reg, value)          \
  60         { reg |= (((value) & 0x01) << 13); }
  61 #define PLL_REG_SET_NOUPD(reg, value)           \
  62         { reg |= (((value) & 0x01) << 14); }
  63 #define PLL_REG_SET_PAD(reg, value)             \
  64         { reg |= (((value) & 0x1FFFF) << 15); }
  65
  66 #define PLL_LOCK        BIT(0)
  67 #define PLL_ERROR       BIT(1)
  68 #define PLL_MAX_LOCK_TIME 100 /* 100 us */
  69
  70 struct axs10x_pll_cfg {
  71         u32 rate;
  72         u32 idiv;
  73         u32 fbdiv;
  74         u32 odiv;
  75 };
  76
  77 static const struct axs10x_pll_cfg arc_pll_cfg[] = {
  78         { 33333333,  1, 1,  1 },
  79         { 50000000,  1, 30, 20 },
  80         { 75000000,  2, 45, 10 },
  81         { 90000000,  2, 54, 10 },
  82         { 100000000, 1, 30, 10 },
  83         { 125000000, 2, 45, 6 },
  84         {}
  85 };
  86
  87 static const struct axs10x_pll_cfg pgu_pll_cfg[] = {
  88         { 25200000, 1, 84, 90 },
  89         { 50000000, 1, 100, 54 },
  90         { 74250000, 1, 44, 16 },
  91         {}
  92 };
  93
  94 struct axs10x_pll_clk {
  95         struct clk_hw hw;
  96         void __iomem *base;
  97         void __iomem *lock;
  98         const struct axs10x_pll_cfg *pll_cfg;
  99         struct device *dev;
 100 };
 101
 102 static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
 103                                     u32 val)
 104 {
 105         iowrite32(val, clk->base + reg);
 106 }
 107
 108 static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
 109 {
 110         return ioread32(clk->base + reg);
 111 }
 112
 113 static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)
 114 {
 115         return container_of(hw, struct axs10x_pll_clk, hw);
 116 }
 117
 118 static inline u32 axs10x_div_get_value(u32 reg)
 119 {
 120         if (PLL_REG_GET_BYPASS(reg))
 121                 return 1;
 122
 123         return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
 124 }
 125
 126 static inline u32 axs10x_encode_div(unsigned int id, int upd)
 127 {
 128         u32 div = 0;
 129
 130         PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);
 131         PLL_REG_SET_HIGH(div, id >> 1);
 132         PLL_REG_SET_EDGE(div, id % 2);
 133         PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
 134         PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
 135
 136         return div;
 137 }
 138
 139 static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
 140                                             unsigned long parent_rate)
 141 {
 142         u64 rate;
 143         u32 idiv, fbdiv, odiv;
 144         struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
 145
 146         idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));
 147         fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
 148         odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));
 149
 150         rate = (u64)parent_rate * fbdiv;
 151         do_div(rate, idiv * odiv);
 152
 153         return rate;
 154 }
 155
 156 static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 157                                   unsigned long *prate)
 158 {
 159         int i;
 160         long best_rate;
 161         struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
 162         const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
 163
 164         if (pll_cfg[0].rate == 0)
 165                 return -EINVAL;
 166
 167         best_rate = pll_cfg[0].rate;
 168
 169         for (i = 1; pll_cfg[i].rate != 0; i++) {
 170                 if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
 171                         best_rate = pll_cfg[i].rate;
 172         }
 173
 174         return best_rate;
 175 }
 176
 177 static int axs10x_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 178                                unsigned long parent_rate)
 179 {
 180         int i;
 181         struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
 182         const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
 183
 184         for (i = 0; pll_cfg[i].rate != 0; i++) {
 185                 if (pll_cfg[i].rate == rate) {
 186                         axs10x_pll_write(clk, PLL_REG_IDIV,
 187                                          axs10x_encode_div(pll_cfg[i].idiv, 0));
 188                         axs10x_pll_write(clk, PLL_REG_FBDIV,
 189                                          axs10x_encode_div(pll_cfg[i].fbdiv, 0));
 190                         axs10x_pll_write(clk, PLL_REG_ODIV,
 191                                          axs10x_encode_div(pll_cfg[i].odiv, 1));
 192
 193                         /*
 194                          * Wait until CGU relocks and check error status.
 195                          * If after timeout CGU is unlocked yet return error
 196                          */
 197                         udelay(PLL_MAX_LOCK_TIME);
 198                         if (!(ioread32(clk->lock) & PLL_LOCK))
 199                                 return -ETIMEDOUT;
 200
 201                         if (ioread32(clk->lock) & PLL_ERROR)
 202                                 return -EINVAL;
 203
 204                         return 0;
 205                 }
 206         }
 207
 208         dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
 209                         parent_rate);
 210         return -EINVAL;
 211 }
 212
 213 static const struct clk_ops axs10x_pll_ops = {
 214         .recalc_rate = axs10x_pll_recalc_rate,
 215         .round_rate = axs10x_pll_round_rate,
 216         .set_rate = axs10x_pll_set_rate,
 217 };
 218
 219 static int axs10x_pll_clk_probe(struct platform_device *pdev)
 220 {
 221         struct device *dev = &pdev->dev;
 222         const char *parent_name;
 223         struct axs10x_pll_clk *pll_clk;
 224         struct clk_init_data init = { };
 225         int ret;
 226
 227         pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
 228         if (!pll_clk)
 229                 return -ENOMEM;
 230
 231         pll_clk->base = devm_platform_ioremap_resource(pdev, 0);
 232         if (IS_ERR(pll_clk->base))
 233                 return PTR_ERR(pll_clk->base);
 234
 235         pll_clk->lock = devm_platform_ioremap_resource(pdev, 1);
 236         if (IS_ERR(pll_clk->lock))
 237                 return PTR_ERR(pll_clk->lock);
 238
 239         init.name = dev->of_node->name;
 240         init.ops = &axs10x_pll_ops;
 241         parent_name = of_clk_get_parent_name(dev->of_node, 0);
 242         init.parent_names = &parent_name;
 243         init.num_parents = 1;
 244         pll_clk->hw.init = &init;
 245         pll_clk->dev = dev;
 246         pll_clk->pll_cfg = of_device_get_match_data(dev);
 247
 248         if (!pll_clk->pll_cfg) {
 249                 dev_err(dev, "No OF match data provided\n");
 250                 return -EINVAL;
 251         }
 252
 253         ret = devm_clk_hw_register(dev, &pll_clk->hw);
 254         if (ret) {
 255                 dev_err(dev, "failed to register %s clock\n", init.name);
 256                 return ret;
 257         }
 258
 259         return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
 260                         &pll_clk->hw);
 261 }
 262
 263 static int axs10x_pll_clk_remove(struct platform_device *pdev)
 264 {
 265         of_clk_del_provider(pdev->dev.of_node);
 266         return 0;
 267 }
 268
 269 static void __init of_axs10x_pll_clk_setup(struct device_node *node)
 270 {
 271         const char *parent_name;
 272         struct axs10x_pll_clk *pll_clk;
 273         struct clk_init_data init = { };
 274         int ret;
 275
 276         pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
 277         if (!pll_clk)
 278                 return;
 279
 280         pll_clk->base = of_iomap(node, 0);
 281         if (!pll_clk->base) {
 282                 pr_err("failed to map pll div registers\n");
 283                 goto err_free_pll_clk;
 284         }
 285
 286         pll_clk->lock = of_iomap(node, 1);
 287         if (!pll_clk->lock) {
 288                 pr_err("failed to map pll lock register\n");
 289                 goto err_unmap_base;
 290         }
 291
 292         init.name = node->name;
 293         init.ops = &axs10x_pll_ops;
 294         parent_name = of_clk_get_parent_name(node, 0);
 295         init.parent_names = &parent_name;
 296         init.num_parents = parent_name ? 1 : 0;
 297         pll_clk->hw.init = &init;
 298         pll_clk->pll_cfg = arc_pll_cfg;
 299
 300         ret = clk_hw_register(NULL, &pll_clk->hw);
 301         if (ret) {
 302                 pr_err("failed to register %pOFn clock\n", node);
 303                 goto err_unmap_lock;
 304         }
 305
 306         ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
 307         if (ret) {
 308                 pr_err("failed to add hw provider for %pOFn clock\n", node);
 309                 goto err_unregister_clk;
 310         }
 311
 312         return;
 313
 314 err_unregister_clk:
 315         clk_hw_unregister(&pll_clk->hw);
 316 err_unmap_lock:
 317         iounmap(pll_clk->lock);
 318 err_unmap_base:
 319         iounmap(pll_clk->base);
 320 err_free_pll_clk:
 321         kfree(pll_clk);
 322 }
 323 CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
 324                of_axs10x_pll_clk_setup);
 325
 326 static const struct of_device_id axs10x_pll_clk_id[] = {
 327         { .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
 328         { }
 329 };
 330 MODULE_DEVICE_TABLE(of, axs10x_pll_clk_id);
 331
 332 static struct platform_driver axs10x_pll_clk_driver = {
 333         .driver = {
 334                 .name = "axs10x-pll-clock",
 335                 .of_match_table = axs10x_pll_clk_id,
 336         },
 337         .probe = axs10x_pll_clk_probe,
 338         .remove = axs10x_pll_clk_remove,
 339 };
 340 builtin_platform_driver(axs10x_pll_clk_driver);
 341
 342 MODULE_AUTHOR("Vlad Zakharov <vzakhar@synopsys.com>");
 343 MODULE_DESCRIPTION("Synopsys AXS10X SDP Generic PLL Clock Driver");
 344 MODULE_LICENSE("GPL v2");