Merge tag 'trace-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[linux/fpc-iii.git] / drivers / clk / bcm / clk-bcm2835.c
blob1ac803e14fa3e17bcc8775dcb12aed891e7ea629
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010,2015 Broadcom
4 * Copyright (C) 2012 Stephen Warren
5 */
7 /**
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
11 * oscillator running at 19.2Mhz. After the oscillator there are 5
12 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
13 * and "HDMI displays". Those 5 PLLs each can divide their output to
14 * produce up to 4 channels. Finally, there is the level of clocks to
15 * be consumed by other hardware components (like "H264" or "HDMI
16 * state machine"), which divide off of some subset of the PLL
17 * channels.
19 * All of the clocks in the tree are exposed in the DT, because the DT
20 * may want to make assignments of the final layer of clocks to the
21 * PLL channels, and some components of the hardware will actually
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
24 * generator).
27 #include <linux/clk-provider.h>
28 #include <linux/clkdev.h>
29 #include <linux/clk.h>
30 #include <linux/debugfs.h>
31 #include <linux/delay.h>
32 #include <linux/io.h>
33 #include <linux/module.h>
34 #include <linux/of_device.h>
35 #include <linux/platform_device.h>
36 #include <linux/slab.h>
37 #include <dt-bindings/clock/bcm2835.h>
39 #define CM_PASSWORD 0x5a000000
41 #define CM_GNRICCTL 0x000
42 #define CM_GNRICDIV 0x004
43 # define CM_DIV_FRAC_BITS 12
44 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
46 #define CM_VPUCTL 0x008
47 #define CM_VPUDIV 0x00c
48 #define CM_SYSCTL 0x010
49 #define CM_SYSDIV 0x014
50 #define CM_PERIACTL 0x018
51 #define CM_PERIADIV 0x01c
52 #define CM_PERIICTL 0x020
53 #define CM_PERIIDIV 0x024
54 #define CM_H264CTL 0x028
55 #define CM_H264DIV 0x02c
56 #define CM_ISPCTL 0x030
57 #define CM_ISPDIV 0x034
58 #define CM_V3DCTL 0x038
59 #define CM_V3DDIV 0x03c
60 #define CM_CAM0CTL 0x040
61 #define CM_CAM0DIV 0x044
62 #define CM_CAM1CTL 0x048
63 #define CM_CAM1DIV 0x04c
64 #define CM_CCP2CTL 0x050
65 #define CM_CCP2DIV 0x054
66 #define CM_DSI0ECTL 0x058
67 #define CM_DSI0EDIV 0x05c
68 #define CM_DSI0PCTL 0x060
69 #define CM_DSI0PDIV 0x064
70 #define CM_DPICTL 0x068
71 #define CM_DPIDIV 0x06c
72 #define CM_GP0CTL 0x070
73 #define CM_GP0DIV 0x074
74 #define CM_GP1CTL 0x078
75 #define CM_GP1DIV 0x07c
76 #define CM_GP2CTL 0x080
77 #define CM_GP2DIV 0x084
78 #define CM_HSMCTL 0x088
79 #define CM_HSMDIV 0x08c
80 #define CM_OTPCTL 0x090
81 #define CM_OTPDIV 0x094
82 #define CM_PCMCTL 0x098
83 #define CM_PCMDIV 0x09c
84 #define CM_PWMCTL 0x0a0
85 #define CM_PWMDIV 0x0a4
86 #define CM_SLIMCTL 0x0a8
87 #define CM_SLIMDIV 0x0ac
88 #define CM_SMICTL 0x0b0
89 #define CM_SMIDIV 0x0b4
90 /* no definition for 0x0b8 and 0x0bc */
91 #define CM_TCNTCTL 0x0c0
92 # define CM_TCNT_SRC1_SHIFT 12
93 #define CM_TCNTCNT 0x0c4
94 #define CM_TECCTL 0x0c8
95 #define CM_TECDIV 0x0cc
96 #define CM_TD0CTL 0x0d0
97 #define CM_TD0DIV 0x0d4
98 #define CM_TD1CTL 0x0d8
99 #define CM_TD1DIV 0x0dc
100 #define CM_TSENSCTL 0x0e0
101 #define CM_TSENSDIV 0x0e4
102 #define CM_TIMERCTL 0x0e8
103 #define CM_TIMERDIV 0x0ec
104 #define CM_UARTCTL 0x0f0
105 #define CM_UARTDIV 0x0f4
106 #define CM_VECCTL 0x0f8
107 #define CM_VECDIV 0x0fc
108 #define CM_PULSECTL 0x190
109 #define CM_PULSEDIV 0x194
110 #define CM_SDCCTL 0x1a8
111 #define CM_SDCDIV 0x1ac
112 #define CM_ARMCTL 0x1b0
113 #define CM_AVEOCTL 0x1b8
114 #define CM_AVEODIV 0x1bc
115 #define CM_EMMCCTL 0x1c0
116 #define CM_EMMCDIV 0x1c4
117 #define CM_EMMC2CTL 0x1d0
118 #define CM_EMMC2DIV 0x1d4
120 /* General bits for the CM_*CTL regs */
121 # define CM_ENABLE BIT(4)
122 # define CM_KILL BIT(5)
123 # define CM_GATE_BIT 6
124 # define CM_GATE BIT(CM_GATE_BIT)
125 # define CM_BUSY BIT(7)
126 # define CM_BUSYD BIT(8)
127 # define CM_FRAC BIT(9)
128 # define CM_SRC_SHIFT 0
129 # define CM_SRC_BITS 4
130 # define CM_SRC_MASK 0xf
131 # define CM_SRC_GND 0
132 # define CM_SRC_OSC 1
133 # define CM_SRC_TESTDEBUG0 2
134 # define CM_SRC_TESTDEBUG1 3
135 # define CM_SRC_PLLA_CORE 4
136 # define CM_SRC_PLLA_PER 4
137 # define CM_SRC_PLLC_CORE0 5
138 # define CM_SRC_PLLC_PER 5
139 # define CM_SRC_PLLC_CORE1 8
140 # define CM_SRC_PLLD_CORE 6
141 # define CM_SRC_PLLD_PER 6
142 # define CM_SRC_PLLH_AUX 7
143 # define CM_SRC_PLLC_CORE1 8
144 # define CM_SRC_PLLC_CORE2 9
146 #define CM_OSCCOUNT 0x100
148 #define CM_PLLA 0x104
149 # define CM_PLL_ANARST BIT(8)
150 # define CM_PLLA_HOLDPER BIT(7)
151 # define CM_PLLA_LOADPER BIT(6)
152 # define CM_PLLA_HOLDCORE BIT(5)
153 # define CM_PLLA_LOADCORE BIT(4)
154 # define CM_PLLA_HOLDCCP2 BIT(3)
155 # define CM_PLLA_LOADCCP2 BIT(2)
156 # define CM_PLLA_HOLDDSI0 BIT(1)
157 # define CM_PLLA_LOADDSI0 BIT(0)
159 #define CM_PLLC 0x108
160 # define CM_PLLC_HOLDPER BIT(7)
161 # define CM_PLLC_LOADPER BIT(6)
162 # define CM_PLLC_HOLDCORE2 BIT(5)
163 # define CM_PLLC_LOADCORE2 BIT(4)
164 # define CM_PLLC_HOLDCORE1 BIT(3)
165 # define CM_PLLC_LOADCORE1 BIT(2)
166 # define CM_PLLC_HOLDCORE0 BIT(1)
167 # define CM_PLLC_LOADCORE0 BIT(0)
169 #define CM_PLLD 0x10c
170 # define CM_PLLD_HOLDPER BIT(7)
171 # define CM_PLLD_LOADPER BIT(6)
172 # define CM_PLLD_HOLDCORE BIT(5)
173 # define CM_PLLD_LOADCORE BIT(4)
174 # define CM_PLLD_HOLDDSI1 BIT(3)
175 # define CM_PLLD_LOADDSI1 BIT(2)
176 # define CM_PLLD_HOLDDSI0 BIT(1)
177 # define CM_PLLD_LOADDSI0 BIT(0)
179 #define CM_PLLH 0x110
180 # define CM_PLLH_LOADRCAL BIT(2)
181 # define CM_PLLH_LOADAUX BIT(1)
182 # define CM_PLLH_LOADPIX BIT(0)
184 #define CM_LOCK 0x114
185 # define CM_LOCK_FLOCKH BIT(12)
186 # define CM_LOCK_FLOCKD BIT(11)
187 # define CM_LOCK_FLOCKC BIT(10)
188 # define CM_LOCK_FLOCKB BIT(9)
189 # define CM_LOCK_FLOCKA BIT(8)
191 #define CM_EVENT 0x118
192 #define CM_DSI1ECTL 0x158
193 #define CM_DSI1EDIV 0x15c
194 #define CM_DSI1PCTL 0x160
195 #define CM_DSI1PDIV 0x164
196 #define CM_DFTCTL 0x168
197 #define CM_DFTDIV 0x16c
199 #define CM_PLLB 0x170
200 # define CM_PLLB_HOLDARM BIT(1)
201 # define CM_PLLB_LOADARM BIT(0)
203 #define A2W_PLLA_CTRL 0x1100
204 #define A2W_PLLC_CTRL 0x1120
205 #define A2W_PLLD_CTRL 0x1140
206 #define A2W_PLLH_CTRL 0x1160
207 #define A2W_PLLB_CTRL 0x11e0
208 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
209 # define A2W_PLL_CTRL_PWRDN BIT(16)
210 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
211 # define A2W_PLL_CTRL_PDIV_SHIFT 12
212 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
213 # define A2W_PLL_CTRL_NDIV_SHIFT 0
215 #define A2W_PLLA_ANA0 0x1010
216 #define A2W_PLLC_ANA0 0x1030
217 #define A2W_PLLD_ANA0 0x1050
218 #define A2W_PLLH_ANA0 0x1070
219 #define A2W_PLLB_ANA0 0x10f0
221 #define A2W_PLL_KA_SHIFT 7
222 #define A2W_PLL_KA_MASK GENMASK(9, 7)
223 #define A2W_PLL_KI_SHIFT 19
224 #define A2W_PLL_KI_MASK GENMASK(21, 19)
225 #define A2W_PLL_KP_SHIFT 15
226 #define A2W_PLL_KP_MASK GENMASK(18, 15)
228 #define A2W_PLLH_KA_SHIFT 19
229 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
230 #define A2W_PLLH_KI_LOW_SHIFT 22
231 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
232 #define A2W_PLLH_KI_HIGH_SHIFT 0
233 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
234 #define A2W_PLLH_KP_SHIFT 1
235 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
237 #define A2W_XOSC_CTRL 0x1190
238 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
239 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
240 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
241 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
242 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
243 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
244 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
245 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
247 #define A2W_PLLA_FRAC 0x1200
248 #define A2W_PLLC_FRAC 0x1220
249 #define A2W_PLLD_FRAC 0x1240
250 #define A2W_PLLH_FRAC 0x1260
251 #define A2W_PLLB_FRAC 0x12e0
252 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
253 # define A2W_PLL_FRAC_BITS 20
255 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
256 #define A2W_PLL_DIV_BITS 8
257 #define A2W_PLL_DIV_SHIFT 0
259 #define A2W_PLLA_DSI0 0x1300
260 #define A2W_PLLA_CORE 0x1400
261 #define A2W_PLLA_PER 0x1500
262 #define A2W_PLLA_CCP2 0x1600
264 #define A2W_PLLC_CORE2 0x1320
265 #define A2W_PLLC_CORE1 0x1420
266 #define A2W_PLLC_PER 0x1520
267 #define A2W_PLLC_CORE0 0x1620
269 #define A2W_PLLD_DSI0 0x1340
270 #define A2W_PLLD_CORE 0x1440
271 #define A2W_PLLD_PER 0x1540
272 #define A2W_PLLD_DSI1 0x1640
274 #define A2W_PLLH_AUX 0x1360
275 #define A2W_PLLH_RCAL 0x1460
276 #define A2W_PLLH_PIX 0x1560
277 #define A2W_PLLH_STS 0x1660
279 #define A2W_PLLH_CTRLR 0x1960
280 #define A2W_PLLH_FRACR 0x1a60
281 #define A2W_PLLH_AUXR 0x1b60
282 #define A2W_PLLH_RCALR 0x1c60
283 #define A2W_PLLH_PIXR 0x1d60
284 #define A2W_PLLH_STSR 0x1e60
286 #define A2W_PLLB_ARM 0x13e0
287 #define A2W_PLLB_SP0 0x14e0
288 #define A2W_PLLB_SP1 0x15e0
289 #define A2W_PLLB_SP2 0x16e0
291 #define LOCK_TIMEOUT_NS 100000000
292 #define BCM2835_MAX_FB_RATE 1750000000u
294 #define SOC_BCM2835 BIT(0)
295 #define SOC_BCM2711 BIT(1)
296 #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
299 * Names of clocks used within the driver that need to be replaced
300 * with an external parent's name. This array is in the order that
301 * the clocks node in the DT references external clocks.
303 static const char *const cprman_parent_names[] = {
304 "xosc",
305 "dsi0_byte",
306 "dsi0_ddr2",
307 "dsi0_ddr",
308 "dsi1_byte",
309 "dsi1_ddr2",
310 "dsi1_ddr",
313 struct bcm2835_cprman {
314 struct device *dev;
315 void __iomem *regs;
316 spinlock_t regs_lock; /* spinlock for all clocks */
317 unsigned int soc;
320 * Real names of cprman clock parents looked up through
321 * of_clk_get_parent_name(), which will be used in the
322 * parent_names[] arrays for clock registration.
324 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
326 /* Must be last */
327 struct clk_hw_onecell_data onecell;
330 struct cprman_plat_data {
331 unsigned int soc;
334 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
336 writel(CM_PASSWORD | val, cprman->regs + reg);
339 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
341 return readl(cprman->regs + reg);
344 /* Does a cycle of measuring a clock through the TCNT clock, which may
345 * source from many other clocks in the system.
347 static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
348 u32 tcnt_mux)
350 u32 osccount = 19200; /* 1ms */
351 u32 count;
352 ktime_t timeout;
354 spin_lock(&cprman->regs_lock);
356 cprman_write(cprman, CM_TCNTCTL, CM_KILL);
358 cprman_write(cprman, CM_TCNTCTL,
359 (tcnt_mux & CM_SRC_MASK) |
360 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
362 cprman_write(cprman, CM_OSCCOUNT, osccount);
364 /* do a kind delay at the start */
365 mdelay(1);
367 /* Finish off whatever is left of OSCCOUNT */
368 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
369 while (cprman_read(cprman, CM_OSCCOUNT)) {
370 if (ktime_after(ktime_get(), timeout)) {
371 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
372 count = 0;
373 goto out;
375 cpu_relax();
378 /* Wait for BUSY to clear. */
379 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
380 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
381 if (ktime_after(ktime_get(), timeout)) {
382 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
383 count = 0;
384 goto out;
386 cpu_relax();
389 count = cprman_read(cprman, CM_TCNTCNT);
391 cprman_write(cprman, CM_TCNTCTL, 0);
393 out:
394 spin_unlock(&cprman->regs_lock);
396 return count * 1000;
399 static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
400 const struct debugfs_reg32 *regs,
401 size_t nregs, struct dentry *dentry)
403 struct debugfs_regset32 *regset;
405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
406 if (!regset)
407 return;
409 regset->regs = regs;
410 regset->nregs = nregs;
411 regset->base = cprman->regs + base;
413 debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
416 struct bcm2835_pll_data {
417 const char *name;
418 u32 cm_ctrl_reg;
419 u32 a2w_ctrl_reg;
420 u32 frac_reg;
421 u32 ana_reg_base;
422 u32 reference_enable_mask;
423 /* Bit in CM_LOCK to indicate when the PLL has locked. */
424 u32 lock_mask;
425 u32 flags;
427 const struct bcm2835_pll_ana_bits *ana;
429 unsigned long min_rate;
430 unsigned long max_rate;
432 * Highest rate for the VCO before we have to use the
433 * pre-divide-by-2.
435 unsigned long max_fb_rate;
438 struct bcm2835_pll_ana_bits {
439 u32 mask0;
440 u32 set0;
441 u32 mask1;
442 u32 set1;
443 u32 mask3;
444 u32 set3;
445 u32 fb_prediv_mask;
448 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
449 .mask0 = 0,
450 .set0 = 0,
451 .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
452 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
453 .mask3 = A2W_PLL_KA_MASK,
454 .set3 = (2 << A2W_PLL_KA_SHIFT),
455 .fb_prediv_mask = BIT(14),
458 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
459 .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
460 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
461 .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
462 .set1 = (6 << A2W_PLLH_KP_SHIFT),
463 .mask3 = 0,
464 .set3 = 0,
465 .fb_prediv_mask = BIT(11),
468 struct bcm2835_pll_divider_data {
469 const char *name;
470 const char *source_pll;
472 u32 cm_reg;
473 u32 a2w_reg;
475 u32 load_mask;
476 u32 hold_mask;
477 u32 fixed_divider;
478 u32 flags;
481 struct bcm2835_clock_data {
482 const char *name;
484 const char *const *parents;
485 int num_mux_parents;
487 /* Bitmap encoding which parents accept rate change propagation. */
488 unsigned int set_rate_parent;
490 u32 ctl_reg;
491 u32 div_reg;
493 /* Number of integer bits in the divider */
494 u32 int_bits;
495 /* Number of fractional bits in the divider */
496 u32 frac_bits;
498 u32 flags;
500 bool is_vpu_clock;
501 bool is_mash_clock;
502 bool low_jitter;
504 u32 tcnt_mux;
507 struct bcm2835_gate_data {
508 const char *name;
509 const char *parent;
511 u32 ctl_reg;
514 struct bcm2835_pll {
515 struct clk_hw hw;
516 struct bcm2835_cprman *cprman;
517 const struct bcm2835_pll_data *data;
520 static int bcm2835_pll_is_on(struct clk_hw *hw)
522 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
523 struct bcm2835_cprman *cprman = pll->cprman;
524 const struct bcm2835_pll_data *data = pll->data;
526 return cprman_read(cprman, data->a2w_ctrl_reg) &
527 A2W_PLL_CTRL_PRST_DISABLE;
530 static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,
531 const struct bcm2835_pll_data *data)
534 * On BCM2711 there isn't a pre-divisor available in the PLL feedback
535 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed
536 * for to for VCO RANGE bits.
538 if (cprman->soc & SOC_BCM2711)
539 return 0;
541 return data->ana->fb_prediv_mask;
544 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
545 unsigned long parent_rate,
546 u32 *ndiv, u32 *fdiv)
548 u64 div;
550 div = (u64)rate << A2W_PLL_FRAC_BITS;
551 do_div(div, parent_rate);
553 *ndiv = div >> A2W_PLL_FRAC_BITS;
554 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
557 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
558 u32 ndiv, u32 fdiv, u32 pdiv)
560 u64 rate;
562 if (pdiv == 0)
563 return 0;
565 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
566 do_div(rate, pdiv);
567 return rate >> A2W_PLL_FRAC_BITS;
570 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
571 unsigned long *parent_rate)
573 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
574 const struct bcm2835_pll_data *data = pll->data;
575 u32 ndiv, fdiv;
577 rate = clamp(rate, data->min_rate, data->max_rate);
579 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
581 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
584 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
585 unsigned long parent_rate)
587 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
588 struct bcm2835_cprman *cprman = pll->cprman;
589 const struct bcm2835_pll_data *data = pll->data;
590 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
591 u32 ndiv, pdiv, fdiv;
592 bool using_prediv;
594 if (parent_rate == 0)
595 return 0;
597 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
598 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
599 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
600 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
601 bcm2835_pll_get_prediv_mask(cprman, data);
603 if (using_prediv) {
604 ndiv *= 2;
605 fdiv *= 2;
608 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
611 static void bcm2835_pll_off(struct clk_hw *hw)
613 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
614 struct bcm2835_cprman *cprman = pll->cprman;
615 const struct bcm2835_pll_data *data = pll->data;
617 spin_lock(&cprman->regs_lock);
618 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
619 cprman_write(cprman, data->a2w_ctrl_reg,
620 cprman_read(cprman, data->a2w_ctrl_reg) |
621 A2W_PLL_CTRL_PWRDN);
622 spin_unlock(&cprman->regs_lock);
625 static int bcm2835_pll_on(struct clk_hw *hw)
627 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
628 struct bcm2835_cprman *cprman = pll->cprman;
629 const struct bcm2835_pll_data *data = pll->data;
630 ktime_t timeout;
632 cprman_write(cprman, data->a2w_ctrl_reg,
633 cprman_read(cprman, data->a2w_ctrl_reg) &
634 ~A2W_PLL_CTRL_PWRDN);
636 /* Take the PLL out of reset. */
637 spin_lock(&cprman->regs_lock);
638 cprman_write(cprman, data->cm_ctrl_reg,
639 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
640 spin_unlock(&cprman->regs_lock);
642 /* Wait for the PLL to lock. */
643 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
644 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
645 if (ktime_after(ktime_get(), timeout)) {
646 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
647 clk_hw_get_name(hw));
648 return -ETIMEDOUT;
651 cpu_relax();
654 cprman_write(cprman, data->a2w_ctrl_reg,
655 cprman_read(cprman, data->a2w_ctrl_reg) |
656 A2W_PLL_CTRL_PRST_DISABLE);
658 return 0;
661 static void
662 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
664 int i;
667 * ANA register setup is done as a series of writes to
668 * ANA3-ANA0, in that order. This lets us write all 4
669 * registers as a single cycle of the serdes interface (taking
670 * 100 xosc clocks), whereas if we were to update ana0, 1, and
671 * 3 individually through their partial-write registers, each
672 * would be their own serdes cycle.
674 for (i = 3; i >= 0; i--)
675 cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
678 static int bcm2835_pll_set_rate(struct clk_hw *hw,
679 unsigned long rate, unsigned long parent_rate)
681 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
682 struct bcm2835_cprman *cprman = pll->cprman;
683 const struct bcm2835_pll_data *data = pll->data;
684 u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data);
685 bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
686 u32 ndiv, fdiv, a2w_ctl;
687 u32 ana[4];
688 int i;
690 if (rate > data->max_fb_rate) {
691 use_fb_prediv = true;
692 rate /= 2;
693 } else {
694 use_fb_prediv = false;
697 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
699 for (i = 3; i >= 0; i--)
700 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
702 was_using_prediv = ana[1] & prediv_mask;
704 ana[0] &= ~data->ana->mask0;
705 ana[0] |= data->ana->set0;
706 ana[1] &= ~data->ana->mask1;
707 ana[1] |= data->ana->set1;
708 ana[3] &= ~data->ana->mask3;
709 ana[3] |= data->ana->set3;
711 if (was_using_prediv && !use_fb_prediv) {
712 ana[1] &= ~prediv_mask;
713 do_ana_setup_first = true;
714 } else if (!was_using_prediv && use_fb_prediv) {
715 ana[1] |= prediv_mask;
716 do_ana_setup_first = false;
717 } else {
718 do_ana_setup_first = true;
721 /* Unmask the reference clock from the oscillator. */
722 spin_lock(&cprman->regs_lock);
723 cprman_write(cprman, A2W_XOSC_CTRL,
724 cprman_read(cprman, A2W_XOSC_CTRL) |
725 data->reference_enable_mask);
726 spin_unlock(&cprman->regs_lock);
728 if (do_ana_setup_first)
729 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
731 /* Set the PLL multiplier from the oscillator. */
732 cprman_write(cprman, data->frac_reg, fdiv);
734 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
735 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
736 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
737 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
738 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
739 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
741 if (!do_ana_setup_first)
742 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
744 return 0;
747 static void bcm2835_pll_debug_init(struct clk_hw *hw,
748 struct dentry *dentry)
750 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
751 struct bcm2835_cprman *cprman = pll->cprman;
752 const struct bcm2835_pll_data *data = pll->data;
753 struct debugfs_reg32 *regs;
755 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
756 if (!regs)
757 return;
759 regs[0].name = "cm_ctrl";
760 regs[0].offset = data->cm_ctrl_reg;
761 regs[1].name = "a2w_ctrl";
762 regs[1].offset = data->a2w_ctrl_reg;
763 regs[2].name = "frac";
764 regs[2].offset = data->frac_reg;
765 regs[3].name = "ana0";
766 regs[3].offset = data->ana_reg_base + 0 * 4;
767 regs[4].name = "ana1";
768 regs[4].offset = data->ana_reg_base + 1 * 4;
769 regs[5].name = "ana2";
770 regs[5].offset = data->ana_reg_base + 2 * 4;
771 regs[6].name = "ana3";
772 regs[6].offset = data->ana_reg_base + 3 * 4;
774 bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
777 static const struct clk_ops bcm2835_pll_clk_ops = {
778 .is_prepared = bcm2835_pll_is_on,
779 .prepare = bcm2835_pll_on,
780 .unprepare = bcm2835_pll_off,
781 .recalc_rate = bcm2835_pll_get_rate,
782 .set_rate = bcm2835_pll_set_rate,
783 .round_rate = bcm2835_pll_round_rate,
784 .debug_init = bcm2835_pll_debug_init,
787 struct bcm2835_pll_divider {
788 struct clk_divider div;
789 struct bcm2835_cprman *cprman;
790 const struct bcm2835_pll_divider_data *data;
793 static struct bcm2835_pll_divider *
794 bcm2835_pll_divider_from_hw(struct clk_hw *hw)
796 return container_of(hw, struct bcm2835_pll_divider, div.hw);
799 static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
801 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
802 struct bcm2835_cprman *cprman = divider->cprman;
803 const struct bcm2835_pll_divider_data *data = divider->data;
805 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
808 static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
809 unsigned long rate,
810 unsigned long *parent_rate)
812 return clk_divider_ops.round_rate(hw, rate, parent_rate);
815 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
816 unsigned long parent_rate)
818 return clk_divider_ops.recalc_rate(hw, parent_rate);
821 static void bcm2835_pll_divider_off(struct clk_hw *hw)
823 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
824 struct bcm2835_cprman *cprman = divider->cprman;
825 const struct bcm2835_pll_divider_data *data = divider->data;
827 spin_lock(&cprman->regs_lock);
828 cprman_write(cprman, data->cm_reg,
829 (cprman_read(cprman, data->cm_reg) &
830 ~data->load_mask) | data->hold_mask);
831 cprman_write(cprman, data->a2w_reg,
832 cprman_read(cprman, data->a2w_reg) |
833 A2W_PLL_CHANNEL_DISABLE);
834 spin_unlock(&cprman->regs_lock);
837 static int bcm2835_pll_divider_on(struct clk_hw *hw)
839 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
840 struct bcm2835_cprman *cprman = divider->cprman;
841 const struct bcm2835_pll_divider_data *data = divider->data;
843 spin_lock(&cprman->regs_lock);
844 cprman_write(cprman, data->a2w_reg,
845 cprman_read(cprman, data->a2w_reg) &
846 ~A2W_PLL_CHANNEL_DISABLE);
848 cprman_write(cprman, data->cm_reg,
849 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
850 spin_unlock(&cprman->regs_lock);
852 return 0;
855 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
856 unsigned long rate,
857 unsigned long parent_rate)
859 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
860 struct bcm2835_cprman *cprman = divider->cprman;
861 const struct bcm2835_pll_divider_data *data = divider->data;
862 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
864 div = DIV_ROUND_UP_ULL(parent_rate, rate);
866 div = min(div, max_div);
867 if (div == max_div)
868 div = 0;
870 cprman_write(cprman, data->a2w_reg, div);
871 cm = cprman_read(cprman, data->cm_reg);
872 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
873 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
875 return 0;
878 static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
879 struct dentry *dentry)
881 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
882 struct bcm2835_cprman *cprman = divider->cprman;
883 const struct bcm2835_pll_divider_data *data = divider->data;
884 struct debugfs_reg32 *regs;
886 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
887 if (!regs)
888 return;
890 regs[0].name = "cm";
891 regs[0].offset = data->cm_reg;
892 regs[1].name = "a2w";
893 regs[1].offset = data->a2w_reg;
895 bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
898 static const struct clk_ops bcm2835_pll_divider_clk_ops = {
899 .is_prepared = bcm2835_pll_divider_is_on,
900 .prepare = bcm2835_pll_divider_on,
901 .unprepare = bcm2835_pll_divider_off,
902 .recalc_rate = bcm2835_pll_divider_get_rate,
903 .set_rate = bcm2835_pll_divider_set_rate,
904 .round_rate = bcm2835_pll_divider_round_rate,
905 .debug_init = bcm2835_pll_divider_debug_init,
909 * The CM dividers do fixed-point division, so we can't use the
910 * generic integer divider code like the PLL dividers do (and we can't
911 * fake it by having some fixed shifts preceding it in the clock tree,
912 * because we'd run out of bits in a 32-bit unsigned long).
914 struct bcm2835_clock {
915 struct clk_hw hw;
916 struct bcm2835_cprman *cprman;
917 const struct bcm2835_clock_data *data;
920 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
922 return container_of(hw, struct bcm2835_clock, hw);
925 static int bcm2835_clock_is_on(struct clk_hw *hw)
927 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
928 struct bcm2835_cprman *cprman = clock->cprman;
929 const struct bcm2835_clock_data *data = clock->data;
931 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
934 static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
935 unsigned long rate,
936 unsigned long parent_rate,
937 bool round_up)
939 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
940 const struct bcm2835_clock_data *data = clock->data;
941 u32 unused_frac_mask =
942 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
943 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
944 u64 rem;
945 u32 div, mindiv, maxdiv;
947 rem = do_div(temp, rate);
948 div = temp;
950 /* Round up and mask off the unused bits */
951 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0))
952 div += unused_frac_mask + 1;
953 div &= ~unused_frac_mask;
955 /* different clamping limits apply for a mash clock */
956 if (data->is_mash_clock) {
957 /* clamp to min divider of 2 */
958 mindiv = 2 << CM_DIV_FRAC_BITS;
959 /* clamp to the highest possible integer divider */
960 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
961 } else {
962 /* clamp to min divider of 1 */
963 mindiv = 1 << CM_DIV_FRAC_BITS;
964 /* clamp to the highest possible fractional divider */
965 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
966 CM_DIV_FRAC_BITS - data->frac_bits);
969 /* apply the clamping limits */
970 div = max_t(u32, div, mindiv);
971 div = min_t(u32, div, maxdiv);
973 return div;
976 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
977 unsigned long parent_rate,
978 u32 div)
980 const struct bcm2835_clock_data *data = clock->data;
981 u64 temp;
983 if (data->int_bits == 0 && data->frac_bits == 0)
984 return parent_rate;
987 * The divisor is a 12.12 fixed point field, but only some of
988 * the bits are populated in any given clock.
990 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
991 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
993 if (div == 0)
994 return 0;
996 temp = (u64)parent_rate << data->frac_bits;
998 do_div(temp, div);
1000 return temp;
1003 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
1004 unsigned long parent_rate)
1006 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1007 struct bcm2835_cprman *cprman = clock->cprman;
1008 const struct bcm2835_clock_data *data = clock->data;
1009 u32 div;
1011 if (data->int_bits == 0 && data->frac_bits == 0)
1012 return parent_rate;
1014 div = cprman_read(cprman, data->div_reg);
1016 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1019 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1021 struct bcm2835_cprman *cprman = clock->cprman;
1022 const struct bcm2835_clock_data *data = clock->data;
1023 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
1025 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1026 if (ktime_after(ktime_get(), timeout)) {
1027 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1028 clk_hw_get_name(&clock->hw));
1029 return;
1031 cpu_relax();
1035 static void bcm2835_clock_off(struct clk_hw *hw)
1037 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1038 struct bcm2835_cprman *cprman = clock->cprman;
1039 const struct bcm2835_clock_data *data = clock->data;
1041 spin_lock(&cprman->regs_lock);
1042 cprman_write(cprman, data->ctl_reg,
1043 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1044 spin_unlock(&cprman->regs_lock);
1046 /* BUSY will remain high until the divider completes its cycle. */
1047 bcm2835_clock_wait_busy(clock);
1050 static int bcm2835_clock_on(struct clk_hw *hw)
1052 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1053 struct bcm2835_cprman *cprman = clock->cprman;
1054 const struct bcm2835_clock_data *data = clock->data;
1056 spin_lock(&cprman->regs_lock);
1057 cprman_write(cprman, data->ctl_reg,
1058 cprman_read(cprman, data->ctl_reg) |
1059 CM_ENABLE |
1060 CM_GATE);
1061 spin_unlock(&cprman->regs_lock);
1063 /* Debug code to measure the clock once it's turned on to see
1064 * if it's ticking at the rate we expect.
1066 if (data->tcnt_mux && false) {
1067 dev_info(cprman->dev,
1068 "clk %s: rate %ld, measure %ld\n",
1069 data->name,
1070 clk_hw_get_rate(hw),
1071 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1074 return 0;
1077 static int bcm2835_clock_set_rate(struct clk_hw *hw,
1078 unsigned long rate, unsigned long parent_rate)
1080 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1081 struct bcm2835_cprman *cprman = clock->cprman;
1082 const struct bcm2835_clock_data *data = clock->data;
1083 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false);
1084 u32 ctl;
1086 spin_lock(&cprman->regs_lock);
1089 * Setting up frac support
1091 * In principle it is recommended to stop/start the clock first,
1092 * but as we set CLK_SET_RATE_GATE during registration of the
1093 * clock this requirement should be take care of by the
1094 * clk-framework.
1096 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1097 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
1098 cprman_write(cprman, data->ctl_reg, ctl);
1100 cprman_write(cprman, data->div_reg, div);
1102 spin_unlock(&cprman->regs_lock);
1104 return 0;
1107 static bool
1108 bcm2835_clk_is_pllc(struct clk_hw *hw)
1110 if (!hw)
1111 return false;
1113 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
1116 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
1117 int parent_idx,
1118 unsigned long rate,
1119 u32 *div,
1120 unsigned long *prate,
1121 unsigned long *avgrate)
1123 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1124 struct bcm2835_cprman *cprman = clock->cprman;
1125 const struct bcm2835_clock_data *data = clock->data;
1126 unsigned long best_rate = 0;
1127 u32 curdiv, mindiv, maxdiv;
1128 struct clk_hw *parent;
1130 parent = clk_hw_get_parent_by_index(hw, parent_idx);
1132 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1133 *prate = clk_hw_get_rate(parent);
1134 *div = bcm2835_clock_choose_div(hw, rate, *prate, true);
1136 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1138 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1139 unsigned long high, low;
1140 u32 int_div = *div & ~CM_DIV_FRAC_MASK;
1142 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1143 int_div);
1144 int_div += CM_DIV_FRAC_MASK + 1;
1145 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1146 int_div);
1149 * Return a value which is the maximum deviation
1150 * below the ideal rate, for use as a metric.
1152 return *avgrate - max(*avgrate - low, high - *avgrate);
1154 return *avgrate;
1157 if (data->frac_bits)
1158 dev_warn(cprman->dev,
1159 "frac bits are not used when propagating rate change");
1161 /* clamp to min divider of 2 if we're dealing with a mash clock */
1162 mindiv = data->is_mash_clock ? 2 : 1;
1163 maxdiv = BIT(data->int_bits) - 1;
1165 /* TODO: Be smart, and only test a subset of the available divisors. */
1166 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
1167 unsigned long tmp_rate;
1169 tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
1170 tmp_rate /= curdiv;
1171 if (curdiv == mindiv ||
1172 (tmp_rate > best_rate && tmp_rate <= rate))
1173 best_rate = tmp_rate;
1175 if (best_rate == rate)
1176 break;
1179 *div = curdiv << CM_DIV_FRAC_BITS;
1180 *prate = curdiv * best_rate;
1181 *avgrate = best_rate;
1183 return best_rate;
1186 static int bcm2835_clock_determine_rate(struct clk_hw *hw,
1187 struct clk_rate_request *req)
1189 struct clk_hw *parent, *best_parent = NULL;
1190 bool current_parent_is_pllc;
1191 unsigned long rate, best_rate = 0;
1192 unsigned long prate, best_prate = 0;
1193 unsigned long avgrate, best_avgrate = 0;
1194 size_t i;
1195 u32 div;
1197 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
1200 * Select parent clock that results in the closest but lower rate
1202 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
1203 parent = clk_hw_get_parent_by_index(hw, i);
1204 if (!parent)
1205 continue;
1208 * Don't choose a PLLC-derived clock as our parent
1209 * unless it had been manually set that way. PLLC's
1210 * frequency gets adjusted by the firmware due to
1211 * over-temp or under-voltage conditions, without
1212 * prior notification to our clock consumer.
1214 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
1215 continue;
1217 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1218 &div, &prate,
1219 &avgrate);
1220 if (rate > best_rate && rate <= req->rate) {
1221 best_parent = parent;
1222 best_prate = prate;
1223 best_rate = rate;
1224 best_avgrate = avgrate;
1228 if (!best_parent)
1229 return -EINVAL;
1231 req->best_parent_hw = best_parent;
1232 req->best_parent_rate = best_prate;
1234 req->rate = best_avgrate;
1236 return 0;
1239 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
1241 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1242 struct bcm2835_cprman *cprman = clock->cprman;
1243 const struct bcm2835_clock_data *data = clock->data;
1244 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
1246 cprman_write(cprman, data->ctl_reg, src);
1247 return 0;
1250 static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
1252 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1253 struct bcm2835_cprman *cprman = clock->cprman;
1254 const struct bcm2835_clock_data *data = clock->data;
1255 u32 src = cprman_read(cprman, data->ctl_reg);
1257 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
1260 static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1262 .name = "ctl",
1263 .offset = 0,
1266 .name = "div",
1267 .offset = 4,
1271 static void bcm2835_clock_debug_init(struct clk_hw *hw,
1272 struct dentry *dentry)
1274 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1275 struct bcm2835_cprman *cprman = clock->cprman;
1276 const struct bcm2835_clock_data *data = clock->data;
1278 bcm2835_debugfs_regset(cprman, data->ctl_reg,
1279 bcm2835_debugfs_clock_reg32,
1280 ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
1281 dentry);
1284 static const struct clk_ops bcm2835_clock_clk_ops = {
1285 .is_prepared = bcm2835_clock_is_on,
1286 .prepare = bcm2835_clock_on,
1287 .unprepare = bcm2835_clock_off,
1288 .recalc_rate = bcm2835_clock_get_rate,
1289 .set_rate = bcm2835_clock_set_rate,
1290 .determine_rate = bcm2835_clock_determine_rate,
1291 .set_parent = bcm2835_clock_set_parent,
1292 .get_parent = bcm2835_clock_get_parent,
1293 .debug_init = bcm2835_clock_debug_init,
1296 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
1298 return true;
1302 * The VPU clock can never be disabled (it doesn't have an ENABLE
1303 * bit), so it gets its own set of clock ops.
1305 static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
1306 .is_prepared = bcm2835_vpu_clock_is_on,
1307 .recalc_rate = bcm2835_clock_get_rate,
1308 .set_rate = bcm2835_clock_set_rate,
1309 .determine_rate = bcm2835_clock_determine_rate,
1310 .set_parent = bcm2835_clock_set_parent,
1311 .get_parent = bcm2835_clock_get_parent,
1312 .debug_init = bcm2835_clock_debug_init,
1315 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1316 const void *data)
1318 const struct bcm2835_pll_data *pll_data = data;
1319 struct bcm2835_pll *pll;
1320 struct clk_init_data init;
1321 int ret;
1323 memset(&init, 0, sizeof(init));
1325 /* All of the PLLs derive from the external oscillator. */
1326 init.parent_names = &cprman->real_parent_names[0];
1327 init.num_parents = 1;
1328 init.name = pll_data->name;
1329 init.ops = &bcm2835_pll_clk_ops;
1330 init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
1332 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1333 if (!pll)
1334 return NULL;
1336 pll->cprman = cprman;
1337 pll->data = pll_data;
1338 pll->hw.init = &init;
1340 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1341 if (ret) {
1342 kfree(pll);
1343 return NULL;
1345 return &pll->hw;
1348 static struct clk_hw *
1349 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1350 const void *data)
1352 const struct bcm2835_pll_divider_data *divider_data = data;
1353 struct bcm2835_pll_divider *divider;
1354 struct clk_init_data init;
1355 const char *divider_name;
1356 int ret;
1358 if (divider_data->fixed_divider != 1) {
1359 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1360 "%s_prediv", divider_data->name);
1361 if (!divider_name)
1362 return NULL;
1363 } else {
1364 divider_name = divider_data->name;
1367 memset(&init, 0, sizeof(init));
1369 init.parent_names = &divider_data->source_pll;
1370 init.num_parents = 1;
1371 init.name = divider_name;
1372 init.ops = &bcm2835_pll_divider_clk_ops;
1373 init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1375 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1376 if (!divider)
1377 return NULL;
1379 divider->div.reg = cprman->regs + divider_data->a2w_reg;
1380 divider->div.shift = A2W_PLL_DIV_SHIFT;
1381 divider->div.width = A2W_PLL_DIV_BITS;
1382 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1383 divider->div.lock = &cprman->regs_lock;
1384 divider->div.hw.init = &init;
1385 divider->div.table = NULL;
1387 divider->cprman = cprman;
1388 divider->data = divider_data;
1390 ret = devm_clk_hw_register(cprman->dev, &divider->div.hw);
1391 if (ret)
1392 return ERR_PTR(ret);
1395 * PLLH's channels have a fixed divide by 10 afterwards, which
1396 * is what our consumers are actually using.
1398 if (divider_data->fixed_divider != 1) {
1399 return clk_hw_register_fixed_factor(cprman->dev,
1400 divider_data->name,
1401 divider_name,
1402 CLK_SET_RATE_PARENT,
1404 divider_data->fixed_divider);
1407 return &divider->div.hw;
1410 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1411 const void *data)
1413 const struct bcm2835_clock_data *clock_data = data;
1414 struct bcm2835_clock *clock;
1415 struct clk_init_data init;
1416 const char *parents[1 << CM_SRC_BITS];
1417 size_t i;
1418 int ret;
1421 * Replace our strings referencing parent clocks with the
1422 * actual clock-output-name of the parent.
1424 for (i = 0; i < clock_data->num_mux_parents; i++) {
1425 parents[i] = clock_data->parents[i];
1427 ret = match_string(cprman_parent_names,
1428 ARRAY_SIZE(cprman_parent_names),
1429 parents[i]);
1430 if (ret >= 0)
1431 parents[i] = cprman->real_parent_names[ret];
1434 memset(&init, 0, sizeof(init));
1435 init.parent_names = parents;
1436 init.num_parents = clock_data->num_mux_parents;
1437 init.name = clock_data->name;
1438 init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1441 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
1442 * rate changes on at least of the parents.
1444 if (clock_data->set_rate_parent)
1445 init.flags |= CLK_SET_RATE_PARENT;
1447 if (clock_data->is_vpu_clock) {
1448 init.ops = &bcm2835_vpu_clock_clk_ops;
1449 } else {
1450 init.ops = &bcm2835_clock_clk_ops;
1451 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1453 /* If the clock wasn't actually enabled at boot, it's not
1454 * critical.
1456 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
1457 init.flags &= ~CLK_IS_CRITICAL;
1460 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1461 if (!clock)
1462 return NULL;
1464 clock->cprman = cprman;
1465 clock->data = clock_data;
1466 clock->hw.init = &init;
1468 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1469 if (ret)
1470 return ERR_PTR(ret);
1471 return &clock->hw;
1474 static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1475 const void *data)
1477 const struct bcm2835_gate_data *gate_data = data;
1479 return clk_hw_register_gate(cprman->dev, gate_data->name,
1480 gate_data->parent,
1481 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1482 cprman->regs + gate_data->ctl_reg,
1483 CM_GATE_BIT, 0, &cprman->regs_lock);
1486 struct bcm2835_clk_desc {
1487 struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,
1488 const void *data);
1489 unsigned int supported;
1490 const void *data;
1493 /* assignment helper macros for different clock types */
1494 #define _REGISTER(f, s, ...) { .clk_register = f, \
1495 .supported = s, \
1496 .data = __VA_ARGS__ }
1497 #define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \
1498 s, \
1499 &(struct bcm2835_pll_data) \
1500 {__VA_ARGS__})
1501 #define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
1502 s, \
1503 &(struct bcm2835_pll_divider_data) \
1504 {__VA_ARGS__})
1505 #define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \
1506 s, \
1507 &(struct bcm2835_clock_data) \
1508 {__VA_ARGS__})
1509 #define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \
1510 s, \
1511 &(struct bcm2835_gate_data) \
1512 {__VA_ARGS__})
1514 /* parent mux arrays plus helper macros */
1516 /* main oscillator parent mux */
1517 static const char *const bcm2835_clock_osc_parents[] = {
1518 "gnd",
1519 "xosc",
1520 "testdebug0",
1521 "testdebug1"
1524 #define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \
1525 s, \
1526 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1527 .parents = bcm2835_clock_osc_parents, \
1528 __VA_ARGS__)
1530 /* main peripherial parent mux */
1531 static const char *const bcm2835_clock_per_parents[] = {
1532 "gnd",
1533 "xosc",
1534 "testdebug0",
1535 "testdebug1",
1536 "plla_per",
1537 "pllc_per",
1538 "plld_per",
1539 "pllh_aux",
1542 #define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \
1543 s, \
1544 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1545 .parents = bcm2835_clock_per_parents, \
1546 __VA_ARGS__)
1549 * Restrict clock sources for the PCM peripheral to the oscillator and
1550 * PLLD_PER because other source may have varying rates or be switched
1551 * off.
1553 * Prevent other sources from being selected by replacing their names in
1554 * the list of potential parents with dummy entries (entry index is
1555 * significant).
1557 static const char *const bcm2835_pcm_per_parents[] = {
1558 "-",
1559 "xosc",
1560 "-",
1561 "-",
1562 "-",
1563 "-",
1564 "plld_per",
1565 "-",
1568 #define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \
1569 s, \
1570 .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
1571 .parents = bcm2835_pcm_per_parents, \
1572 __VA_ARGS__)
1574 /* main vpu parent mux */
1575 static const char *const bcm2835_clock_vpu_parents[] = {
1576 "gnd",
1577 "xosc",
1578 "testdebug0",
1579 "testdebug1",
1580 "plla_core",
1581 "pllc_core0",
1582 "plld_core",
1583 "pllh_aux",
1584 "pllc_core1",
1585 "pllc_core2",
1588 #define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \
1589 s, \
1590 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1591 .parents = bcm2835_clock_vpu_parents, \
1592 __VA_ARGS__)
1595 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
1596 * analog PHY. The _inv variants are generated internally to cprman,
1597 * but we don't use them so they aren't hooked up.
1599 static const char *const bcm2835_clock_dsi0_parents[] = {
1600 "gnd",
1601 "xosc",
1602 "testdebug0",
1603 "testdebug1",
1604 "dsi0_ddr",
1605 "dsi0_ddr_inv",
1606 "dsi0_ddr2",
1607 "dsi0_ddr2_inv",
1608 "dsi0_byte",
1609 "dsi0_byte_inv",
1612 static const char *const bcm2835_clock_dsi1_parents[] = {
1613 "gnd",
1614 "xosc",
1615 "testdebug0",
1616 "testdebug1",
1617 "dsi1_ddr",
1618 "dsi1_ddr_inv",
1619 "dsi1_ddr2",
1620 "dsi1_ddr2_inv",
1621 "dsi1_byte",
1622 "dsi1_byte_inv",
1625 #define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \
1626 s, \
1627 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
1628 .parents = bcm2835_clock_dsi0_parents, \
1629 __VA_ARGS__)
1631 #define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \
1632 s, \
1633 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
1634 .parents = bcm2835_clock_dsi1_parents, \
1635 __VA_ARGS__)
1638 * the real definition of all the pll, pll_dividers and clocks
1639 * these make use of the above REGISTER_* macros
1641 static const struct bcm2835_clk_desc clk_desc_array[] = {
1642 /* the PLL + PLL dividers */
1645 * PLLA is the auxiliary PLL, used to drive the CCP2
1646 * (Compact Camera Port 2) transmitter clock.
1648 * It is in the PX LDO power domain, which is on when the
1649 * AUDIO domain is on.
1651 [BCM2835_PLLA] = REGISTER_PLL(
1652 SOC_ALL,
1653 .name = "plla",
1654 .cm_ctrl_reg = CM_PLLA,
1655 .a2w_ctrl_reg = A2W_PLLA_CTRL,
1656 .frac_reg = A2W_PLLA_FRAC,
1657 .ana_reg_base = A2W_PLLA_ANA0,
1658 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
1659 .lock_mask = CM_LOCK_FLOCKA,
1661 .ana = &bcm2835_ana_default,
1663 .min_rate = 600000000u,
1664 .max_rate = 2400000000u,
1665 .max_fb_rate = BCM2835_MAX_FB_RATE),
1666 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
1667 SOC_ALL,
1668 .name = "plla_core",
1669 .source_pll = "plla",
1670 .cm_reg = CM_PLLA,
1671 .a2w_reg = A2W_PLLA_CORE,
1672 .load_mask = CM_PLLA_LOADCORE,
1673 .hold_mask = CM_PLLA_HOLDCORE,
1674 .fixed_divider = 1,
1675 .flags = CLK_SET_RATE_PARENT),
1676 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1677 SOC_ALL,
1678 .name = "plla_per",
1679 .source_pll = "plla",
1680 .cm_reg = CM_PLLA,
1681 .a2w_reg = A2W_PLLA_PER,
1682 .load_mask = CM_PLLA_LOADPER,
1683 .hold_mask = CM_PLLA_HOLDPER,
1684 .fixed_divider = 1,
1685 .flags = CLK_SET_RATE_PARENT),
1686 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
1687 SOC_ALL,
1688 .name = "plla_dsi0",
1689 .source_pll = "plla",
1690 .cm_reg = CM_PLLA,
1691 .a2w_reg = A2W_PLLA_DSI0,
1692 .load_mask = CM_PLLA_LOADDSI0,
1693 .hold_mask = CM_PLLA_HOLDDSI0,
1694 .fixed_divider = 1),
1695 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
1696 SOC_ALL,
1697 .name = "plla_ccp2",
1698 .source_pll = "plla",
1699 .cm_reg = CM_PLLA,
1700 .a2w_reg = A2W_PLLA_CCP2,
1701 .load_mask = CM_PLLA_LOADCCP2,
1702 .hold_mask = CM_PLLA_HOLDCCP2,
1703 .fixed_divider = 1,
1704 .flags = CLK_SET_RATE_PARENT),
1706 /* PLLB is used for the ARM's clock. */
1707 [BCM2835_PLLB] = REGISTER_PLL(
1708 SOC_ALL,
1709 .name = "pllb",
1710 .cm_ctrl_reg = CM_PLLB,
1711 .a2w_ctrl_reg = A2W_PLLB_CTRL,
1712 .frac_reg = A2W_PLLB_FRAC,
1713 .ana_reg_base = A2W_PLLB_ANA0,
1714 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
1715 .lock_mask = CM_LOCK_FLOCKB,
1717 .ana = &bcm2835_ana_default,
1719 .min_rate = 600000000u,
1720 .max_rate = 3000000000u,
1721 .max_fb_rate = BCM2835_MAX_FB_RATE,
1722 .flags = CLK_GET_RATE_NOCACHE),
1723 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
1724 SOC_ALL,
1725 .name = "pllb_arm",
1726 .source_pll = "pllb",
1727 .cm_reg = CM_PLLB,
1728 .a2w_reg = A2W_PLLB_ARM,
1729 .load_mask = CM_PLLB_LOADARM,
1730 .hold_mask = CM_PLLB_HOLDARM,
1731 .fixed_divider = 1,
1732 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
1735 * PLLC is the core PLL, used to drive the core VPU clock.
1737 * It is in the PX LDO power domain, which is on when the
1738 * AUDIO domain is on.
1740 [BCM2835_PLLC] = REGISTER_PLL(
1741 SOC_ALL,
1742 .name = "pllc",
1743 .cm_ctrl_reg = CM_PLLC,
1744 .a2w_ctrl_reg = A2W_PLLC_CTRL,
1745 .frac_reg = A2W_PLLC_FRAC,
1746 .ana_reg_base = A2W_PLLC_ANA0,
1747 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1748 .lock_mask = CM_LOCK_FLOCKC,
1750 .ana = &bcm2835_ana_default,
1752 .min_rate = 600000000u,
1753 .max_rate = 3000000000u,
1754 .max_fb_rate = BCM2835_MAX_FB_RATE),
1755 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
1756 SOC_ALL,
1757 .name = "pllc_core0",
1758 .source_pll = "pllc",
1759 .cm_reg = CM_PLLC,
1760 .a2w_reg = A2W_PLLC_CORE0,
1761 .load_mask = CM_PLLC_LOADCORE0,
1762 .hold_mask = CM_PLLC_HOLDCORE0,
1763 .fixed_divider = 1,
1764 .flags = CLK_SET_RATE_PARENT),
1765 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
1766 SOC_ALL,
1767 .name = "pllc_core1",
1768 .source_pll = "pllc",
1769 .cm_reg = CM_PLLC,
1770 .a2w_reg = A2W_PLLC_CORE1,
1771 .load_mask = CM_PLLC_LOADCORE1,
1772 .hold_mask = CM_PLLC_HOLDCORE1,
1773 .fixed_divider = 1,
1774 .flags = CLK_SET_RATE_PARENT),
1775 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
1776 SOC_ALL,
1777 .name = "pllc_core2",
1778 .source_pll = "pllc",
1779 .cm_reg = CM_PLLC,
1780 .a2w_reg = A2W_PLLC_CORE2,
1781 .load_mask = CM_PLLC_LOADCORE2,
1782 .hold_mask = CM_PLLC_HOLDCORE2,
1783 .fixed_divider = 1,
1784 .flags = CLK_SET_RATE_PARENT),
1785 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
1786 SOC_ALL,
1787 .name = "pllc_per",
1788 .source_pll = "pllc",
1789 .cm_reg = CM_PLLC,
1790 .a2w_reg = A2W_PLLC_PER,
1791 .load_mask = CM_PLLC_LOADPER,
1792 .hold_mask = CM_PLLC_HOLDPER,
1793 .fixed_divider = 1,
1794 .flags = CLK_SET_RATE_PARENT),
1797 * PLLD is the display PLL, used to drive DSI display panels.
1799 * It is in the PX LDO power domain, which is on when the
1800 * AUDIO domain is on.
1802 [BCM2835_PLLD] = REGISTER_PLL(
1803 SOC_ALL,
1804 .name = "plld",
1805 .cm_ctrl_reg = CM_PLLD,
1806 .a2w_ctrl_reg = A2W_PLLD_CTRL,
1807 .frac_reg = A2W_PLLD_FRAC,
1808 .ana_reg_base = A2W_PLLD_ANA0,
1809 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
1810 .lock_mask = CM_LOCK_FLOCKD,
1812 .ana = &bcm2835_ana_default,
1814 .min_rate = 600000000u,
1815 .max_rate = 2400000000u,
1816 .max_fb_rate = BCM2835_MAX_FB_RATE),
1817 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
1818 SOC_ALL,
1819 .name = "plld_core",
1820 .source_pll = "plld",
1821 .cm_reg = CM_PLLD,
1822 .a2w_reg = A2W_PLLD_CORE,
1823 .load_mask = CM_PLLD_LOADCORE,
1824 .hold_mask = CM_PLLD_HOLDCORE,
1825 .fixed_divider = 1,
1826 .flags = CLK_SET_RATE_PARENT),
1828 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.
1829 * Otherwise this could cause firmware lookups. That's why we mark
1830 * it as critical.
1832 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
1833 SOC_ALL,
1834 .name = "plld_per",
1835 .source_pll = "plld",
1836 .cm_reg = CM_PLLD,
1837 .a2w_reg = A2W_PLLD_PER,
1838 .load_mask = CM_PLLD_LOADPER,
1839 .hold_mask = CM_PLLD_HOLDPER,
1840 .fixed_divider = 1,
1841 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1842 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
1843 SOC_ALL,
1844 .name = "plld_dsi0",
1845 .source_pll = "plld",
1846 .cm_reg = CM_PLLD,
1847 .a2w_reg = A2W_PLLD_DSI0,
1848 .load_mask = CM_PLLD_LOADDSI0,
1849 .hold_mask = CM_PLLD_HOLDDSI0,
1850 .fixed_divider = 1),
1851 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
1852 SOC_ALL,
1853 .name = "plld_dsi1",
1854 .source_pll = "plld",
1855 .cm_reg = CM_PLLD,
1856 .a2w_reg = A2W_PLLD_DSI1,
1857 .load_mask = CM_PLLD_LOADDSI1,
1858 .hold_mask = CM_PLLD_HOLDDSI1,
1859 .fixed_divider = 1),
1862 * PLLH is used to supply the pixel clock or the AUX clock for the
1863 * TV encoder.
1865 * It is in the HDMI power domain.
1867 [BCM2835_PLLH] = REGISTER_PLL(
1868 SOC_BCM2835,
1869 "pllh",
1870 .cm_ctrl_reg = CM_PLLH,
1871 .a2w_ctrl_reg = A2W_PLLH_CTRL,
1872 .frac_reg = A2W_PLLH_FRAC,
1873 .ana_reg_base = A2W_PLLH_ANA0,
1874 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
1875 .lock_mask = CM_LOCK_FLOCKH,
1877 .ana = &bcm2835_ana_pllh,
1879 .min_rate = 600000000u,
1880 .max_rate = 3000000000u,
1881 .max_fb_rate = BCM2835_MAX_FB_RATE),
1882 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
1883 SOC_BCM2835,
1884 .name = "pllh_rcal",
1885 .source_pll = "pllh",
1886 .cm_reg = CM_PLLH,
1887 .a2w_reg = A2W_PLLH_RCAL,
1888 .load_mask = CM_PLLH_LOADRCAL,
1889 .hold_mask = 0,
1890 .fixed_divider = 10,
1891 .flags = CLK_SET_RATE_PARENT),
1892 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
1893 SOC_BCM2835,
1894 .name = "pllh_aux",
1895 .source_pll = "pllh",
1896 .cm_reg = CM_PLLH,
1897 .a2w_reg = A2W_PLLH_AUX,
1898 .load_mask = CM_PLLH_LOADAUX,
1899 .hold_mask = 0,
1900 .fixed_divider = 1,
1901 .flags = CLK_SET_RATE_PARENT),
1902 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
1903 SOC_BCM2835,
1904 .name = "pllh_pix",
1905 .source_pll = "pllh",
1906 .cm_reg = CM_PLLH,
1907 .a2w_reg = A2W_PLLH_PIX,
1908 .load_mask = CM_PLLH_LOADPIX,
1909 .hold_mask = 0,
1910 .fixed_divider = 10,
1911 .flags = CLK_SET_RATE_PARENT),
1913 /* the clocks */
1915 /* clocks with oscillator parent mux */
1917 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1918 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
1919 SOC_ALL,
1920 .name = "otp",
1921 .ctl_reg = CM_OTPCTL,
1922 .div_reg = CM_OTPDIV,
1923 .int_bits = 4,
1924 .frac_bits = 0,
1925 .tcnt_mux = 6),
1927 * Used for a 1Mhz clock for the system clocksource, and also used
1928 * bythe watchdog timer and the camera pulse generator.
1930 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
1931 SOC_ALL,
1932 .name = "timer",
1933 .ctl_reg = CM_TIMERCTL,
1934 .div_reg = CM_TIMERDIV,
1935 .int_bits = 6,
1936 .frac_bits = 12),
1938 * Clock for the temperature sensor.
1939 * Generally run at 2Mhz, max 5Mhz.
1941 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
1942 SOC_ALL,
1943 .name = "tsens",
1944 .ctl_reg = CM_TSENSCTL,
1945 .div_reg = CM_TSENSDIV,
1946 .int_bits = 5,
1947 .frac_bits = 0),
1948 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
1949 SOC_ALL,
1950 .name = "tec",
1951 .ctl_reg = CM_TECCTL,
1952 .div_reg = CM_TECDIV,
1953 .int_bits = 6,
1954 .frac_bits = 0),
1956 /* clocks with vpu parent mux */
1957 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
1958 SOC_ALL,
1959 .name = "h264",
1960 .ctl_reg = CM_H264CTL,
1961 .div_reg = CM_H264DIV,
1962 .int_bits = 4,
1963 .frac_bits = 8,
1964 .tcnt_mux = 1),
1965 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
1966 SOC_ALL,
1967 .name = "isp",
1968 .ctl_reg = CM_ISPCTL,
1969 .div_reg = CM_ISPDIV,
1970 .int_bits = 4,
1971 .frac_bits = 8,
1972 .tcnt_mux = 2),
1975 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1976 * in the SDRAM controller can't be used.
1978 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
1979 SOC_ALL,
1980 .name = "sdram",
1981 .ctl_reg = CM_SDCCTL,
1982 .div_reg = CM_SDCDIV,
1983 .int_bits = 6,
1984 .frac_bits = 0,
1985 .tcnt_mux = 3),
1986 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
1987 SOC_ALL,
1988 .name = "v3d",
1989 .ctl_reg = CM_V3DCTL,
1990 .div_reg = CM_V3DDIV,
1991 .int_bits = 4,
1992 .frac_bits = 8,
1993 .tcnt_mux = 4),
1995 * VPU clock. This doesn't have an enable bit, since it drives
1996 * the bus for everything else, and is special so it doesn't need
1997 * to be gated for rate changes. It is also known as "clk_audio"
1998 * in various hardware documentation.
2000 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
2001 SOC_ALL,
2002 .name = "vpu",
2003 .ctl_reg = CM_VPUCTL,
2004 .div_reg = CM_VPUDIV,
2005 .int_bits = 12,
2006 .frac_bits = 8,
2007 .flags = CLK_IS_CRITICAL,
2008 .is_vpu_clock = true,
2009 .tcnt_mux = 5),
2011 /* clocks with per parent mux */
2012 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
2013 SOC_ALL,
2014 .name = "aveo",
2015 .ctl_reg = CM_AVEOCTL,
2016 .div_reg = CM_AVEODIV,
2017 .int_bits = 4,
2018 .frac_bits = 0,
2019 .tcnt_mux = 38),
2020 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
2021 SOC_ALL,
2022 .name = "cam0",
2023 .ctl_reg = CM_CAM0CTL,
2024 .div_reg = CM_CAM0DIV,
2025 .int_bits = 4,
2026 .frac_bits = 8,
2027 .tcnt_mux = 14),
2028 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
2029 SOC_ALL,
2030 .name = "cam1",
2031 .ctl_reg = CM_CAM1CTL,
2032 .div_reg = CM_CAM1DIV,
2033 .int_bits = 4,
2034 .frac_bits = 8,
2035 .tcnt_mux = 15),
2036 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
2037 SOC_ALL,
2038 .name = "dft",
2039 .ctl_reg = CM_DFTCTL,
2040 .div_reg = CM_DFTDIV,
2041 .int_bits = 5,
2042 .frac_bits = 0),
2043 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
2044 SOC_ALL,
2045 .name = "dpi",
2046 .ctl_reg = CM_DPICTL,
2047 .div_reg = CM_DPIDIV,
2048 .int_bits = 4,
2049 .frac_bits = 8,
2050 .tcnt_mux = 17),
2052 /* Arasan EMMC clock */
2053 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
2054 SOC_ALL,
2055 .name = "emmc",
2056 .ctl_reg = CM_EMMCCTL,
2057 .div_reg = CM_EMMCDIV,
2058 .int_bits = 4,
2059 .frac_bits = 8,
2060 .tcnt_mux = 39),
2062 /* EMMC2 clock (only available for BCM2711) */
2063 [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
2064 SOC_BCM2711,
2065 .name = "emmc2",
2066 .ctl_reg = CM_EMMC2CTL,
2067 .div_reg = CM_EMMC2DIV,
2068 .int_bits = 4,
2069 .frac_bits = 8,
2070 .tcnt_mux = 42),
2072 /* General purpose (GPIO) clocks */
2073 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
2074 SOC_ALL,
2075 .name = "gp0",
2076 .ctl_reg = CM_GP0CTL,
2077 .div_reg = CM_GP0DIV,
2078 .int_bits = 12,
2079 .frac_bits = 12,
2080 .is_mash_clock = true,
2081 .tcnt_mux = 20),
2082 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
2083 SOC_ALL,
2084 .name = "gp1",
2085 .ctl_reg = CM_GP1CTL,
2086 .div_reg = CM_GP1DIV,
2087 .int_bits = 12,
2088 .frac_bits = 12,
2089 .flags = CLK_IS_CRITICAL,
2090 .is_mash_clock = true,
2091 .tcnt_mux = 21),
2092 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
2093 SOC_ALL,
2094 .name = "gp2",
2095 .ctl_reg = CM_GP2CTL,
2096 .div_reg = CM_GP2DIV,
2097 .int_bits = 12,
2098 .frac_bits = 12,
2099 .flags = CLK_IS_CRITICAL),
2101 /* HDMI state machine */
2102 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
2103 SOC_ALL,
2104 .name = "hsm",
2105 .ctl_reg = CM_HSMCTL,
2106 .div_reg = CM_HSMDIV,
2107 .int_bits = 4,
2108 .frac_bits = 8,
2109 .tcnt_mux = 22),
2110 [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
2111 SOC_ALL,
2112 .name = "pcm",
2113 .ctl_reg = CM_PCMCTL,
2114 .div_reg = CM_PCMDIV,
2115 .int_bits = 12,
2116 .frac_bits = 12,
2117 .is_mash_clock = true,
2118 .low_jitter = true,
2119 .tcnt_mux = 23),
2120 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
2121 SOC_ALL,
2122 .name = "pwm",
2123 .ctl_reg = CM_PWMCTL,
2124 .div_reg = CM_PWMDIV,
2125 .int_bits = 12,
2126 .frac_bits = 12,
2127 .is_mash_clock = true,
2128 .tcnt_mux = 24),
2129 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
2130 SOC_ALL,
2131 .name = "slim",
2132 .ctl_reg = CM_SLIMCTL,
2133 .div_reg = CM_SLIMDIV,
2134 .int_bits = 12,
2135 .frac_bits = 12,
2136 .is_mash_clock = true,
2137 .tcnt_mux = 25),
2138 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
2139 SOC_ALL,
2140 .name = "smi",
2141 .ctl_reg = CM_SMICTL,
2142 .div_reg = CM_SMIDIV,
2143 .int_bits = 4,
2144 .frac_bits = 8,
2145 .tcnt_mux = 27),
2146 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
2147 SOC_ALL,
2148 .name = "uart",
2149 .ctl_reg = CM_UARTCTL,
2150 .div_reg = CM_UARTDIV,
2151 .int_bits = 10,
2152 .frac_bits = 12,
2153 .tcnt_mux = 28),
2155 /* TV encoder clock. Only operating frequency is 108Mhz. */
2156 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
2157 SOC_ALL,
2158 .name = "vec",
2159 .ctl_reg = CM_VECCTL,
2160 .div_reg = CM_VECDIV,
2161 .int_bits = 4,
2162 .frac_bits = 0,
2164 * Allow rate change propagation only on PLLH_AUX which is
2165 * assigned index 7 in the parent array.
2167 .set_rate_parent = BIT(7),
2168 .tcnt_mux = 29),
2170 /* dsi clocks */
2171 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
2172 SOC_ALL,
2173 .name = "dsi0e",
2174 .ctl_reg = CM_DSI0ECTL,
2175 .div_reg = CM_DSI0EDIV,
2176 .int_bits = 4,
2177 .frac_bits = 8,
2178 .tcnt_mux = 18),
2179 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
2180 SOC_ALL,
2181 .name = "dsi1e",
2182 .ctl_reg = CM_DSI1ECTL,
2183 .div_reg = CM_DSI1EDIV,
2184 .int_bits = 4,
2185 .frac_bits = 8,
2186 .tcnt_mux = 19),
2187 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
2188 SOC_ALL,
2189 .name = "dsi0p",
2190 .ctl_reg = CM_DSI0PCTL,
2191 .div_reg = CM_DSI0PDIV,
2192 .int_bits = 0,
2193 .frac_bits = 0,
2194 .tcnt_mux = 12),
2195 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
2196 SOC_ALL,
2197 .name = "dsi1p",
2198 .ctl_reg = CM_DSI1PCTL,
2199 .div_reg = CM_DSI1PDIV,
2200 .int_bits = 0,
2201 .frac_bits = 0,
2202 .tcnt_mux = 13),
2204 /* the gates */
2207 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
2208 * you have the debug bit set in the power manager, which we
2209 * don't bother exposing) are individual gates off of the
2210 * non-stop vpu clock.
2212 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2213 SOC_ALL,
2214 .name = "peri_image",
2215 .parent = "vpu",
2216 .ctl_reg = CM_PERIICTL),
2220 * Permanently take a reference on the parent of the SDRAM clock.
2222 * While the SDRAM is being driven by its dedicated PLL most of the
2223 * time, there is a little loop running in the firmware that
2224 * periodically switches the SDRAM to using our CM clock to do PVT
2225 * recalibration, with the assumption that the previously configured
2226 * SDRAM parent is still enabled and running.
2228 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2230 struct clk *parent = clk_get_parent(sdc);
2232 if (IS_ERR(parent))
2233 return PTR_ERR(parent);
2235 return clk_prepare_enable(parent);
2238 static int bcm2835_clk_probe(struct platform_device *pdev)
2240 struct device *dev = &pdev->dev;
2241 struct clk_hw **hws;
2242 struct bcm2835_cprman *cprman;
2243 const struct bcm2835_clk_desc *desc;
2244 const size_t asize = ARRAY_SIZE(clk_desc_array);
2245 const struct cprman_plat_data *pdata;
2246 size_t i;
2247 int ret;
2249 pdata = of_device_get_match_data(&pdev->dev);
2250 if (!pdata)
2251 return -ENODEV;
2253 cprman = devm_kzalloc(dev,
2254 struct_size(cprman, onecell.hws, asize),
2255 GFP_KERNEL);
2256 if (!cprman)
2257 return -ENOMEM;
2259 spin_lock_init(&cprman->regs_lock);
2260 cprman->dev = dev;
2261 cprman->regs = devm_platform_ioremap_resource(pdev, 0);
2262 if (IS_ERR(cprman->regs))
2263 return PTR_ERR(cprman->regs);
2265 memcpy(cprman->real_parent_names, cprman_parent_names,
2266 sizeof(cprman_parent_names));
2267 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2268 ARRAY_SIZE(cprman_parent_names));
2271 * Make sure the external oscillator has been registered.
2273 * The other (DSI) clocks are not present on older device
2274 * trees, which we still need to support for backwards
2275 * compatibility.
2277 if (!cprman->real_parent_names[0])
2278 return -ENODEV;
2280 platform_set_drvdata(pdev, cprman);
2282 cprman->onecell.num = asize;
2283 cprman->soc = pdata->soc;
2284 hws = cprman->onecell.hws;
2286 for (i = 0; i < asize; i++) {
2287 desc = &clk_desc_array[i];
2288 if (desc->clk_register && desc->data &&
2289 (desc->supported & pdata->soc)) {
2290 hws[i] = desc->clk_register(cprman, desc->data);
2294 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2295 if (ret)
2296 return ret;
2298 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2299 &cprman->onecell);
2302 static const struct cprman_plat_data cprman_bcm2835_plat_data = {
2303 .soc = SOC_BCM2835,
2306 static const struct cprman_plat_data cprman_bcm2711_plat_data = {
2307 .soc = SOC_BCM2711,
2310 static const struct of_device_id bcm2835_clk_of_match[] = {
2311 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2312 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2315 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
2317 static struct platform_driver bcm2835_clk_driver = {
2318 .driver = {
2319 .name = "bcm2835-clk",
2320 .of_match_table = bcm2835_clk_of_match,
2322 .probe = bcm2835_clk_probe,
2325 builtin_platform_driver(bcm2835_clk_driver);
2327 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
2328 MODULE_DESCRIPTION("BCM2835 clock driver");
2329 MODULE_LICENSE("GPL");