drivers/clk/clk-gemini.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cortina Gemini SoC Clock Controller driver
   4  * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>
   5  */
   6
   7 #define pr_fmt(fmt) "clk-gemini: " fmt
   8
   9 #include <linux/init.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/slab.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/regmap.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/reset-controller.h>
  22 #include <dt-bindings/reset/cortina,gemini-reset.h>
  23 #include <dt-bindings/clock/cortina,gemini-clock.h>
  24
  25 /* Globally visible clocks */
  26 static DEFINE_SPINLOCK(gemini_clk_lock);
  27
  28 #define GEMINI_GLOBAL_STATUS            0x04
  29 #define PLL_OSC_SEL                     BIT(30)
  30 #define AHBSPEED_SHIFT                  (15)
  31 #define AHBSPEED_MASK                   0x07
  32 #define CPU_AHB_RATIO_SHIFT             (18)
  33 #define CPU_AHB_RATIO_MASK              0x03
  34
  35 #define GEMINI_GLOBAL_PLL_CONTROL       0x08
  36
  37 #define GEMINI_GLOBAL_SOFT_RESET        0x0c
  38
  39 #define GEMINI_GLOBAL_MISC_CONTROL      0x30
  40 #define PCI_CLK_66MHZ                   BIT(18)
  41
  42 #define GEMINI_GLOBAL_CLOCK_CONTROL     0x34
  43 #define PCI_CLKRUN_EN                   BIT(16)
  44 #define TVC_HALFDIV_SHIFT               (24)
  45 #define TVC_HALFDIV_MASK                0x1f
  46 #define SECURITY_CLK_SEL                BIT(29)
  47
  48 #define GEMINI_GLOBAL_PCI_DLL_CONTROL   0x44
  49 #define PCI_DLL_BYPASS                  BIT(31)
  50 #define PCI_DLL_TAP_SEL_MASK            0x1f
  51
  52 /**
  53  * struct gemini_data_data - Gemini gated clocks
  54  * @bit_idx: the bit used to gate this clock in the clock register
  55  * @name: the clock name
  56  * @parent_name: the name of the parent clock
  57  * @flags: standard clock framework flags
  58  */
  59 struct gemini_gate_data {
  60         u8 bit_idx;
  61         const char *name;
  62         const char *parent_name;
  63         unsigned long flags;
  64 };
  65
  66 /**
  67  * struct clk_gemini_pci - Gemini PCI clock
  68  * @hw: corresponding clock hardware entry
  69  * @map: regmap to access the registers
  70  * @rate: current rate
  71  */
  72 struct clk_gemini_pci {
  73         struct clk_hw hw;
  74         struct regmap *map;
  75         unsigned long rate;
  76 };
  77
  78 /**
  79  * struct gemini_reset - gemini reset controller
  80  * @map: regmap to access the containing system controller
  81  * @rcdev: reset controller device
  82  */
  83 struct gemini_reset {
  84         struct regmap *map;
  85         struct reset_controller_dev rcdev;
  86 };
  87
  88 /* Keeps track of all clocks */
  89 static struct clk_hw_onecell_data *gemini_clk_data;
  90
  91 static const struct gemini_gate_data gemini_gates[] = {
  92         { 1, "security-gate", "secdiv", 0 },
  93         { 2, "gmac0-gate", "ahb", 0 },
  94         { 3, "gmac1-gate", "ahb", 0 },
  95         { 4, "sata0-gate", "ahb", 0 },
  96         { 5, "sata1-gate", "ahb", 0 },
  97         { 6, "usb0-gate", "ahb", 0 },
  98         { 7, "usb1-gate", "ahb", 0 },
  99         { 8, "ide-gate", "ahb", 0 },
 100         { 9, "pci-gate", "ahb", 0 },
 101         /*
 102          * The DDR controller may never have a driver, but certainly must
 103          * not be gated off.
 104          */
 105         { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
 106         /*
 107          * The flash controller must be on to access NOR flash through the
 108          * memory map.
 109          */
 110         { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
 111         { 12, "tvc-gate", "ahb", 0 },
 112         { 13, "boot-gate", "apb", 0 },
 113 };
 114
 115 #define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)
 116
 117 #define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)
 118
 119 static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
 120                                             unsigned long parent_rate)
 121 {
 122         struct clk_gemini_pci *pciclk = to_pciclk(hw);
 123         u32 val;
 124
 125         regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);
 126         if (val & PCI_CLK_66MHZ)
 127                 return 66000000;
 128         return 33000000;
 129 }
 130
 131 static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,
 132                                   unsigned long *prate)
 133 {
 134         /* We support 33 and 66 MHz */
 135         if (rate < 48000000)
 136                 return 33000000;
 137         return 66000000;
 138 }
 139
 140 static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,
 141                                unsigned long parent_rate)
 142 {
 143         struct clk_gemini_pci *pciclk = to_pciclk(hw);
 144
 145         if (rate == 33000000)
 146                 return regmap_update_bits(pciclk->map,
 147                                           GEMINI_GLOBAL_MISC_CONTROL,
 148                                           PCI_CLK_66MHZ, 0);
 149         if (rate == 66000000)
 150                 return regmap_update_bits(pciclk->map,
 151                                           GEMINI_GLOBAL_MISC_CONTROL,
 152                                           0, PCI_CLK_66MHZ);
 153         return -EINVAL;
 154 }
 155
 156 static int gemini_pci_enable(struct clk_hw *hw)
 157 {
 158         struct clk_gemini_pci *pciclk = to_pciclk(hw);
 159
 160         regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
 161                            0, PCI_CLKRUN_EN);
 162         return 0;
 163 }
 164
 165 static void gemini_pci_disable(struct clk_hw *hw)
 166 {
 167         struct clk_gemini_pci *pciclk = to_pciclk(hw);
 168
 169         regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
 170                            PCI_CLKRUN_EN, 0);
 171 }
 172
 173 static int gemini_pci_is_enabled(struct clk_hw *hw)
 174 {
 175         struct clk_gemini_pci *pciclk = to_pciclk(hw);
 176         unsigned int val;
 177
 178         regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
 179         return !!(val & PCI_CLKRUN_EN);
 180 }
 181
 182 static const struct clk_ops gemini_pci_clk_ops = {
 183         .recalc_rate = gemini_pci_recalc_rate,
 184         .round_rate = gemini_pci_round_rate,
 185         .set_rate = gemini_pci_set_rate,
 186         .enable = gemini_pci_enable,
 187         .disable = gemini_pci_disable,
 188         .is_enabled = gemini_pci_is_enabled,
 189 };
 190
 191 static struct clk_hw *gemini_pci_clk_setup(const char *name,
 192                                            const char *parent_name,
 193                                            struct regmap *map)
 194 {
 195         struct clk_gemini_pci *pciclk;
 196         struct clk_init_data init;
 197         int ret;
 198
 199         pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);
 200         if (!pciclk)
 201                 return ERR_PTR(-ENOMEM);
 202
 203         init.name = name;
 204         init.ops = &gemini_pci_clk_ops;
 205         init.flags = 0;
 206         init.parent_names = &parent_name;
 207         init.num_parents = 1;
 208         pciclk->map = map;
 209         pciclk->hw.init = &init;
 210
 211         ret = clk_hw_register(NULL, &pciclk->hw);
 212         if (ret) {
 213                 kfree(pciclk);
 214                 return ERR_PTR(ret);
 215         }
 216
 217         return &pciclk->hw;
 218 }
 219
 220 /*
 221  * This is a self-deasserting reset controller.
 222  */
 223 static int gemini_reset(struct reset_controller_dev *rcdev,
 224                         unsigned long id)
 225 {
 226         struct gemini_reset *gr = to_gemini_reset(rcdev);
 227
 228         /* Manual says to always set BIT 30 (CPU1) to 1 */
 229         return regmap_write(gr->map,
 230                             GEMINI_GLOBAL_SOFT_RESET,
 231                             BIT(GEMINI_RESET_CPU1) | BIT(id));
 232 }
 233
 234 static int gemini_reset_assert(struct reset_controller_dev *rcdev,
 235                                unsigned long id)
 236 {
 237         return 0;
 238 }
 239
 240 static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
 241                                  unsigned long id)
 242 {
 243         return 0;
 244 }
 245
 246 static int gemini_reset_status(struct reset_controller_dev *rcdev,
 247                              unsigned long id)
 248 {
 249         struct gemini_reset *gr = to_gemini_reset(rcdev);
 250         u32 val;
 251         int ret;
 252
 253         ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);
 254         if (ret)
 255                 return ret;
 256
 257         return !!(val & BIT(id));
 258 }
 259
 260 static const struct reset_control_ops gemini_reset_ops = {
 261         .reset = gemini_reset,
 262         .assert = gemini_reset_assert,
 263         .deassert = gemini_reset_deassert,
 264         .status = gemini_reset_status,
 265 };
 266
 267 static int gemini_clk_probe(struct platform_device *pdev)
 268 {
 269         /* Gives the fracions 1x, 1.5x, 1.85x and 2x */
 270         unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
 271         unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
 272         void __iomem *base;
 273         struct gemini_reset *gr;
 274         struct regmap *map;
 275         struct clk_hw *hw;
 276         struct device *dev = &pdev->dev;
 277         struct device_node *np = dev->of_node;
 278         unsigned int mult, div;
 279         struct resource *res;
 280         u32 val;
 281         int ret;
 282         int i;
 283
 284         gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
 285         if (!gr)
 286                 return -ENOMEM;
 287
 288         /* Remap the system controller for the exclusive register */
 289         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 290         base = devm_ioremap_resource(dev, res);
 291         if (IS_ERR(base))
 292                 return PTR_ERR(base);
 293
 294         map = syscon_node_to_regmap(np);
 295         if (IS_ERR(map)) {
 296                 dev_err(dev, "no syscon regmap\n");
 297                 return PTR_ERR(map);
 298         }
 299
 300         gr->map = map;
 301         gr->rcdev.owner = THIS_MODULE;
 302         gr->rcdev.nr_resets = 32;
 303         gr->rcdev.ops = &gemini_reset_ops;
 304         gr->rcdev.of_node = np;
 305
 306         ret = devm_reset_controller_register(dev, &gr->rcdev);
 307         if (ret) {
 308                 dev_err(dev, "could not register reset controller\n");
 309                 return ret;
 310         }
 311
 312         /* RTC clock 32768 Hz */
 313         hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
 314         gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;
 315
 316         /* CPU clock derived as a fixed ratio from the AHB clock */
 317         regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
 318         val >>= CPU_AHB_RATIO_SHIFT;
 319         val &= CPU_AHB_RATIO_MASK;
 320         hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,
 321                                           cpu_ahb_mult[val],
 322                                           cpu_ahb_div[val]);
 323         gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;
 324
 325         /* Security clock is 1:1 or 0.75 of APB */
 326         regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
 327         if (val & SECURITY_CLK_SEL) {
 328                 mult = 1;
 329                 div = 1;
 330         } else {
 331                 mult = 3;
 332                 div = 4;
 333         }
 334         hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);
 335
 336         /*
 337          * These are the leaf gates, at boot no clocks are gated.
 338          */
 339         for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {
 340                 const struct gemini_gate_data *gd;
 341
 342                 gd = &gemini_gates[i];
 343                 gemini_clk_data->hws[GEMINI_CLK_GATES + i] =
 344                         clk_hw_register_gate(NULL, gd->name,
 345                                              gd->parent_name,
 346                                              gd->flags,
 347                                              base + GEMINI_GLOBAL_CLOCK_CONTROL,
 348                                              gd->bit_idx,
 349                                              CLK_GATE_SET_TO_DISABLE,
 350                                              &gemini_clk_lock);
 351         }
 352
 353         /*
 354          * The TV Interface Controller has a 5-bit half divider register.
 355          * This clock is supposed to be 27MHz as this is an exact multiple
 356          * of PAL and NTSC frequencies. The register is undocumented :(
 357          * FIXME: figure out the parent and how the divider works.
 358          */
 359         mult = 1;
 360         div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);
 361         dev_dbg(dev, "TVC half divider value = %d\n", div);
 362         div += 1;
 363         hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);
 364         gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;
 365
 366         /* FIXME: very unclear what the parent is */
 367         hw = gemini_pci_clk_setup("PCI", "xtal", map);
 368         gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;
 369
 370         /* FIXME: very unclear what the parent is */
 371         hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);
 372         gemini_clk_data->hws[GEMINI_CLK_UART] = hw;
 373
 374         return 0;
 375 }
 376
 377 static const struct of_device_id gemini_clk_dt_ids[] = {
 378         { .compatible = "cortina,gemini-syscon", },
 379         { /* sentinel */ },
 380 };
 381
 382 static struct platform_driver gemini_clk_driver = {
 383         .probe  = gemini_clk_probe,
 384         .driver = {
 385                 .name = "gemini-clk",
 386                 .of_match_table = gemini_clk_dt_ids,
 387                 .suppress_bind_attrs = true,
 388         },
 389 };
 390 builtin_platform_driver(gemini_clk_driver);
 391
 392 static void __init gemini_cc_init(struct device_node *np)
 393 {
 394         struct regmap *map;
 395         struct clk_hw *hw;
 396         unsigned long freq;
 397         unsigned int mult, div;
 398         u32 val;
 399         int ret;
 400         int i;
 401
 402         gemini_clk_data = kzalloc(struct_size(gemini_clk_data, hws,
 403                                               GEMINI_NUM_CLKS),
 404                                   GFP_KERNEL);
 405         if (!gemini_clk_data)
 406                 return;
 407
 408         /*
 409          * This way all clock fetched before the platform device probes,
 410          * except those we assign here for early use, will be deferred.
 411          */
 412         for (i = 0; i < GEMINI_NUM_CLKS; i++)
 413                 gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
 414
 415         map = syscon_node_to_regmap(np);
 416         if (IS_ERR(map)) {
 417                 pr_err("no syscon regmap\n");
 418                 return;
 419         }
 420         /*
 421          * We check that the regmap works on this very first access,
 422          * but as this is an MMIO-backed regmap, subsequent regmap
 423          * access is not going to fail and we skip error checks from
 424          * this point.
 425          */
 426         ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
 427         if (ret) {
 428                 pr_err("failed to read global status register\n");
 429                 return;
 430         }
 431
 432         /*
 433          * XTAL is the crystal oscillator, 60 or 30 MHz selected from
 434          * strap pin E6
 435          */
 436         if (val & PLL_OSC_SEL)
 437                 freq = 30000000;
 438         else
 439                 freq = 60000000;
 440         hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
 441         pr_debug("main crystal @%lu MHz\n", freq / 1000000);
 442
 443         /* VCO clock derived from the crystal */
 444         mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
 445         div = 2;
 446         /* If we run on 30 MHz crystal we have to multiply with two */
 447         if (val & PLL_OSC_SEL)
 448                 mult *= 2;
 449         hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
 450
 451         /* The AHB clock is always 1/3 of the VCO */
 452         hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
 453         gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
 454
 455         /* The APB clock is always 1/6 of the AHB */
 456         hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
 457         gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
 458
 459         /* Register the clocks to be accessed by the device tree */
 460         gemini_clk_data->num = GEMINI_NUM_CLKS;
 461         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
 462 }
 463 CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);