1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Hisilicon clock separated gate driver
5 * Copyright (c) 2012-2013 Hisilicon Limited.
6 * Copyright (c) 2012-2013 Linaro Limited.
8 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
9 * Xin Li <li.xin@linaro.org>
12 #include <linux/kernel.h>
13 #include <linux/clk-provider.h>
15 #include <linux/slab.h>
19 /* clock separated gate register offset */
20 #define CLKGATE_SEPERATED_ENABLE 0x0
21 #define CLKGATE_SEPERATED_DISABLE 0x4
22 #define CLKGATE_SEPERATED_STATUS 0x8
24 struct clkgate_separated
{
26 void __iomem
*enable
; /* enable register */
27 u8 bit_idx
; /* bits in enable/disable register */
32 static int clkgate_separated_enable(struct clk_hw
*hw
)
34 struct clkgate_separated
*sclk
;
35 unsigned long flags
= 0;
38 sclk
= container_of(hw
, struct clkgate_separated
, hw
);
40 spin_lock_irqsave(sclk
->lock
, flags
);
41 reg
= BIT(sclk
->bit_idx
);
42 writel_relaxed(reg
, sclk
->enable
);
43 readl_relaxed(sclk
->enable
+ CLKGATE_SEPERATED_STATUS
);
45 spin_unlock_irqrestore(sclk
->lock
, flags
);
49 static void clkgate_separated_disable(struct clk_hw
*hw
)
51 struct clkgate_separated
*sclk
;
52 unsigned long flags
= 0;
55 sclk
= container_of(hw
, struct clkgate_separated
, hw
);
57 spin_lock_irqsave(sclk
->lock
, flags
);
58 reg
= BIT(sclk
->bit_idx
);
59 writel_relaxed(reg
, sclk
->enable
+ CLKGATE_SEPERATED_DISABLE
);
60 readl_relaxed(sclk
->enable
+ CLKGATE_SEPERATED_STATUS
);
62 spin_unlock_irqrestore(sclk
->lock
, flags
);
65 static int clkgate_separated_is_enabled(struct clk_hw
*hw
)
67 struct clkgate_separated
*sclk
;
70 sclk
= container_of(hw
, struct clkgate_separated
, hw
);
71 reg
= readl_relaxed(sclk
->enable
+ CLKGATE_SEPERATED_STATUS
);
72 reg
&= BIT(sclk
->bit_idx
);
77 static const struct clk_ops clkgate_separated_ops
= {
78 .enable
= clkgate_separated_enable
,
79 .disable
= clkgate_separated_disable
,
80 .is_enabled
= clkgate_separated_is_enabled
,
83 struct clk
*hisi_register_clkgate_sep(struct device
*dev
, const char *name
,
84 const char *parent_name
,
86 void __iomem
*reg
, u8 bit_idx
,
87 u8 clk_gate_flags
, spinlock_t
*lock
)
89 struct clkgate_separated
*sclk
;
91 struct clk_init_data init
;
93 sclk
= kzalloc(sizeof(*sclk
), GFP_KERNEL
);
95 return ERR_PTR(-ENOMEM
);
98 init
.ops
= &clkgate_separated_ops
;
100 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
101 init
.num_parents
= (parent_name
? 1 : 0);
103 sclk
->enable
= reg
+ CLKGATE_SEPERATED_ENABLE
;
104 sclk
->bit_idx
= bit_idx
;
105 sclk
->flags
= clk_gate_flags
;
106 sclk
->hw
.init
= &init
;
109 clk
= clk_register(dev
, &sclk
->hw
);