drivers/clk/mediatek/clk-mt7629-hif.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 MediaTek Inc.
   4  * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
   5  *         Ryder Lee <ryder.lee@mediatek.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13
  14 #include "clk-mtk.h"
  15 #include "clk-gate.h"
  16
  17 #include <dt-bindings/clock/mt7629-clk.h>
  18
  19 #define GATE_PCIE(_id, _name, _parent, _shift) {        \
  20                 .id = _id,                              \
  21                 .name = _name,                          \
  22                 .parent_name = _parent,                 \
  23                 .regs = &pcie_cg_regs,                  \
  24                 .shift = _shift,                        \
  25                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  26         }
  27
  28 #define GATE_SSUSB(_id, _name, _parent, _shift) {       \
  29                 .id = _id,                              \
  30                 .name = _name,                          \
  31                 .parent_name = _parent,                 \
  32                 .regs = &ssusb_cg_regs,                 \
  33                 .shift = _shift,                        \
  34                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
  35         }
  36
  37 static const struct mtk_gate_regs pcie_cg_regs = {
  38         .set_ofs = 0x30,
  39         .clr_ofs = 0x30,
  40         .sta_ofs = 0x30,
  41 };
  42
  43 static const struct mtk_gate_regs ssusb_cg_regs = {
  44         .set_ofs = 0x30,
  45         .clr_ofs = 0x30,
  46         .sta_ofs = 0x30,
  47 };
  48
  49 static const struct mtk_gate ssusb_clks[] = {
  50         GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
  51                    "to_u2_phy_1p", 0),
  52         GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
  53         GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
  54         GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
  55         GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
  56         GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
  57 };
  58
  59 static const struct mtk_gate pcie_clks[] = {
  60         GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
  61         GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
  62         GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
  63         GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
  64         GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
  65         GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
  66         GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
  67         GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
  68         GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
  69         GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
  70         GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
  71         GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
  72 };
  73
  74 static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
  75 {
  76         struct clk_onecell_data *clk_data;
  77         struct device_node *node = pdev->dev.of_node;
  78         int r;
  79
  80         clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
  81
  82         mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
  83                                clk_data);
  84
  85         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
  86         if (r)
  87                 dev_err(&pdev->dev,
  88                         "could not register clock provider: %s: %d\n",
  89                         pdev->name, r);
  90
  91         mtk_register_reset_controller(node, 1, 0x34);
  92
  93         return r;
  94 }
  95
  96 static int clk_mt7629_pciesys_init(struct platform_device *pdev)
  97 {
  98         struct clk_onecell_data *clk_data;
  99         struct device_node *node = pdev->dev.of_node;
 100         int r;
 101
 102         clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
 103
 104         mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
 105                                clk_data);
 106
 107         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 108         if (r)
 109                 dev_err(&pdev->dev,
 110                         "could not register clock provider: %s: %d\n",
 111                         pdev->name, r);
 112
 113         mtk_register_reset_controller(node, 1, 0x34);
 114
 115         return r;
 116 }
 117
 118 static const struct of_device_id of_match_clk_mt7629_hif[] = {
 119         {
 120                 .compatible = "mediatek,mt7629-pciesys",
 121                 .data = clk_mt7629_pciesys_init,
 122         }, {
 123                 .compatible = "mediatek,mt7629-ssusbsys",
 124                 .data = clk_mt7629_ssusbsys_init,
 125         }, {
 126                 /* sentinel */
 127         }
 128 };
 129
 130 static int clk_mt7629_hif_probe(struct platform_device *pdev)
 131 {
 132         int (*clk_init)(struct platform_device *);
 133         int r;
 134
 135         clk_init = of_device_get_match_data(&pdev->dev);
 136         if (!clk_init)
 137                 return -EINVAL;
 138
 139         r = clk_init(pdev);
 140         if (r)
 141                 dev_err(&pdev->dev,
 142                         "could not register clock provider: %s: %d\n",
 143                         pdev->name, r);
 144
 145         return r;
 146 }
 147
 148 static struct platform_driver clk_mt7629_hif_drv = {
 149         .probe = clk_mt7629_hif_probe,
 150         .driver = {
 151                 .name = "clk-mt7629-hif",
 152                 .of_match_table = of_match_clk_mt7629_hif,
 153         },
 154 };
 155
 156 builtin_platform_driver(clk_mt7629_hif_drv);