drivers/clk/microchip/clk-pic32mzda.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Purna Chandra Mandal,<purna.mandal@microchip.com>
   4  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
   5  */
   6 #include <dt-bindings/clock/microchip,pic32-clock.h>
   7 #include <linux/clk.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/clkdev.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_device.h>
  15 #include <asm/traps.h>
  16
  17 #include "clk-core.h"
  18
  19 /* FRC Postscaler */
  20 #define OSC_FRCDIV_MASK         0x07
  21 #define OSC_FRCDIV_SHIFT        24
  22
  23 /* SPLL fields */
  24 #define PLL_ICLK_MASK           0x01
  25 #define PLL_ICLK_SHIFT          7
  26
  27 #define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags)    \
  28         {                                                       \
  29                 .ctrl_reg = (__reg),                            \
  30                 .init_data = {                                  \
  31                         .name = (__clk_name),                   \
  32                         .parent_names = (const char *[]) {      \
  33                                 "sys_clk"                       \
  34                         },                                      \
  35                         .num_parents = 1,                       \
  36                         .ops = &pic32_pbclk_ops,                \
  37                         .flags = (__flags),                     \
  38                 },                                              \
  39         }
  40
  41 #define DECLARE_REFO_CLOCK(__clkid, __reg)                              \
  42         {                                                               \
  43                 .ctrl_reg = (__reg),                                    \
  44                 .init_data = {                                          \
  45                         .name = "refo" #__clkid "_clk",                 \
  46                         .parent_names = (const char *[]) {              \
  47                                 "sys_clk", "pb1_clk", "posc_clk",       \
  48                                 "frc_clk", "lprc_clk", "sosc_clk",      \
  49                                 "sys_pll", "refi" #__clkid "_clk",      \
  50                                 "bfrc_clk",                             \
  51                         },                                              \
  52                         .num_parents = 9,                               \
  53                         .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\
  54                         .ops = &pic32_roclk_ops,                        \
  55                 },                                                      \
  56                 .parent_map = (const u32[]) {                           \
  57                         0, 1, 2, 3, 4, 5, 7, 8, 9                       \
  58                 },                                                      \
  59         }
  60
  61 static const struct pic32_ref_osc_data ref_clks[] = {
  62         DECLARE_REFO_CLOCK(1, 0x80),
  63         DECLARE_REFO_CLOCK(2, 0xa0),
  64         DECLARE_REFO_CLOCK(3, 0xc0),
  65         DECLARE_REFO_CLOCK(4, 0xe0),
  66         DECLARE_REFO_CLOCK(5, 0x100),
  67 };
  68
  69 static const struct pic32_periph_clk_data periph_clocks[] = {
  70         DECLARE_PERIPHERAL_CLOCK("pb1_clk", 0x140, 0),
  71         DECLARE_PERIPHERAL_CLOCK("pb2_clk", 0x150, CLK_IGNORE_UNUSED),
  72         DECLARE_PERIPHERAL_CLOCK("pb3_clk", 0x160, 0),
  73         DECLARE_PERIPHERAL_CLOCK("pb4_clk", 0x170, 0),
  74         DECLARE_PERIPHERAL_CLOCK("pb5_clk", 0x180, 0),
  75         DECLARE_PERIPHERAL_CLOCK("pb6_clk", 0x190, 0),
  76         DECLARE_PERIPHERAL_CLOCK("cpu_clk", 0x1a0, CLK_IGNORE_UNUSED),
  77 };
  78
  79 static const struct pic32_sys_clk_data sys_mux_clk = {
  80         .slew_reg = 0x1c0,
  81         .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
  82         .init_data = {
  83                 .name = "sys_clk",
  84                 .parent_names = (const char *[]) {
  85                         "frcdiv_clk", "sys_pll", "posc_clk",
  86                         "sosc_clk", "lprc_clk", "frcdiv_clk",
  87                 },
  88                 .num_parents = 6,
  89                 .ops = &pic32_sclk_ops,
  90         },
  91         .parent_map = (const u32[]) {
  92                 0, 1, 2, 4, 5, 7,
  93         },
  94 };
  95
  96 static const struct pic32_sys_pll_data sys_pll = {
  97         .ctrl_reg = 0x020,
  98         .status_reg = 0x1d0,
  99         .lock_mask = BIT(7),
 100         .init_data = {
 101                 .name = "sys_pll",
 102                 .parent_names = (const char *[]) {
 103                         "spll_mux_clk"
 104                 },
 105                 .num_parents = 1,
 106                 .ops = &pic32_spll_ops,
 107         },
 108 };
 109
 110 static const struct pic32_sec_osc_data sosc_clk = {
 111         .status_reg = 0x1d0,
 112         .enable_mask = BIT(1),
 113         .status_mask = BIT(4),
 114         .fixed_rate = 32768,
 115         .init_data = {
 116                 .name = "sosc_clk",
 117                 .parent_names = NULL,
 118                 .ops = &pic32_sosc_ops,
 119         },
 120 };
 121
 122 static int pic32mzda_critical_clks[] = {
 123         PB2CLK, PB7CLK
 124 };
 125
 126 /* PIC32MZDA clock data */
 127 struct pic32mzda_clk_data {
 128         struct clk *clks[MAXCLKS];
 129         struct pic32_clk_common core;
 130         struct clk_onecell_data onecell_data;
 131         struct notifier_block failsafe_notifier;
 132 };
 133
 134 static int pic32_fscm_nmi(struct notifier_block *nb,
 135                           unsigned long action, void *data)
 136 {
 137         struct pic32mzda_clk_data *cd;
 138
 139         cd  = container_of(nb, struct pic32mzda_clk_data, failsafe_notifier);
 140
 141         /* SYSCLK is now running from BFRCCLK. Report clock failure. */
 142         if (readl(cd->core.iobase) & BIT(2))
 143                 pr_alert("pic32-clk: FSCM detected clk failure.\n");
 144
 145         /* TODO: detect reason of failure and recover accordingly */
 146
 147         return NOTIFY_OK;
 148 }
 149
 150 static int pic32mzda_clk_probe(struct platform_device *pdev)
 151 {
 152         const char *const pll_mux_parents[] = {"posc_clk", "frc_clk"};
 153         struct device_node *np = pdev->dev.of_node;
 154         struct pic32mzda_clk_data *cd;
 155         struct pic32_clk_common *core;
 156         struct clk *pll_mux_clk, *clk;
 157         struct clk **clks;
 158         int nr_clks, i, ret;
 159
 160         cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL);
 161         if (!cd)
 162                 return -ENOMEM;
 163
 164         core = &cd->core;
 165         core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np));
 166         if (IS_ERR(core->iobase)) {
 167                 dev_err(&pdev->dev, "pic32-clk: failed to map registers\n");
 168                 return PTR_ERR(core->iobase);
 169         }
 170
 171         spin_lock_init(&core->reg_lock);
 172         core->dev = &pdev->dev;
 173         clks = &cd->clks[0];
 174
 175         /* register fixed rate clocks */
 176         clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,
 177                                                 0, 24000000);
 178         clks[FRCCLK] =  clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,
 179                                                 0, 8000000);
 180         clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,
 181                                                 0, 8000000);
 182         clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,
 183                                                 0, 32000);
 184         clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,
 185                                                 0, 24000000);
 186         /* fixed rate (optional) clock */
 187         if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) {
 188                 pr_info("pic32-clk: dt requests SOSC.\n");
 189                 clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core);
 190         }
 191         /* divider clock */
 192         clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
 193                                                "frc_clk", 0,
 194                                                core->iobase,
 195                                                OSC_FRCDIV_SHIFT,
 196                                                OSC_FRCDIV_MASK,
 197                                                CLK_DIVIDER_POWER_OF_TWO,
 198                                                &core->reg_lock);
 199         /* PLL ICLK mux */
 200         pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",
 201                                        pll_mux_parents, 2, 0,
 202                                        core->iobase + 0x020,
 203                                        PLL_ICLK_SHIFT, 1, 0, &core->reg_lock);
 204         if (IS_ERR(pll_mux_clk))
 205                 pr_err("spll_mux_clk: clk register failed\n");
 206
 207         /* PLL */
 208         clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core);
 209         /* SYSTEM clock */
 210         clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core);
 211         /* Peripheral bus clocks */
 212         for (nr_clks = PB1CLK, i = 0; nr_clks <= PB7CLK; i++, nr_clks++)
 213                 clks[nr_clks] = pic32_periph_clk_register(&periph_clocks[i],
 214                                                           core);
 215         /* Reference oscillator clock */
 216         for (nr_clks = REF1CLK, i = 0; nr_clks <= REF5CLK; i++, nr_clks++)
 217                 clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core);
 218
 219         /* register clkdev */
 220         for (i = 0; i < MAXCLKS; i++) {
 221                 if (IS_ERR(clks[i]))
 222                         continue;
 223                 clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i]));
 224         }
 225
 226         /* register clock provider */
 227         cd->onecell_data.clks = clks;
 228         cd->onecell_data.clk_num = MAXCLKS;
 229         ret = of_clk_add_provider(np, of_clk_src_onecell_get,
 230                                   &cd->onecell_data);
 231         if (ret)
 232                 return ret;
 233
 234         /* force enable critical clocks */
 235         for (i = 0; i < ARRAY_SIZE(pic32mzda_critical_clks); i++) {
 236                 clk = clks[pic32mzda_critical_clks[i]];
 237                 if (clk_prepare_enable(clk))
 238                         dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n",
 239                                 __clk_get_name(clk));
 240         }
 241
 242         /* register NMI for failsafe clock monitor */
 243         cd->failsafe_notifier.notifier_call = pic32_fscm_nmi;
 244         return register_nmi_notifier(&cd->failsafe_notifier);
 245 }
 246
 247 static const struct of_device_id pic32mzda_clk_match_table[] = {
 248         { .compatible = "microchip,pic32mzda-clk", },
 249         { }
 250 };
 251 MODULE_DEVICE_TABLE(of, pic32mzda_clk_match_table);
 252
 253 static struct platform_driver pic32mzda_clk_driver = {
 254         .probe          = pic32mzda_clk_probe,
 255         .driver         = {
 256                 .name   = "clk-pic32mzda",
 257                 .of_match_table = pic32mzda_clk_match_table,
 258         },
 259 };
 260
 261 static int __init microchip_pic32mzda_clk_init(void)
 262 {
 263         return platform_driver_register(&pic32mzda_clk_driver);
 264 }
 265 core_initcall(microchip_pic32mzda_clk_init);
 266
 267 MODULE_DESCRIPTION("Microchip PIC32MZDA Clock Driver");
 268 MODULE_LICENSE("GPL v2");
 269 MODULE_ALIAS("platform:clk-pic32mzda");