1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MMP PLL clock rate calculation
5 * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
8 #include <linux/clk-provider.h>
9 #include <linux/slab.h>
14 #define to_clk_mmp_pll(hw) container_of(hw, struct mmp_clk_pll, hw)
18 unsigned long default_rate
;
19 void __iomem
*enable_reg
;
24 unsigned long input_rate
;
25 void __iomem
*postdiv_reg
;
29 static int mmp_clk_pll_is_enabled(struct clk_hw
*hw
)
31 struct mmp_clk_pll
*pll
= to_clk_mmp_pll(hw
);
34 val
= readl_relaxed(pll
->enable_reg
);
35 if ((val
& pll
->enable
) == pll
->enable
)
38 /* Some PLLs, if not software controlled, output default clock. */
39 if (pll
->default_rate
> 0)
45 static unsigned long mmp_clk_pll_recalc_rate(struct clk_hw
*hw
,
46 unsigned long parent_rate
)
48 struct mmp_clk_pll
*pll
= to_clk_mmp_pll(hw
);
49 u32 fbdiv
, refdiv
, postdiv
;
53 val
= readl_relaxed(pll
->enable_reg
);
54 if ((val
& pll
->enable
) != pll
->enable
)
55 return pll
->default_rate
;
58 val
= readl_relaxed(pll
->reg
);
59 fbdiv
= (val
>> pll
->shift
) & 0x1ff;
60 refdiv
= (val
>> (pll
->shift
+ 9)) & 0x1f;
66 if (pll
->postdiv_reg
) {
67 /* MMP3 clock rate calculation */
68 static const u8 postdivs
[] = {2, 3, 4, 5, 6, 8, 10, 12, 16};
70 val
= readl_relaxed(pll
->postdiv_reg
);
71 postdiv
= (val
>> pll
->postdiv_shift
) & 0x7;
73 rate
= pll
->input_rate
;
76 do_div(rate
, postdivs
[postdiv
]);
78 /* MMP2 clock rate calculation */
81 } else if (refdiv
== 4) {
84 pr_err("bad refdiv: %d (0x%08x)\n", refdiv
, val
);
89 do_div(rate
, refdiv
+ 2);
92 return (unsigned long)rate
;
95 static const struct clk_ops mmp_clk_pll_ops
= {
96 .is_enabled
= mmp_clk_pll_is_enabled
,
97 .recalc_rate
= mmp_clk_pll_recalc_rate
,
100 static struct clk
*mmp_clk_register_pll(char *name
,
101 unsigned long default_rate
,
102 void __iomem
*enable_reg
, u32 enable
,
103 void __iomem
*reg
, u8 shift
,
104 unsigned long input_rate
,
105 void __iomem
*postdiv_reg
, u8 postdiv_shift
)
107 struct mmp_clk_pll
*pll
;
109 struct clk_init_data init
;
111 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
113 return ERR_PTR(-ENOMEM
);
116 init
.ops
= &mmp_clk_pll_ops
;
118 init
.parent_names
= NULL
;
119 init
.num_parents
= 0;
121 pll
->default_rate
= default_rate
;
122 pll
->enable_reg
= enable_reg
;
123 pll
->enable
= enable
;
127 pll
->input_rate
= input_rate
;
128 pll
->postdiv_reg
= postdiv_reg
;
129 pll
->postdiv_shift
= postdiv_shift
;
131 pll
->hw
.init
= &init
;
133 clk
= clk_register(NULL
, &pll
->hw
);
141 void mmp_register_pll_clks(struct mmp_clk_unit
*unit
,
142 struct mmp_param_pll_clk
*clks
,
143 void __iomem
*base
, int size
)
148 for (i
= 0; i
< size
; i
++) {
149 void __iomem
*reg
= NULL
;
152 reg
= base
+ clks
[i
].offset
;
154 clk
= mmp_clk_register_pll(clks
[i
].name
,
155 clks
[i
].default_rate
,
156 base
+ clks
[i
].enable_offset
,
160 base
+ clks
[i
].postdiv_offset
,
161 clks
[i
].postdiv_shift
);
163 pr_err("%s: failed to register clock %s\n",
164 __func__
, clks
[i
].name
);
168 unit
->clk_table
[clks
[i
].id
] = clk
;