drivers/clk/qcom/gcc-sm8150.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/kernel.h>
   5 #include <linux/bitops.h>
   6 #include <linux/err.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/regmap.h>
  13 #include <linux/reset-controller.h>
  14
  15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  16
  17 #include "common.h"
  18 #include "clk-alpha-pll.h"
  19 #include "clk-branch.h"
  20 #include "clk-pll.h"
  21 #include "clk-rcg.h"
  22 #include "clk-regmap.h"
  23 #include "reset.h"
  24 #include "gdsc.h"
  25
  26 enum {
  27         P_BI_TCXO,
  28         P_AUD_REF_CLK,
  29         P_CORE_BI_PLL_TEST_SE,
  30         P_GPLL0_OUT_EVEN,
  31         P_GPLL0_OUT_MAIN,
  32         P_GPLL7_OUT_MAIN,
  33         P_GPLL9_OUT_MAIN,
  34         P_SLEEP_CLK,
  35 };
  36
  37 static struct clk_alpha_pll gpll0 = {
  38         .offset = 0x0,
  39         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  40         .clkr = {
  41                 .enable_reg = 0x52000,
  42                 .enable_mask = BIT(0),
  43                 .hw.init = &(struct clk_init_data){
  44                         .name = "gpll0",
  45                         .parent_data = &(const struct clk_parent_data){
  46                                 .fw_name = "bi_tcxo",
  47                                 .name = "bi_tcxo",
  48                         },
  49                         .num_parents = 1,
  50                         .ops = &clk_alpha_pll_fixed_trion_ops,
  51                 },
  52         },
  53 };
  54
  55 static const struct clk_div_table post_div_table_trion_even[] = {
  56         { 0x0, 1 },
  57         { 0x1, 2 },
  58         { 0x3, 4 },
  59         { 0x7, 8 },
  60         { }
  61 };
  62
  63 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  64         .offset = 0x0,
  65         .post_div_shift = 8,
  66         .post_div_table = post_div_table_trion_even,
  67         .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
  68         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  69         .width = 4,
  70         .clkr.hw.init = &(struct clk_init_data){
  71                 .name = "gpll0_out_even",
  72                 .parent_data = &(const struct clk_parent_data){
  73                         .hw = &gpll0.clkr.hw,
  74                 },
  75                 .num_parents = 1,
  76                 .ops = &clk_alpha_pll_postdiv_trion_ops,
  77         },
  78 };
  79
  80 static struct clk_alpha_pll gpll7 = {
  81         .offset = 0x1a000,
  82         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
  83         .clkr = {
  84                 .enable_reg = 0x52000,
  85                 .enable_mask = BIT(7),
  86                 .hw.init = &(struct clk_init_data){
  87                         .name = "gpll7",
  88                         .parent_data = &(const struct clk_parent_data){
  89                                 .fw_name = "bi_tcxo",
  90                                 .name = "bi_tcxo",
  91                         },
  92                         .num_parents = 1,
  93                         .ops = &clk_alpha_pll_fixed_trion_ops,
  94                 },
  95         },
  96 };
  97
  98 static struct clk_alpha_pll gpll9 = {
  99         .offset = 0x1c000,
 100         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
 101         .clkr = {
 102                 .enable_reg = 0x52000,
 103                 .enable_mask = BIT(9),
 104                 .hw.init = &(struct clk_init_data){
 105                         .name = "gpll9",
 106                         .parent_data = &(const struct clk_parent_data){
 107                                 .fw_name = "bi_tcxo",
 108                                 .name = "bi_tcxo",
 109                         },
 110                         .num_parents = 1,
 111                         .ops = &clk_alpha_pll_fixed_trion_ops,
 112                 },
 113         },
 114 };
 115
 116 static const struct parent_map gcc_parent_map_0[] = {
 117         { P_BI_TCXO, 0 },
 118         { P_GPLL0_OUT_MAIN, 1 },
 119         { P_GPLL0_OUT_EVEN, 6 },
 120         { P_CORE_BI_PLL_TEST_SE, 7 },
 121 };
 122
 123 static const struct clk_parent_data gcc_parents_0[] = {
 124         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 125         { .hw = &gpll0.clkr.hw },
 126         { .hw = &gpll0_out_even.clkr.hw },
 127         { .fw_name = "core_bi_pll_test_se" },
 128 };
 129
 130 static const struct parent_map gcc_parent_map_1[] = {
 131         { P_BI_TCXO, 0 },
 132         { P_GPLL0_OUT_MAIN, 1 },
 133         { P_SLEEP_CLK, 5 },
 134         { P_GPLL0_OUT_EVEN, 6 },
 135         { P_CORE_BI_PLL_TEST_SE, 7 },
 136 };
 137
 138 static const struct clk_parent_data gcc_parents_1[] = {
 139         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 140         { .hw = &gpll0.clkr.hw },
 141         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 142         { .hw = &gpll0_out_even.clkr.hw },
 143         { .fw_name = "core_bi_pll_test_se" },
 144 };
 145
 146 static const struct parent_map gcc_parent_map_2[] = {
 147         { P_BI_TCXO, 0 },
 148         { P_SLEEP_CLK, 5 },
 149         { P_CORE_BI_PLL_TEST_SE, 7 },
 150 };
 151
 152 static const struct clk_parent_data gcc_parents_2[] = {
 153         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 154         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 155         { .fw_name = "core_bi_pll_test_se" },
 156 };
 157
 158 static const struct parent_map gcc_parent_map_3[] = {
 159         { P_BI_TCXO, 0 },
 160         { P_GPLL0_OUT_MAIN, 1 },
 161         { P_CORE_BI_PLL_TEST_SE, 7 },
 162 };
 163
 164 static const struct clk_parent_data gcc_parents_3[] = {
 165         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 166         { .hw = &gpll0.clkr.hw },
 167         { .fw_name = "core_bi_pll_test_se"},
 168 };
 169
 170 static const struct parent_map gcc_parent_map_4[] = {
 171         { P_BI_TCXO, 0 },
 172         { P_CORE_BI_PLL_TEST_SE, 7 },
 173 };
 174
 175 static const struct clk_parent_data gcc_parents_4[] = {
 176         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 177         { .fw_name = "core_bi_pll_test_se" },
 178 };
 179
 180 static const struct parent_map gcc_parent_map_5[] = {
 181         { P_BI_TCXO, 0 },
 182         { P_GPLL0_OUT_MAIN, 1 },
 183         { P_GPLL7_OUT_MAIN, 3 },
 184         { P_GPLL0_OUT_EVEN, 6 },
 185         { P_CORE_BI_PLL_TEST_SE, 7 },
 186 };
 187
 188 static const struct clk_parent_data gcc_parents_5[] = {
 189         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 190         { .hw = &gpll0.clkr.hw },
 191         { .hw = &gpll7.clkr.hw },
 192         { .hw = &gpll0_out_even.clkr.hw },
 193         { .fw_name = "core_bi_pll_test_se" },
 194 };
 195
 196 static const struct parent_map gcc_parent_map_6[] = {
 197         { P_BI_TCXO, 0 },
 198         { P_GPLL0_OUT_MAIN, 1 },
 199         { P_GPLL9_OUT_MAIN, 2 },
 200         { P_GPLL0_OUT_EVEN, 6 },
 201         { P_CORE_BI_PLL_TEST_SE, 7 },
 202 };
 203
 204 static const struct clk_parent_data gcc_parents_6[] = {
 205         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 206         { .hw = &gpll0.clkr.hw },
 207         { .hw = &gpll9.clkr.hw },
 208         { .hw = &gpll0_out_even.clkr.hw },
 209         { .fw_name = "core_bi_pll_test_se" },
 210 };
 211
 212 static const struct parent_map gcc_parent_map_7[] = {
 213         { P_BI_TCXO, 0 },
 214         { P_GPLL0_OUT_MAIN, 1 },
 215         { P_AUD_REF_CLK, 2 },
 216         { P_GPLL0_OUT_EVEN, 6 },
 217         { P_CORE_BI_PLL_TEST_SE, 7 },
 218 };
 219
 220 static const struct clk_parent_data gcc_parents_7[] = {
 221         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 222         { .hw = &gpll0.clkr.hw },
 223         { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
 224         { .hw = &gpll0_out_even.clkr.hw },
 225         { .fw_name = "core_bi_pll_test_se" },
 226 };
 227
 228 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 229         F(19200000, P_BI_TCXO, 1, 0, 0),
 230         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 231         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 232         { }
 233 };
 234
 235 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 236         .cmd_rcgr = 0x48014,
 237         .mnd_width = 0,
 238         .hid_width = 5,
 239         .parent_map = gcc_parent_map_0,
 240         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 241         .clkr.hw.init = &(struct clk_init_data){
 242                 .name = "gcc_cpuss_ahb_clk_src",
 243                 .parent_data = gcc_parents_0,
 244                 .num_parents = 4,
 245                 .flags = CLK_SET_RATE_PARENT,
 246                 .ops = &clk_rcg2_ops,
 247         },
 248 };
 249
 250 static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
 251         F(19200000, P_BI_TCXO, 1, 0, 0),
 252         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 253         F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 254         F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
 255         { }
 256 };
 257
 258 static struct clk_rcg2 gcc_emac_ptp_clk_src = {
 259         .cmd_rcgr = 0x6038,
 260         .mnd_width = 0,
 261         .hid_width = 5,
 262         .parent_map = gcc_parent_map_5,
 263         .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
 264         .clkr.hw.init = &(struct clk_init_data){
 265                 .name = "gcc_emac_ptp_clk_src",
 266                 .parent_data = gcc_parents_5,
 267                 .num_parents = 5,
 268                 .flags = CLK_SET_RATE_PARENT,
 269                 .ops = &clk_rcg2_ops,
 270         },
 271 };
 272
 273 static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
 274         F(2500000, P_BI_TCXO, 1, 25, 192),
 275         F(5000000, P_BI_TCXO, 1, 25, 96),
 276         F(19200000, P_BI_TCXO, 1, 0, 0),
 277         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 278         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 279         F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 280         F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
 281         { }
 282 };
 283
 284 static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
 285         .cmd_rcgr = 0x601c,
 286         .mnd_width = 8,
 287         .hid_width = 5,
 288         .parent_map = gcc_parent_map_5,
 289         .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
 290         .clkr.hw.init = &(struct clk_init_data){
 291                 .name = "gcc_emac_rgmii_clk_src",
 292                 .parent_data = gcc_parents_5,
 293                 .num_parents = 5,
 294                 .flags = CLK_SET_RATE_PARENT,
 295                 .ops = &clk_rcg2_ops,
 296         },
 297 };
 298
 299 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 300         F(19200000, P_BI_TCXO, 1, 0, 0),
 301         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 302         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 303         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 304         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 305         { }
 306 };
 307
 308 static struct clk_rcg2 gcc_gp1_clk_src = {
 309         .cmd_rcgr = 0x64004,
 310         .mnd_width = 8,
 311         .hid_width = 5,
 312         .parent_map = gcc_parent_map_1,
 313         .freq_tbl = ftbl_gcc_gp1_clk_src,
 314         .clkr.hw.init = &(struct clk_init_data){
 315                 .name = "gcc_gp1_clk_src",
 316                 .parent_data = gcc_parents_1,
 317                 .num_parents = 5,
 318                 .flags = CLK_SET_RATE_PARENT,
 319                 .ops = &clk_rcg2_ops,
 320         },
 321 };
 322
 323 static struct clk_rcg2 gcc_gp2_clk_src = {
 324         .cmd_rcgr = 0x65004,
 325         .mnd_width = 8,
 326         .hid_width = 5,
 327         .parent_map = gcc_parent_map_1,
 328         .freq_tbl = ftbl_gcc_gp1_clk_src,
 329         .clkr.hw.init = &(struct clk_init_data){
 330                 .name = "gcc_gp2_clk_src",
 331                 .parent_data = gcc_parents_1,
 332                 .num_parents = 5,
 333                 .flags = CLK_SET_RATE_PARENT,
 334                 .ops = &clk_rcg2_ops,
 335         },
 336 };
 337
 338 static struct clk_rcg2 gcc_gp3_clk_src = {
 339         .cmd_rcgr = 0x66004,
 340         .mnd_width = 8,
 341         .hid_width = 5,
 342         .parent_map = gcc_parent_map_1,
 343         .freq_tbl = ftbl_gcc_gp1_clk_src,
 344         .clkr.hw.init = &(struct clk_init_data){
 345                 .name = "gcc_gp3_clk_src",
 346                 .parent_data = gcc_parents_1,
 347                 .num_parents = 5,
 348                 .flags = CLK_SET_RATE_PARENT,
 349                 .ops = &clk_rcg2_ops,
 350         },
 351 };
 352
 353 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 354         F(9600000, P_BI_TCXO, 2, 0, 0),
 355         F(19200000, P_BI_TCXO, 1, 0, 0),
 356         { }
 357 };
 358
 359 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 360         .cmd_rcgr = 0x6b02c,
 361         .mnd_width = 16,
 362         .hid_width = 5,
 363         .parent_map = gcc_parent_map_2,
 364         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 365         .clkr.hw.init = &(struct clk_init_data){
 366                 .name = "gcc_pcie_0_aux_clk_src",
 367                 .parent_data = gcc_parents_2,
 368                 .num_parents = 3,
 369                 .flags = CLK_SET_RATE_PARENT,
 370                 .ops = &clk_rcg2_ops,
 371         },
 372 };
 373
 374 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 375         .cmd_rcgr = 0x8d02c,
 376         .mnd_width = 16,
 377         .hid_width = 5,
 378         .parent_map = gcc_parent_map_2,
 379         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 380         .clkr.hw.init = &(struct clk_init_data){
 381                 .name = "gcc_pcie_1_aux_clk_src",
 382                 .parent_data = gcc_parents_2,
 383                 .num_parents = 3,
 384                 .flags = CLK_SET_RATE_PARENT,
 385                 .ops = &clk_rcg2_ops,
 386         },
 387 };
 388
 389 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
 390         F(19200000, P_BI_TCXO, 1, 0, 0),
 391         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 392         { }
 393 };
 394
 395 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
 396         .cmd_rcgr = 0x6f014,
 397         .mnd_width = 0,
 398         .hid_width = 5,
 399         .parent_map = gcc_parent_map_0,
 400         .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
 401         .clkr.hw.init = &(struct clk_init_data){
 402                 .name = "gcc_pcie_phy_refgen_clk_src",
 403                 .parent_data = gcc_parents_0,
 404                 .num_parents = 4,
 405                 .flags = CLK_SET_RATE_PARENT,
 406                 .ops = &clk_rcg2_ops,
 407         },
 408 };
 409
 410 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 411         F(9600000, P_BI_TCXO, 2, 0, 0),
 412         F(19200000, P_BI_TCXO, 1, 0, 0),
 413         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 414         { }
 415 };
 416
 417 static struct clk_rcg2 gcc_pdm2_clk_src = {
 418         .cmd_rcgr = 0x33010,
 419         .mnd_width = 0,
 420         .hid_width = 5,
 421         .parent_map = gcc_parent_map_0,
 422         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 423         .clkr.hw.init = &(struct clk_init_data){
 424                 .name = "gcc_pdm2_clk_src",
 425                 .parent_data = gcc_parents_0,
 426                 .num_parents = 4,
 427                 .flags = CLK_SET_RATE_PARENT,
 428                 .ops = &clk_rcg2_ops,
 429         },
 430 };
 431
 432 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
 433         F(19200000, P_BI_TCXO, 1, 0, 0),
 434         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 435         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 436         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 437         { }
 438 };
 439
 440 static struct clk_rcg2 gcc_qspi_core_clk_src = {
 441         .cmd_rcgr = 0x4b008,
 442         .mnd_width = 0,
 443         .hid_width = 5,
 444         .parent_map = gcc_parent_map_0,
 445         .freq_tbl = ftbl_gcc_qspi_core_clk_src,
 446         .clkr.hw.init = &(struct clk_init_data){
 447                 .name = "gcc_qspi_core_clk_src",
 448                 .parent_data = gcc_parents_0,
 449                 .num_parents = 4,
 450                 .flags = CLK_SET_RATE_PARENT,
 451                 .ops = &clk_rcg2_ops,
 452         },
 453 };
 454
 455 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 456         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 457         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 458         F(19200000, P_BI_TCXO, 1, 0, 0),
 459         F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 460         F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 461         F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 462         F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 463         F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 464         F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 465         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 466         F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 467         F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 468         F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 469         F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 470         F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
 471         { }
 472 };
 473
 474 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 475         .cmd_rcgr = 0x17148,
 476         .mnd_width = 16,
 477         .hid_width = 5,
 478         .parent_map = gcc_parent_map_0,
 479         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 480         .clkr.hw.init = &(struct clk_init_data){
 481                 .name = "gcc_qupv3_wrap0_s0_clk_src",
 482                 .parent_data = gcc_parents_0,
 483                 .num_parents = 4,
 484                 .flags = CLK_SET_RATE_PARENT,
 485                 .ops = &clk_rcg2_ops,
 486         },
 487 };
 488
 489 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 490         .cmd_rcgr = 0x17278,
 491         .mnd_width = 16,
 492         .hid_width = 5,
 493         .parent_map = gcc_parent_map_0,
 494         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 495         .clkr.hw.init = &(struct clk_init_data){
 496                 .name = "gcc_qupv3_wrap0_s1_clk_src",
 497                 .parent_data = gcc_parents_0,
 498                 .num_parents = 4,
 499                 .flags = CLK_SET_RATE_PARENT,
 500                 .ops = &clk_rcg2_ops,
 501         },
 502 };
 503
 504 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 505         .cmd_rcgr = 0x173a8,
 506         .mnd_width = 16,
 507         .hid_width = 5,
 508         .parent_map = gcc_parent_map_0,
 509         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 510         .clkr.hw.init = &(struct clk_init_data){
 511                 .name = "gcc_qupv3_wrap0_s2_clk_src",
 512                 .parent_data = gcc_parents_0,
 513                 .num_parents = 4,
 514                 .flags = CLK_SET_RATE_PARENT,
 515                 .ops = &clk_rcg2_ops,
 516         },
 517 };
 518
 519 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 520         .cmd_rcgr = 0x174d8,
 521         .mnd_width = 16,
 522         .hid_width = 5,
 523         .parent_map = gcc_parent_map_0,
 524         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 525         .clkr.hw.init = &(struct clk_init_data){
 526                 .name = "gcc_qupv3_wrap0_s3_clk_src",
 527                 .parent_data = gcc_parents_0,
 528                 .num_parents = 4,
 529                 .flags = CLK_SET_RATE_PARENT,
 530                 .ops = &clk_rcg2_ops,
 531         },
 532 };
 533
 534 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 535         .cmd_rcgr = 0x17608,
 536         .mnd_width = 16,
 537         .hid_width = 5,
 538         .parent_map = gcc_parent_map_0,
 539         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 540         .clkr.hw.init = &(struct clk_init_data){
 541                 .name = "gcc_qupv3_wrap0_s4_clk_src",
 542                 .parent_data = gcc_parents_0,
 543                 .num_parents = 4,
 544                 .flags = CLK_SET_RATE_PARENT,
 545                 .ops = &clk_rcg2_ops,
 546         },
 547 };
 548
 549 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 550         .cmd_rcgr = 0x17738,
 551         .mnd_width = 16,
 552         .hid_width = 5,
 553         .parent_map = gcc_parent_map_0,
 554         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 555         .clkr.hw.init = &(struct clk_init_data){
 556                 .name = "gcc_qupv3_wrap0_s5_clk_src",
 557                 .parent_data = gcc_parents_0,
 558                 .num_parents = 4,
 559                 .flags = CLK_SET_RATE_PARENT,
 560                 .ops = &clk_rcg2_ops,
 561         },
 562 };
 563
 564 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 565         .cmd_rcgr = 0x17868,
 566         .mnd_width = 16,
 567         .hid_width = 5,
 568         .parent_map = gcc_parent_map_0,
 569         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 570         .clkr.hw.init = &(struct clk_init_data){
 571                 .name = "gcc_qupv3_wrap0_s6_clk_src",
 572                 .parent_data = gcc_parents_0,
 573                 .num_parents = 4,
 574                 .flags = CLK_SET_RATE_PARENT,
 575                 .ops = &clk_rcg2_ops,
 576         },
 577 };
 578
 579 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 580         .cmd_rcgr = 0x17998,
 581         .mnd_width = 16,
 582         .hid_width = 5,
 583         .parent_map = gcc_parent_map_0,
 584         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 585         .clkr.hw.init = &(struct clk_init_data){
 586                 .name = "gcc_qupv3_wrap0_s7_clk_src",
 587                 .parent_data = gcc_parents_0,
 588                 .num_parents = 4,
 589                 .flags = CLK_SET_RATE_PARENT,
 590                 .ops = &clk_rcg2_ops,
 591         },
 592 };
 593
 594 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 595         .cmd_rcgr = 0x18148,
 596         .mnd_width = 16,
 597         .hid_width = 5,
 598         .parent_map = gcc_parent_map_0,
 599         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 600         .clkr.hw.init = &(struct clk_init_data){
 601                 .name = "gcc_qupv3_wrap1_s0_clk_src",
 602                 .parent_data = gcc_parents_0,
 603                 .num_parents = 4,
 604                 .flags = CLK_SET_RATE_PARENT,
 605                 .ops = &clk_rcg2_ops,
 606         },
 607 };
 608
 609 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 610         .cmd_rcgr = 0x18278,
 611         .mnd_width = 16,
 612         .hid_width = 5,
 613         .parent_map = gcc_parent_map_0,
 614         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 615         .clkr.hw.init = &(struct clk_init_data){
 616                 .name = "gcc_qupv3_wrap1_s1_clk_src",
 617                 .parent_data = gcc_parents_0,
 618                 .num_parents = 4,
 619                 .flags = CLK_SET_RATE_PARENT,
 620                 .ops = &clk_rcg2_ops,
 621         },
 622 };
 623
 624 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 625         .cmd_rcgr = 0x183a8,
 626         .mnd_width = 16,
 627         .hid_width = 5,
 628         .parent_map = gcc_parent_map_0,
 629         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 630         .clkr.hw.init = &(struct clk_init_data){
 631                 .name = "gcc_qupv3_wrap1_s2_clk_src",
 632                 .parent_data = gcc_parents_0,
 633                 .num_parents = 4,
 634                 .flags = CLK_SET_RATE_PARENT,
 635                 .ops = &clk_rcg2_ops,
 636         },
 637 };
 638
 639 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 640         .cmd_rcgr = 0x184d8,
 641         .mnd_width = 16,
 642         .hid_width = 5,
 643         .parent_map = gcc_parent_map_0,
 644         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 645         .clkr.hw.init = &(struct clk_init_data){
 646                 .name = "gcc_qupv3_wrap1_s3_clk_src",
 647                 .parent_data = gcc_parents_0,
 648                 .num_parents = 4,
 649                 .flags = CLK_SET_RATE_PARENT,
 650                 .ops = &clk_rcg2_ops,
 651         },
 652 };
 653
 654 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 655         .cmd_rcgr = 0x18608,
 656         .mnd_width = 16,
 657         .hid_width = 5,
 658         .parent_map = gcc_parent_map_0,
 659         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 660         .clkr.hw.init = &(struct clk_init_data){
 661                 .name = "gcc_qupv3_wrap1_s4_clk_src",
 662                 .parent_data = gcc_parents_0,
 663                 .num_parents = 4,
 664                 .flags = CLK_SET_RATE_PARENT,
 665                 .ops = &clk_rcg2_ops,
 666         },
 667 };
 668
 669 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 670         .cmd_rcgr = 0x18738,
 671         .mnd_width = 16,
 672         .hid_width = 5,
 673         .parent_map = gcc_parent_map_0,
 674         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 675         .clkr.hw.init = &(struct clk_init_data){
 676                 .name = "gcc_qupv3_wrap1_s5_clk_src",
 677                 .parent_data = gcc_parents_0,
 678                 .num_parents = 4,
 679                 .flags = CLK_SET_RATE_PARENT,
 680                 .ops = &clk_rcg2_ops,
 681         },
 682 };
 683
 684 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
 685         .cmd_rcgr = 0x1e148,
 686         .mnd_width = 16,
 687         .hid_width = 5,
 688         .parent_map = gcc_parent_map_0,
 689         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 690         .clkr.hw.init = &(struct clk_init_data){
 691                 .name = "gcc_qupv3_wrap2_s0_clk_src",
 692                 .parent_data = gcc_parents_0,
 693                 .num_parents = 4,
 694                 .flags = CLK_SET_RATE_PARENT,
 695                 .ops = &clk_rcg2_ops,
 696         },
 697 };
 698
 699 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
 700         .cmd_rcgr = 0x1e278,
 701         .mnd_width = 16,
 702         .hid_width = 5,
 703         .parent_map = gcc_parent_map_0,
 704         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 705         .clkr.hw.init = &(struct clk_init_data){
 706                 .name = "gcc_qupv3_wrap2_s1_clk_src",
 707                 .parent_data = gcc_parents_0,
 708                 .num_parents = 4,
 709                 .flags = CLK_SET_RATE_PARENT,
 710                 .ops = &clk_rcg2_ops,
 711         },
 712 };
 713
 714 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
 715         .cmd_rcgr = 0x1e3a8,
 716         .mnd_width = 16,
 717         .hid_width = 5,
 718         .parent_map = gcc_parent_map_0,
 719         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 720         .clkr.hw.init = &(struct clk_init_data){
 721                 .name = "gcc_qupv3_wrap2_s2_clk_src",
 722                 .parent_data = gcc_parents_0,
 723                 .num_parents = 4,
 724                 .flags = CLK_SET_RATE_PARENT,
 725                 .ops = &clk_rcg2_ops,
 726         },
 727 };
 728
 729 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
 730         .cmd_rcgr = 0x1e4d8,
 731         .mnd_width = 16,
 732         .hid_width = 5,
 733         .parent_map = gcc_parent_map_0,
 734         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 735         .clkr.hw.init = &(struct clk_init_data){
 736                 .name = "gcc_qupv3_wrap2_s3_clk_src",
 737                 .parent_data = gcc_parents_0,
 738                 .num_parents = 4,
 739                 .flags = CLK_SET_RATE_PARENT,
 740                 .ops = &clk_rcg2_ops,
 741         },
 742 };
 743
 744 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
 745         .cmd_rcgr = 0x1e608,
 746         .mnd_width = 16,
 747         .hid_width = 5,
 748         .parent_map = gcc_parent_map_0,
 749         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 750         .clkr.hw.init = &(struct clk_init_data){
 751                 .name = "gcc_qupv3_wrap2_s4_clk_src",
 752                 .parent_data = gcc_parents_0,
 753                 .num_parents = 4,
 754                 .flags = CLK_SET_RATE_PARENT,
 755                 .ops = &clk_rcg2_ops,
 756         },
 757 };
 758
 759 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
 760         .cmd_rcgr = 0x1e738,
 761         .mnd_width = 16,
 762         .hid_width = 5,
 763         .parent_map = gcc_parent_map_0,
 764         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 765         .clkr.hw.init = &(struct clk_init_data){
 766                 .name = "gcc_qupv3_wrap2_s5_clk_src",
 767                 .parent_data = gcc_parents_0,
 768                 .num_parents = 4,
 769                 .flags = CLK_SET_RATE_PARENT,
 770                 .ops = &clk_rcg2_ops,
 771         },
 772 };
 773
 774 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 775         F(400000, P_BI_TCXO, 12, 1, 4),
 776         F(9600000, P_BI_TCXO, 2, 0, 0),
 777         F(19200000, P_BI_TCXO, 1, 0, 0),
 778         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 779         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 780         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 781         F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
 782         { }
 783 };
 784
 785 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 786         .cmd_rcgr = 0x1400c,
 787         .mnd_width = 8,
 788         .hid_width = 5,
 789         .parent_map = gcc_parent_map_6,
 790         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 791         .clkr.hw.init = &(struct clk_init_data){
 792                 .name = "gcc_sdcc2_apps_clk_src",
 793                 .parent_data = gcc_parents_6,
 794                 .num_parents = 5,
 795                 .flags = CLK_SET_RATE_PARENT,
 796                 .ops = &clk_rcg2_floor_ops,
 797         },
 798 };
 799
 800 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
 801         F(400000, P_BI_TCXO, 12, 1, 4),
 802         F(9600000, P_BI_TCXO, 2, 0, 0),
 803         F(19200000, P_BI_TCXO, 1, 0, 0),
 804         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 805         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 806         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 807         { }
 808 };
 809
 810 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 811         .cmd_rcgr = 0x1600c,
 812         .mnd_width = 8,
 813         .hid_width = 5,
 814         .parent_map = gcc_parent_map_3,
 815         .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
 816         .clkr.hw.init = &(struct clk_init_data){
 817                 .name = "gcc_sdcc4_apps_clk_src",
 818                 .parent_data = gcc_parents_3,
 819                 .num_parents = 3,
 820                 .flags = CLK_SET_RATE_PARENT,
 821                 .ops = &clk_rcg2_floor_ops,
 822         },
 823 };
 824
 825 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
 826         F(105495, P_BI_TCXO, 2, 1, 91),
 827         { }
 828 };
 829
 830 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
 831         .cmd_rcgr = 0x36010,
 832         .mnd_width = 8,
 833         .hid_width = 5,
 834         .parent_map = gcc_parent_map_7,
 835         .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
 836         .clkr.hw.init = &(struct clk_init_data){
 837                 .name = "gcc_tsif_ref_clk_src",
 838                 .parent_data = gcc_parents_7,
 839                 .num_parents = 5,
 840                 .flags = CLK_SET_RATE_PARENT,
 841                 .ops = &clk_rcg2_ops,
 842         },
 843 };
 844
 845 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
 846         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 847         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 848         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 849         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 850         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 851         { }
 852 };
 853
 854 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
 855         .cmd_rcgr = 0x75020,
 856         .mnd_width = 8,
 857         .hid_width = 5,
 858         .parent_map = gcc_parent_map_0,
 859         .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
 860         .clkr.hw.init = &(struct clk_init_data){
 861                 .name = "gcc_ufs_card_axi_clk_src",
 862                 .parent_data = gcc_parents_0,
 863                 .num_parents = 4,
 864                 .flags = CLK_SET_RATE_PARENT,
 865                 .ops = &clk_rcg2_ops,
 866         },
 867 };
 868
 869 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
 870         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 871         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 872         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 873         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 874         { }
 875 };
 876
 877 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
 878         .cmd_rcgr = 0x75060,
 879         .mnd_width = 0,
 880         .hid_width = 5,
 881         .parent_map = gcc_parent_map_0,
 882         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 883         .clkr.hw.init = &(struct clk_init_data){
 884                 .name = "gcc_ufs_card_ice_core_clk_src",
 885                 .parent_data = gcc_parents_0,
 886                 .num_parents = 4,
 887                 .flags = CLK_SET_RATE_PARENT,
 888                 .ops = &clk_rcg2_ops,
 889         },
 890 };
 891
 892 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
 893         F(19200000, P_BI_TCXO, 1, 0, 0),
 894         { }
 895 };
 896
 897 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
 898         .cmd_rcgr = 0x75094,
 899         .mnd_width = 0,
 900         .hid_width = 5,
 901         .parent_map = gcc_parent_map_4,
 902         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
 903         .clkr.hw.init = &(struct clk_init_data){
 904                 .name = "gcc_ufs_card_phy_aux_clk_src",
 905                 .parent_data = gcc_parents_4,
 906                 .num_parents = 2,
 907                 .flags = CLK_SET_RATE_PARENT,
 908                 .ops = &clk_rcg2_ops,
 909         },
 910 };
 911
 912 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
 913         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 914         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 915         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 916         { }
 917 };
 918
 919 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
 920         .cmd_rcgr = 0x75078,
 921         .mnd_width = 0,
 922         .hid_width = 5,
 923         .parent_map = gcc_parent_map_0,
 924         .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
 925         .clkr.hw.init = &(struct clk_init_data){
 926                 .name = "gcc_ufs_card_unipro_core_clk_src",
 927                 .parent_data = gcc_parents_0,
 928                 .num_parents = 4,
 929                 .flags = CLK_SET_RATE_PARENT,
 930                 .ops = &clk_rcg2_ops,
 931         },
 932 };
 933
 934 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 935         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 936         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 937         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 938         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 939         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 940         { }
 941 };
 942
 943 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 944         .cmd_rcgr = 0x77020,
 945         .mnd_width = 8,
 946         .hid_width = 5,
 947         .parent_map = gcc_parent_map_0,
 948         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 949         .clkr.hw.init = &(struct clk_init_data){
 950                 .name = "gcc_ufs_phy_axi_clk_src",
 951                 .parent_data = gcc_parents_0,
 952                 .num_parents = 4,
 953                 .flags = CLK_SET_RATE_PARENT,
 954                 .ops = &clk_rcg2_ops,
 955         },
 956 };
 957
 958 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
 959         .cmd_rcgr = 0x77060,
 960         .mnd_width = 0,
 961         .hid_width = 5,
 962         .parent_map = gcc_parent_map_0,
 963         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 964         .clkr.hw.init = &(struct clk_init_data){
 965                 .name = "gcc_ufs_phy_ice_core_clk_src",
 966                 .parent_data = gcc_parents_0,
 967                 .num_parents = 4,
 968                 .flags = CLK_SET_RATE_PARENT,
 969                 .ops = &clk_rcg2_ops,
 970         },
 971 };
 972
 973 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 974         .cmd_rcgr = 0x77094,
 975         .mnd_width = 0,
 976         .hid_width = 5,
 977         .parent_map = gcc_parent_map_4,
 978         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 979         .clkr.hw.init = &(struct clk_init_data){
 980                 .name = "gcc_ufs_phy_phy_aux_clk_src",
 981                 .parent_data = gcc_parents_4,
 982                 .num_parents = 2,
 983                 .flags = CLK_SET_RATE_PARENT,
 984                 .ops = &clk_rcg2_ops,
 985         },
 986 };
 987
 988 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 989         .cmd_rcgr = 0x77078,
 990         .mnd_width = 0,
 991         .hid_width = 5,
 992         .parent_map = gcc_parent_map_0,
 993         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 994         .clkr.hw.init = &(struct clk_init_data){
 995                 .name = "gcc_ufs_phy_unipro_core_clk_src",
 996                 .parent_data = gcc_parents_0,
 997                 .num_parents = 4,
 998                 .flags = CLK_SET_RATE_PARENT,
 999                 .ops = &clk_rcg2_ops,
1000         },
1001 };
1002
1003 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1004         F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1005         F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1006         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1007         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1008         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1009         { }
1010 };
1011
1012 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1013         .cmd_rcgr = 0xf01c,
1014         .mnd_width = 8,
1015         .hid_width = 5,
1016         .parent_map = gcc_parent_map_0,
1017         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1018         .clkr.hw.init = &(struct clk_init_data){
1019                 .name = "gcc_usb30_prim_master_clk_src",
1020                 .parent_data = gcc_parents_0,
1021                 .num_parents = 4,
1022                 .flags = CLK_SET_RATE_PARENT,
1023                 .ops = &clk_rcg2_ops,
1024         },
1025 };
1026
1027 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1028         F(19200000, P_BI_TCXO, 1, 0, 0),
1029         F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1030         F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1031         { }
1032 };
1033
1034 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1035         .cmd_rcgr = 0xf034,
1036         .mnd_width = 0,
1037         .hid_width = 5,
1038         .parent_map = gcc_parent_map_0,
1039         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1040         .clkr.hw.init = &(struct clk_init_data){
1041                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1042                 .parent_data = gcc_parents_0,
1043                 .num_parents = 4,
1044                 .flags = CLK_SET_RATE_PARENT,
1045                 .ops = &clk_rcg2_ops,
1046         },
1047 };
1048
1049 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1050         .cmd_rcgr = 0x1001c,
1051         .mnd_width = 8,
1052         .hid_width = 5,
1053         .parent_map = gcc_parent_map_0,
1054         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1055         .clkr.hw.init = &(struct clk_init_data){
1056                 .name = "gcc_usb30_sec_master_clk_src",
1057                 .parent_data = gcc_parents_0,
1058                 .num_parents = 4,
1059                 .flags = CLK_SET_RATE_PARENT,
1060                 .ops = &clk_rcg2_ops,
1061         },
1062 };
1063
1064 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1065         .cmd_rcgr = 0x10034,
1066         .mnd_width = 0,
1067         .hid_width = 5,
1068         .parent_map = gcc_parent_map_0,
1069         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1070         .clkr.hw.init = &(struct clk_init_data){
1071                 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1072                 .parent_data = gcc_parents_0,
1073                 .num_parents = 4,
1074                 .flags = CLK_SET_RATE_PARENT,
1075                 .ops = &clk_rcg2_ops,
1076         },
1077 };
1078
1079 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1080         .cmd_rcgr = 0xf060,
1081         .mnd_width = 0,
1082         .hid_width = 5,
1083         .parent_map = gcc_parent_map_2,
1084         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1085         .clkr.hw.init = &(struct clk_init_data){
1086                 .name = "gcc_usb3_prim_phy_aux_clk_src",
1087                 .parent_data = gcc_parents_2,
1088                 .num_parents = 3,
1089                 .flags = CLK_SET_RATE_PARENT,
1090                 .ops = &clk_rcg2_ops,
1091         },
1092 };
1093
1094 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1095         .cmd_rcgr = 0x10060,
1096         .mnd_width = 0,
1097         .hid_width = 5,
1098         .parent_map = gcc_parent_map_2,
1099         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1100         .clkr.hw.init = &(struct clk_init_data){
1101                 .name = "gcc_usb3_sec_phy_aux_clk_src",
1102                 .parent_data = gcc_parents_2,
1103                 .num_parents = 3,
1104                 .flags = CLK_SET_RATE_PARENT,
1105                 .ops = &clk_rcg2_ops,
1106         },
1107 };
1108
1109 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1110         .halt_reg = 0x90018,
1111         .halt_check = BRANCH_HALT,
1112         .clkr = {
1113                 .enable_reg = 0x90018,
1114                 .enable_mask = BIT(0),
1115                 .hw.init = &(struct clk_init_data){
1116                         .name = "gcc_aggre_noc_pcie_tbu_clk",
1117                         .ops = &clk_branch2_ops,
1118                 },
1119         },
1120 };
1121
1122 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1123         .halt_reg = 0x750c0,
1124         .halt_check = BRANCH_HALT,
1125         .hwcg_reg = 0x750c0,
1126         .hwcg_bit = 1,
1127         .clkr = {
1128                 .enable_reg = 0x750c0,
1129                 .enable_mask = BIT(0),
1130                 .hw.init = &(struct clk_init_data){
1131                         .name = "gcc_aggre_ufs_card_axi_clk",
1132                         .parent_hws = (const struct clk_hw *[]){
1133                                       &gcc_ufs_card_axi_clk_src.clkr.hw },
1134                         .num_parents = 1,
1135                         .flags = CLK_SET_RATE_PARENT,
1136                         .ops = &clk_branch2_ops,
1137                 },
1138         },
1139 };
1140
1141 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1142         .halt_reg = 0x750c0,
1143         .halt_check = BRANCH_HALT,
1144         .hwcg_reg = 0x750c0,
1145         .hwcg_bit = 1,
1146         .clkr = {
1147                 .enable_reg = 0x750c0,
1148                 .enable_mask = BIT(1),
1149                 .hw.init = &(struct clk_init_data){
1150                         .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1151                         .parent_hws = (const struct clk_hw *[]){
1152                                       &gcc_aggre_ufs_card_axi_clk.clkr.hw },
1153                         .num_parents = 1,
1154                         .flags = CLK_SET_RATE_PARENT,
1155                         .ops = &clk_branch_simple_ops,
1156                 },
1157         },
1158 };
1159
1160 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1161         .halt_reg = 0x770c0,
1162         .halt_check = BRANCH_HALT,
1163         .hwcg_reg = 0x770c0,
1164         .hwcg_bit = 1,
1165         .clkr = {
1166                 .enable_reg = 0x770c0,
1167                 .enable_mask = BIT(0),
1168                 .hw.init = &(struct clk_init_data){
1169                         .name = "gcc_aggre_ufs_phy_axi_clk",
1170                         .parent_hws = (const struct clk_hw *[]){
1171                                       &gcc_ufs_phy_axi_clk_src.clkr.hw },
1172                         .num_parents = 1,
1173                         .flags = CLK_SET_RATE_PARENT,
1174                         .ops = &clk_branch2_ops,
1175                 },
1176         },
1177 };
1178
1179 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1180         .halt_reg = 0x770c0,
1181         .halt_check = BRANCH_HALT,
1182         .hwcg_reg = 0x770c0,
1183         .hwcg_bit = 1,
1184         .clkr = {
1185                 .enable_reg = 0x770c0,
1186                 .enable_mask = BIT(1),
1187                 .hw.init = &(struct clk_init_data){
1188                         .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1189                         .parent_hws = (const struct clk_hw *[]){
1190                                       &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
1191                         .num_parents = 1,
1192                         .flags = CLK_SET_RATE_PARENT,
1193                         .ops = &clk_branch_simple_ops,
1194                 },
1195         },
1196 };
1197
1198 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1199         .halt_reg = 0xf07c,
1200         .halt_check = BRANCH_HALT,
1201         .clkr = {
1202                 .enable_reg = 0xf07c,
1203                 .enable_mask = BIT(0),
1204                 .hw.init = &(struct clk_init_data){
1205                         .name = "gcc_aggre_usb3_prim_axi_clk",
1206                         .parent_hws = (const struct clk_hw *[]){
1207                                       &gcc_usb30_prim_master_clk_src.clkr.hw },
1208                         .num_parents = 1,
1209                         .flags = CLK_SET_RATE_PARENT,
1210                         .ops = &clk_branch2_ops,
1211                 },
1212         },
1213 };
1214
1215 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1216         .halt_reg = 0x1007c,
1217         .halt_check = BRANCH_HALT,
1218         .clkr = {
1219                 .enable_reg = 0x1007c,
1220                 .enable_mask = BIT(0),
1221                 .hw.init = &(struct clk_init_data){
1222                         .name = "gcc_aggre_usb3_sec_axi_clk",
1223                         .parent_hws = (const struct clk_hw *[]){
1224                                       &gcc_usb30_sec_master_clk_src.clkr.hw },
1225                         .num_parents = 1,
1226                         .flags = CLK_SET_RATE_PARENT,
1227                         .ops = &clk_branch2_ops,
1228                 },
1229         },
1230 };
1231
1232 static struct clk_branch gcc_boot_rom_ahb_clk = {
1233         .halt_reg = 0x38004,
1234         .halt_check = BRANCH_HALT_VOTED,
1235         .hwcg_reg = 0x38004,
1236         .hwcg_bit = 1,
1237         .clkr = {
1238                 .enable_reg = 0x52004,
1239                 .enable_mask = BIT(10),
1240                 .hw.init = &(struct clk_init_data){
1241                         .name = "gcc_boot_rom_ahb_clk",
1242                         .ops = &clk_branch2_ops,
1243                 },
1244         },
1245 };
1246
1247 /*
1248  * Clock ON depends on external parent 'config noc', so cant poll
1249  * delay and also mark as crtitical for camss boot
1250  */
1251 static struct clk_branch gcc_camera_ahb_clk = {
1252         .halt_reg = 0xb008,
1253         .halt_check = BRANCH_HALT_DELAY,
1254         .hwcg_reg = 0xb008,
1255         .hwcg_bit = 1,
1256         .clkr = {
1257                 .enable_reg = 0xb008,
1258                 .enable_mask = BIT(0),
1259                 .hw.init = &(struct clk_init_data){
1260                         .name = "gcc_camera_ahb_clk",
1261                         .flags = CLK_IS_CRITICAL,
1262                         .ops = &clk_branch2_ops,
1263                 },
1264         },
1265 };
1266
1267 static struct clk_branch gcc_camera_hf_axi_clk = {
1268         .halt_reg = 0xb030,
1269         .halt_check = BRANCH_HALT,
1270         .clkr = {
1271                 .enable_reg = 0xb030,
1272                 .enable_mask = BIT(0),
1273                 .hw.init = &(struct clk_init_data){
1274                         .name = "gcc_camera_hf_axi_clk",
1275                         .ops = &clk_branch2_ops,
1276                 },
1277         },
1278 };
1279
1280 static struct clk_branch gcc_camera_sf_axi_clk = {
1281         .halt_reg = 0xb034,
1282         .halt_check = BRANCH_HALT,
1283         .clkr = {
1284                 .enable_reg = 0xb034,
1285                 .enable_mask = BIT(0),
1286                 .hw.init = &(struct clk_init_data){
1287                         .name = "gcc_camera_sf_axi_clk",
1288                         .ops = &clk_branch2_ops,
1289                 },
1290         },
1291 };
1292
1293 /* XO critical input to camss, so no need to poll */
1294 static struct clk_branch gcc_camera_xo_clk = {
1295         .halt_reg = 0xb044,
1296         .halt_check = BRANCH_HALT_DELAY,
1297         .clkr = {
1298                 .enable_reg = 0xb044,
1299                 .enable_mask = BIT(0),
1300                 .hw.init = &(struct clk_init_data){
1301                         .name = "gcc_camera_xo_clk",
1302                         .flags = CLK_IS_CRITICAL,
1303                         .ops = &clk_branch2_ops,
1304                 },
1305         },
1306 };
1307
1308 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1309         .halt_reg = 0xf078,
1310         .halt_check = BRANCH_HALT,
1311         .clkr = {
1312                 .enable_reg = 0xf078,
1313                 .enable_mask = BIT(0),
1314                 .hw.init = &(struct clk_init_data){
1315                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1316                         .parent_hws = (const struct clk_hw *[]){
1317                                       &gcc_usb30_prim_master_clk_src.clkr.hw },
1318                         .num_parents = 1,
1319                         .flags = CLK_SET_RATE_PARENT,
1320                         .ops = &clk_branch2_ops,
1321                 },
1322         },
1323 };
1324
1325 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1326         .halt_reg = 0x10078,
1327         .halt_check = BRANCH_HALT,
1328         .clkr = {
1329                 .enable_reg = 0x10078,
1330                 .enable_mask = BIT(0),
1331                 .hw.init = &(struct clk_init_data){
1332                         .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1333                         .parent_hws = (const struct clk_hw *[]){
1334                                       &gcc_usb30_sec_master_clk_src.clkr.hw },
1335                         .num_parents = 1,
1336                         .flags = CLK_SET_RATE_PARENT,
1337                         .ops = &clk_branch2_ops,
1338                 },
1339         },
1340 };
1341
1342 static struct clk_branch gcc_cpuss_ahb_clk = {
1343         .halt_reg = 0x48000,
1344         .halt_check = BRANCH_HALT_VOTED,
1345         .clkr = {
1346                 .enable_reg = 0x52004,
1347                 .enable_mask = BIT(21),
1348                 .hw.init = &(struct clk_init_data){
1349                         .name = "gcc_cpuss_ahb_clk",
1350                         .parent_hws = (const struct clk_hw *[]){
1351                                       &gcc_cpuss_ahb_clk_src.clkr.hw },
1352                         .num_parents = 1,
1353                          /* required for cpuss */
1354                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1355                         .ops = &clk_branch2_ops,
1356                 },
1357         },
1358 };
1359
1360 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
1361         .halt_reg = 0x48190,
1362         .halt_check = BRANCH_HALT,
1363         .clkr = {
1364                 .enable_reg = 0x48190,
1365                 .enable_mask = BIT(0),
1366                 .hw.init = &(struct clk_init_data){
1367                         .name = "gcc_cpuss_dvm_bus_clk",
1368                          /* required for cpuss */
1369                         .flags = CLK_IS_CRITICAL,
1370                         .ops = &clk_branch2_ops,
1371                 },
1372         },
1373 };
1374
1375 static struct clk_branch gcc_cpuss_gnoc_clk = {
1376         .halt_reg = 0x48004,
1377         .halt_check = BRANCH_HALT_VOTED,
1378         .hwcg_reg = 0x48004,
1379         .hwcg_bit = 1,
1380         .clkr = {
1381                 .enable_reg = 0x52004,
1382                 .enable_mask = BIT(22),
1383                 .hw.init = &(struct clk_init_data){
1384                         .name = "gcc_cpuss_gnoc_clk",
1385                          /* required for cpuss */
1386                         .flags = CLK_IS_CRITICAL,
1387                         .ops = &clk_branch2_ops,
1388                 },
1389         },
1390 };
1391
1392 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1393         .halt_reg = 0x48008,
1394         .halt_check = BRANCH_HALT,
1395         .clkr = {
1396                 .enable_reg = 0x48008,
1397                 .enable_mask = BIT(0),
1398                 .hw.init = &(struct clk_init_data){
1399                         .name = "gcc_cpuss_rbcpr_clk",
1400                         .ops = &clk_branch2_ops,
1401                 },
1402         },
1403 };
1404
1405 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1406         .halt_reg = 0x71154,
1407         .halt_check = BRANCH_VOTED,
1408         .clkr = {
1409                 .enable_reg = 0x71154,
1410                 .enable_mask = BIT(0),
1411                 .hw.init = &(struct clk_init_data){
1412                         .name = "gcc_ddrss_gpu_axi_clk",
1413                         .ops = &clk_branch2_ops,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * Clock ON depends on external parent 'config noc', so cant poll
1420  * delay and also mark as crtitical for disp boot
1421  */
1422 static struct clk_branch gcc_disp_ahb_clk = {
1423         .halt_reg = 0xb00c,
1424         .halt_check = BRANCH_HALT_DELAY,
1425         .hwcg_reg = 0xb00c,
1426         .hwcg_bit = 1,
1427         .clkr = {
1428                 .enable_reg = 0xb00c,
1429                 .enable_mask = BIT(0),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "gcc_disp_ahb_clk",
1432                         .flags = CLK_IS_CRITICAL,
1433                         .ops = &clk_branch2_ops,
1434                 },
1435         },
1436 };
1437
1438 static struct clk_branch gcc_disp_hf_axi_clk = {
1439         .halt_reg = 0xb038,
1440         .halt_check = BRANCH_HALT,
1441         .clkr = {
1442                 .enable_reg = 0xb038,
1443                 .enable_mask = BIT(0),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "gcc_disp_hf_axi_clk",
1446                         .ops = &clk_branch2_ops,
1447                 },
1448         },
1449 };
1450
1451 static struct clk_branch gcc_disp_sf_axi_clk = {
1452         .halt_reg = 0xb03c,
1453         .halt_check = BRANCH_HALT,
1454         .clkr = {
1455                 .enable_reg = 0xb03c,
1456                 .enable_mask = BIT(0),
1457                 .hw.init = &(struct clk_init_data){
1458                         .name = "gcc_disp_sf_axi_clk",
1459                         .ops = &clk_branch2_ops,
1460                 },
1461         },
1462 };
1463
1464 /* XO critical input to disp, so no need to poll */
1465 static struct clk_branch gcc_disp_xo_clk = {
1466         .halt_reg = 0xb048,
1467         .halt_check = BRANCH_HALT_DELAY,
1468         .clkr = {
1469                 .enable_reg = 0xb048,
1470                 .enable_mask = BIT(0),
1471                 .hw.init = &(struct clk_init_data){
1472                         .name = "gcc_disp_xo_clk",
1473                         .flags = CLK_IS_CRITICAL,
1474                         .ops = &clk_branch2_ops,
1475                 },
1476         },
1477 };
1478
1479 static struct clk_branch gcc_emac_axi_clk = {
1480         .halt_reg = 0x6010,
1481         .halt_check = BRANCH_HALT,
1482         .clkr = {
1483                 .enable_reg = 0x6010,
1484                 .enable_mask = BIT(0),
1485                 .hw.init = &(struct clk_init_data){
1486                         .name = "gcc_emac_axi_clk",
1487                         .ops = &clk_branch2_ops,
1488                 },
1489         },
1490 };
1491
1492 static struct clk_branch gcc_emac_ptp_clk = {
1493         .halt_reg = 0x6034,
1494         .halt_check = BRANCH_HALT,
1495         .clkr = {
1496                 .enable_reg = 0x6034,
1497                 .enable_mask = BIT(0),
1498                 .hw.init = &(struct clk_init_data){
1499                         .name = "gcc_emac_ptp_clk",
1500                         .parent_hws = (const struct clk_hw *[]){
1501                                       &gcc_emac_ptp_clk_src.clkr.hw },
1502                         .num_parents = 1,
1503                         .flags = CLK_SET_RATE_PARENT,
1504                         .ops = &clk_branch2_ops,
1505                 },
1506         },
1507 };
1508
1509 static struct clk_branch gcc_emac_rgmii_clk = {
1510         .halt_reg = 0x6018,
1511         .halt_check = BRANCH_HALT,
1512         .clkr = {
1513                 .enable_reg = 0x6018,
1514                 .enable_mask = BIT(0),
1515                 .hw.init = &(struct clk_init_data){
1516                         .name = "gcc_emac_rgmii_clk",
1517                         .parent_hws = (const struct clk_hw *[]){
1518                                       &gcc_emac_rgmii_clk_src.clkr.hw },
1519                         .num_parents = 1,
1520                         .flags = CLK_SET_RATE_PARENT,
1521                         .ops = &clk_branch2_ops,
1522                 },
1523         },
1524 };
1525
1526 static struct clk_branch gcc_emac_slv_ahb_clk = {
1527         .halt_reg = 0x6014,
1528         .halt_check = BRANCH_HALT,
1529         .hwcg_reg = 0x6014,
1530         .hwcg_bit = 1,
1531         .clkr = {
1532                 .enable_reg = 0x6014,
1533                 .enable_mask = BIT(0),
1534                 .hw.init = &(struct clk_init_data){
1535                         .name = "gcc_emac_slv_ahb_clk",
1536                         .ops = &clk_branch2_ops,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_branch gcc_gp1_clk = {
1542         .halt_reg = 0x64000,
1543         .halt_check = BRANCH_HALT,
1544         .clkr = {
1545                 .enable_reg = 0x64000,
1546                 .enable_mask = BIT(0),
1547                 .hw.init = &(struct clk_init_data){
1548                         .name = "gcc_gp1_clk",
1549                         .parent_hws = (const struct clk_hw *[]){
1550                                       &gcc_gp1_clk_src.clkr.hw },
1551                         .num_parents = 1,
1552                         .flags = CLK_SET_RATE_PARENT,
1553                         .ops = &clk_branch2_ops,
1554                 },
1555         },
1556 };
1557
1558 static struct clk_branch gcc_gp2_clk = {
1559         .halt_reg = 0x65000,
1560         .halt_check = BRANCH_HALT,
1561         .clkr = {
1562                 .enable_reg = 0x65000,
1563                 .enable_mask = BIT(0),
1564                 .hw.init = &(struct clk_init_data){
1565                         .name = "gcc_gp2_clk",
1566                         .parent_hws = (const struct clk_hw *[]){
1567                                       &gcc_gp2_clk_src.clkr.hw },
1568                         .num_parents = 1,
1569                         .flags = CLK_SET_RATE_PARENT,
1570                         .ops = &clk_branch2_ops,
1571                 },
1572         },
1573 };
1574
1575 static struct clk_branch gcc_gp3_clk = {
1576         .halt_reg = 0x66000,
1577         .halt_check = BRANCH_HALT,
1578         .clkr = {
1579                 .enable_reg = 0x66000,
1580                 .enable_mask = BIT(0),
1581                 .hw.init = &(struct clk_init_data){
1582                         .name = "gcc_gp3_clk",
1583                         .parent_hws = (const struct clk_hw *[]){
1584                                       &gcc_gp3_clk_src.clkr.hw },
1585                         .num_parents = 1,
1586                         .flags = CLK_SET_RATE_PARENT,
1587                         .ops = &clk_branch2_ops,
1588                 },
1589         },
1590 };
1591
1592 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1593         .halt_reg = 0x71004,
1594         .halt_check = BRANCH_HALT,
1595         .hwcg_reg = 0x71004,
1596         .hwcg_bit = 1,
1597         .clkr = {
1598                 .enable_reg = 0x71004,
1599                 .enable_mask = BIT(0),
1600                 .hw.init = &(struct clk_init_data){
1601                         .name = "gcc_gpu_cfg_ahb_clk",
1602                          /* required for gpu */
1603                         .flags = CLK_IS_CRITICAL,
1604                         .ops = &clk_branch2_ops,
1605                 },
1606         },
1607 };
1608
1609 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1610         .halt_check = BRANCH_HALT_SKIP,
1611         .clkr = {
1612                 .enable_reg = 0x52004,
1613                 .enable_mask = BIT(15),
1614                 .hw.init = &(struct clk_init_data){
1615                         .name = "gcc_gpu_gpll0_clk_src",
1616                         .parent_hws = (const struct clk_hw *[]){
1617                                 &gpll0.clkr.hw },
1618                         .num_parents = 1,
1619                         .flags = CLK_SET_RATE_PARENT,
1620                         .ops = &clk_branch2_ops,
1621                 },
1622         },
1623 };
1624
1625 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1626         .halt_check = BRANCH_HALT_SKIP,
1627         .clkr = {
1628                 .enable_reg = 0x52004,
1629                 .enable_mask = BIT(16),
1630                 .hw.init = &(struct clk_init_data){
1631                         .name = "gcc_gpu_gpll0_div_clk_src",
1632                         .parent_hws = (const struct clk_hw *[]){
1633                                 &gpll0_out_even.clkr.hw },
1634                         .num_parents = 1,
1635                         .flags = CLK_SET_RATE_PARENT,
1636                         .ops = &clk_branch2_ops,
1637                 },
1638         },
1639 };
1640
1641 static struct clk_branch gcc_gpu_iref_clk = {
1642         .halt_reg = 0x8c010,
1643         .halt_check = BRANCH_HALT,
1644         .clkr = {
1645                 .enable_reg = 0x8c010,
1646                 .enable_mask = BIT(0),
1647                 .hw.init = &(struct clk_init_data){
1648                         .name = "gcc_gpu_iref_clk",
1649                         .ops = &clk_branch2_ops,
1650                 },
1651         },
1652 };
1653
1654 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1655         .halt_reg = 0x7100c,
1656         .halt_check = BRANCH_VOTED,
1657         .clkr = {
1658                 .enable_reg = 0x7100c,
1659                 .enable_mask = BIT(0),
1660                 .hw.init = &(struct clk_init_data){
1661                         .name = "gcc_gpu_memnoc_gfx_clk",
1662                         .ops = &clk_branch2_ops,
1663                 },
1664         },
1665 };
1666
1667 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1668         .halt_reg = 0x71018,
1669         .halt_check = BRANCH_HALT,
1670         .clkr = {
1671                 .enable_reg = 0x71018,
1672                 .enable_mask = BIT(0),
1673                 .hw.init = &(struct clk_init_data){
1674                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1675                         .ops = &clk_branch2_ops,
1676                 },
1677         },
1678 };
1679
1680 static struct clk_branch gcc_npu_at_clk = {
1681         .halt_reg = 0x4d010,
1682         .halt_check = BRANCH_VOTED,
1683         .clkr = {
1684                 .enable_reg = 0x4d010,
1685                 .enable_mask = BIT(0),
1686                 .hw.init = &(struct clk_init_data){
1687                         .name = "gcc_npu_at_clk",
1688                         .ops = &clk_branch2_ops,
1689                 },
1690         },
1691 };
1692
1693 static struct clk_branch gcc_npu_axi_clk = {
1694         .halt_reg = 0x4d008,
1695         .halt_check = BRANCH_VOTED,
1696         .clkr = {
1697                 .enable_reg = 0x4d008,
1698                 .enable_mask = BIT(0),
1699                 .hw.init = &(struct clk_init_data){
1700                         .name = "gcc_npu_axi_clk",
1701                         .ops = &clk_branch2_ops,
1702                 },
1703         },
1704 };
1705
1706 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1707         .halt_reg = 0x4d004,
1708         .halt_check = BRANCH_HALT,
1709         .hwcg_reg = 0x4d004,
1710         .hwcg_bit = 1,
1711         .clkr = {
1712                 .enable_reg = 0x4d004,
1713                 .enable_mask = BIT(0),
1714                 .hw.init = &(struct clk_init_data){
1715                         .name = "gcc_npu_cfg_ahb_clk",
1716                          /* required for npu */
1717                         .flags = CLK_IS_CRITICAL,
1718                         .ops = &clk_branch2_ops,
1719                 },
1720         },
1721 };
1722
1723 static struct clk_branch gcc_npu_gpll0_clk_src = {
1724         .halt_check = BRANCH_HALT_SKIP,
1725         .clkr = {
1726                 .enable_reg = 0x52004,
1727                 .enable_mask = BIT(18),
1728                 .hw.init = &(struct clk_init_data){
1729                         .name = "gcc_npu_gpll0_clk_src",
1730                         .parent_hws = (const struct clk_hw *[]){
1731                                 &gpll0.clkr.hw },
1732                         .num_parents = 1,
1733                         .flags = CLK_SET_RATE_PARENT,
1734                         .ops = &clk_branch2_ops,
1735                 },
1736         },
1737 };
1738
1739 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1740         .halt_check = BRANCH_HALT_SKIP,
1741         .clkr = {
1742                 .enable_reg = 0x52004,
1743                 .enable_mask = BIT(19),
1744                 .hw.init = &(struct clk_init_data){
1745                         .name = "gcc_npu_gpll0_div_clk_src",
1746                         .parent_hws = (const struct clk_hw *[]){
1747                                 &gpll0_out_even.clkr.hw },
1748                         .num_parents = 1,
1749                         .flags = CLK_SET_RATE_PARENT,
1750                         .ops = &clk_branch2_ops,
1751                 },
1752         },
1753 };
1754
1755 static struct clk_branch gcc_npu_trig_clk = {
1756         .halt_reg = 0x4d00c,
1757         .halt_check = BRANCH_VOTED,
1758         .clkr = {
1759                 .enable_reg = 0x4d00c,
1760                 .enable_mask = BIT(0),
1761                 .hw.init = &(struct clk_init_data){
1762                         .name = "gcc_npu_trig_clk",
1763                         .ops = &clk_branch2_ops,
1764                 },
1765         },
1766 };
1767
1768 static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1769         .halt_reg = 0x6f02c,
1770         .halt_check = BRANCH_HALT,
1771         .clkr = {
1772                 .enable_reg = 0x6f02c,
1773                 .enable_mask = BIT(0),
1774                 .hw.init = &(struct clk_init_data){
1775                         .name = "gcc_pcie0_phy_refgen_clk",
1776                         .parent_hws = (const struct clk_hw *[]){
1777                                       &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1778                         .num_parents = 1,
1779                         .flags = CLK_SET_RATE_PARENT,
1780                         .ops = &clk_branch2_ops,
1781                 },
1782         },
1783 };
1784
1785 static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1786         .halt_reg = 0x6f030,
1787         .halt_check = BRANCH_HALT,
1788         .clkr = {
1789                 .enable_reg = 0x6f030,
1790                 .enable_mask = BIT(0),
1791                 .hw.init = &(struct clk_init_data){
1792                         .name = "gcc_pcie1_phy_refgen_clk",
1793                         .parent_hws = (const struct clk_hw *[]){
1794                                       &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1795                         .num_parents = 1,
1796                         .flags = CLK_SET_RATE_PARENT,
1797                         .ops = &clk_branch2_ops,
1798                 },
1799         },
1800 };
1801
1802 static struct clk_branch gcc_pcie_0_aux_clk = {
1803         .halt_reg = 0x6b020,
1804         .halt_check = BRANCH_HALT_VOTED,
1805         .clkr = {
1806                 .enable_reg = 0x5200c,
1807                 .enable_mask = BIT(3),
1808                 .hw.init = &(struct clk_init_data){
1809                         .name = "gcc_pcie_0_aux_clk",
1810                         .parent_hws = (const struct clk_hw *[]){
1811                                       &gcc_pcie_0_aux_clk_src.clkr.hw },
1812                         .num_parents = 1,
1813                         .flags = CLK_SET_RATE_PARENT,
1814                         .ops = &clk_branch2_ops,
1815                 },
1816         },
1817 };
1818
1819 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1820         .halt_reg = 0x6b01c,
1821         .halt_check = BRANCH_HALT_VOTED,
1822         .hwcg_reg = 0x6b01c,
1823         .hwcg_bit = 1,
1824         .clkr = {
1825                 .enable_reg = 0x5200c,
1826                 .enable_mask = BIT(2),
1827                 .hw.init = &(struct clk_init_data){
1828                         .name = "gcc_pcie_0_cfg_ahb_clk",
1829                         .ops = &clk_branch2_ops,
1830                 },
1831         },
1832 };
1833
1834 static struct clk_branch gcc_pcie_0_clkref_clk = {
1835         .halt_reg = 0x8c00c,
1836         .halt_check = BRANCH_HALT,
1837         .clkr = {
1838                 .enable_reg = 0x8c00c,
1839                 .enable_mask = BIT(0),
1840                 .hw.init = &(struct clk_init_data){
1841                         .name = "gcc_pcie_0_clkref_clk",
1842                         .ops = &clk_branch2_ops,
1843                 },
1844         },
1845 };
1846
1847 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1848         .halt_reg = 0x6b018,
1849         .halt_check = BRANCH_HALT_VOTED,
1850         .clkr = {
1851                 .enable_reg = 0x5200c,
1852                 .enable_mask = BIT(1),
1853                 .hw.init = &(struct clk_init_data){
1854                         .name = "gcc_pcie_0_mstr_axi_clk",
1855                         .ops = &clk_branch2_ops,
1856                 },
1857         },
1858 };
1859
1860 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1861 static struct clk_branch gcc_pcie_0_pipe_clk = {
1862         .halt_reg = 0x6b024,
1863         .halt_check = BRANCH_HALT_DELAY,
1864         .clkr = {
1865                 .enable_reg = 0x5200c,
1866                 .enable_mask = BIT(4),
1867                 .hw.init = &(struct clk_init_data){
1868                         .name = "gcc_pcie_0_pipe_clk",
1869                         .ops = &clk_branch2_ops,
1870                 },
1871         },
1872 };
1873
1874 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1875         .halt_reg = 0x6b014,
1876         .halt_check = BRANCH_HALT_VOTED,
1877         .hwcg_reg = 0x6b014,
1878         .hwcg_bit = 1,
1879         .clkr = {
1880                 .enable_reg = 0x5200c,
1881                 .enable_mask = BIT(0),
1882                 .hw.init = &(struct clk_init_data){
1883                         .name = "gcc_pcie_0_slv_axi_clk",
1884                         .ops = &clk_branch2_ops,
1885                 },
1886         },
1887 };
1888
1889 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1890         .halt_reg = 0x6b010,
1891         .halt_check = BRANCH_HALT_VOTED,
1892         .clkr = {
1893                 .enable_reg = 0x5200c,
1894                 .enable_mask = BIT(5),
1895                 .hw.init = &(struct clk_init_data){
1896                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1897                         .ops = &clk_branch2_ops,
1898                 },
1899         },
1900 };
1901
1902 static struct clk_branch gcc_pcie_1_aux_clk = {
1903         .halt_reg = 0x8d020,
1904         .halt_check = BRANCH_HALT_VOTED,
1905         .clkr = {
1906                 .enable_reg = 0x52004,
1907                 .enable_mask = BIT(29),
1908                 .hw.init = &(struct clk_init_data){
1909                         .name = "gcc_pcie_1_aux_clk",
1910                         .parent_hws = (const struct clk_hw *[]){
1911                                       &gcc_pcie_1_aux_clk_src.clkr.hw },
1912                         .num_parents = 1,
1913                         .flags = CLK_SET_RATE_PARENT,
1914                         .ops = &clk_branch2_ops,
1915                 },
1916         },
1917 };
1918
1919 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1920         .halt_reg = 0x8d01c,
1921         .halt_check = BRANCH_HALT_VOTED,
1922         .hwcg_reg = 0x8d01c,
1923         .hwcg_bit = 1,
1924         .clkr = {
1925                 .enable_reg = 0x52004,
1926                 .enable_mask = BIT(28),
1927                 .hw.init = &(struct clk_init_data){
1928                         .name = "gcc_pcie_1_cfg_ahb_clk",
1929                         .ops = &clk_branch2_ops,
1930                 },
1931         },
1932 };
1933
1934 static struct clk_branch gcc_pcie_1_clkref_clk = {
1935         .halt_reg = 0x8c02c,
1936         .halt_check = BRANCH_HALT,
1937         .clkr = {
1938                 .enable_reg = 0x8c02c,
1939                 .enable_mask = BIT(0),
1940                 .hw.init = &(struct clk_init_data){
1941                         .name = "gcc_pcie_1_clkref_clk",
1942                         .ops = &clk_branch2_ops,
1943                 },
1944         },
1945 };
1946
1947 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1948         .halt_reg = 0x8d018,
1949         .halt_check = BRANCH_HALT_VOTED,
1950         .clkr = {
1951                 .enable_reg = 0x52004,
1952                 .enable_mask = BIT(27),
1953                 .hw.init = &(struct clk_init_data){
1954                         .name = "gcc_pcie_1_mstr_axi_clk",
1955                         .ops = &clk_branch2_ops,
1956                 },
1957         },
1958 };
1959
1960 /* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1961 static struct clk_branch gcc_pcie_1_pipe_clk = {
1962         .halt_reg = 0x8d024,
1963         .halt_check = BRANCH_HALT_DELAY,
1964         .clkr = {
1965                 .enable_reg = 0x52004,
1966                 .enable_mask = BIT(30),
1967                 .hw.init = &(struct clk_init_data){
1968                         .name = "gcc_pcie_1_pipe_clk",
1969                         .ops = &clk_branch2_ops,
1970                 },
1971         },
1972 };
1973
1974 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1975         .halt_reg = 0x8d014,
1976         .halt_check = BRANCH_HALT_VOTED,
1977         .hwcg_reg = 0x8d014,
1978         .hwcg_bit = 1,
1979         .clkr = {
1980                 .enable_reg = 0x52004,
1981                 .enable_mask = BIT(26),
1982                 .hw.init = &(struct clk_init_data){
1983                         .name = "gcc_pcie_1_slv_axi_clk",
1984                         .ops = &clk_branch2_ops,
1985                 },
1986         },
1987 };
1988
1989 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1990         .halt_reg = 0x8d010,
1991         .halt_check = BRANCH_HALT_VOTED,
1992         .clkr = {
1993                 .enable_reg = 0x52004,
1994                 .enable_mask = BIT(25),
1995                 .hw.init = &(struct clk_init_data){
1996                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
1997                         .ops = &clk_branch2_ops,
1998                 },
1999         },
2000 };
2001
2002 static struct clk_branch gcc_pcie_phy_aux_clk = {
2003         .halt_reg = 0x6f004,
2004         .halt_check = BRANCH_HALT,
2005         .clkr = {
2006                 .enable_reg = 0x6f004,
2007                 .enable_mask = BIT(0),
2008                 .hw.init = &(struct clk_init_data){
2009                         .name = "gcc_pcie_phy_aux_clk",
2010                         .parent_hws = (const struct clk_hw *[]){
2011                                       &gcc_pcie_0_aux_clk_src.clkr.hw },
2012                         .num_parents = 1,
2013                         .flags = CLK_SET_RATE_PARENT,
2014                         .ops = &clk_branch2_ops,
2015                 },
2016         },
2017 };
2018
2019 static struct clk_branch gcc_pdm2_clk = {
2020         .halt_reg = 0x3300c,
2021         .halt_check = BRANCH_HALT,
2022         .clkr = {
2023                 .enable_reg = 0x3300c,
2024                 .enable_mask = BIT(0),
2025                 .hw.init = &(struct clk_init_data){
2026                         .name = "gcc_pdm2_clk",
2027                         .parent_hws = (const struct clk_hw *[]){
2028                                       &gcc_pdm2_clk_src.clkr.hw },
2029                         .num_parents = 1,
2030                         .flags = CLK_SET_RATE_PARENT,
2031                         .ops = &clk_branch2_ops,
2032                 },
2033         },
2034 };
2035
2036 static struct clk_branch gcc_pdm_ahb_clk = {
2037         .halt_reg = 0x33004,
2038         .halt_check = BRANCH_HALT,
2039         .hwcg_reg = 0x33004,
2040         .hwcg_bit = 1,
2041         .clkr = {
2042                 .enable_reg = 0x33004,
2043                 .enable_mask = BIT(0),
2044                 .hw.init = &(struct clk_init_data){
2045                         .name = "gcc_pdm_ahb_clk",
2046                         .ops = &clk_branch2_ops,
2047                 },
2048         },
2049 };
2050
2051 static struct clk_branch gcc_pdm_xo4_clk = {
2052         .halt_reg = 0x33008,
2053         .halt_check = BRANCH_HALT,
2054         .clkr = {
2055                 .enable_reg = 0x33008,
2056                 .enable_mask = BIT(0),
2057                 .hw.init = &(struct clk_init_data){
2058                         .name = "gcc_pdm_xo4_clk",
2059                         .ops = &clk_branch2_ops,
2060                 },
2061         },
2062 };
2063
2064 static struct clk_branch gcc_prng_ahb_clk = {
2065         .halt_reg = 0x34004,
2066         .halt_check = BRANCH_HALT_VOTED,
2067         .clkr = {
2068                 .enable_reg = 0x52004,
2069                 .enable_mask = BIT(13),
2070                 .hw.init = &(struct clk_init_data){
2071                         .name = "gcc_prng_ahb_clk",
2072                         .ops = &clk_branch2_ops,
2073                 },
2074         },
2075 };
2076
2077 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2078         .halt_reg = 0xb018,
2079         .halt_check = BRANCH_HALT,
2080         .hwcg_reg = 0xb018,
2081         .hwcg_bit = 1,
2082         .clkr = {
2083                 .enable_reg = 0xb018,
2084                 .enable_mask = BIT(0),
2085                 .hw.init = &(struct clk_init_data){
2086                         .name = "gcc_qmip_camera_nrt_ahb_clk",
2087                         .ops = &clk_branch2_ops,
2088                 },
2089         },
2090 };
2091
2092 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2093         .halt_reg = 0xb01c,
2094         .halt_check = BRANCH_HALT,
2095         .hwcg_reg = 0xb01c,
2096         .hwcg_bit = 1,
2097         .clkr = {
2098                 .enable_reg = 0xb01c,
2099                 .enable_mask = BIT(0),
2100                 .hw.init = &(struct clk_init_data){
2101                         .name = "gcc_qmip_camera_rt_ahb_clk",
2102                         .ops = &clk_branch2_ops,
2103                 },
2104         },
2105 };
2106
2107 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2108         .halt_reg = 0xb020,
2109         .halt_check = BRANCH_HALT,
2110         .hwcg_reg = 0xb020,
2111         .hwcg_bit = 1,
2112         .clkr = {
2113                 .enable_reg = 0xb020,
2114                 .enable_mask = BIT(0),
2115                 .hw.init = &(struct clk_init_data){
2116                         .name = "gcc_qmip_disp_ahb_clk",
2117                         .ops = &clk_branch2_ops,
2118                 },
2119         },
2120 };
2121
2122 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2123         .halt_reg = 0xb010,
2124         .halt_check = BRANCH_HALT,
2125         .hwcg_reg = 0xb010,
2126         .hwcg_bit = 1,
2127         .clkr = {
2128                 .enable_reg = 0xb010,
2129                 .enable_mask = BIT(0),
2130                 .hw.init = &(struct clk_init_data){
2131                         .name = "gcc_qmip_video_cvp_ahb_clk",
2132                         .ops = &clk_branch2_ops,
2133                 },
2134         },
2135 };
2136
2137 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2138         .halt_reg = 0xb014,
2139         .halt_check = BRANCH_HALT,
2140         .hwcg_reg = 0xb014,
2141         .hwcg_bit = 1,
2142         .clkr = {
2143                 .enable_reg = 0xb014,
2144                 .enable_mask = BIT(0),
2145                 .hw.init = &(struct clk_init_data){
2146                         .name = "gcc_qmip_video_vcodec_ahb_clk",
2147                         .ops = &clk_branch2_ops,
2148                 },
2149         },
2150 };
2151
2152 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2153         .halt_reg = 0x4b000,
2154         .halt_check = BRANCH_HALT,
2155         .clkr = {
2156                 .enable_reg = 0x4b000,
2157                 .enable_mask = BIT(0),
2158                 .hw.init = &(struct clk_init_data){
2159                         .name = "gcc_qspi_cnoc_periph_ahb_clk",
2160                         .ops = &clk_branch2_ops,
2161                 },
2162         },
2163 };
2164
2165 static struct clk_branch gcc_qspi_core_clk = {
2166         .halt_reg = 0x4b004,
2167         .halt_check = BRANCH_HALT,
2168         .clkr = {
2169                 .enable_reg = 0x4b004,
2170                 .enable_mask = BIT(0),
2171                 .hw.init = &(struct clk_init_data){
2172                         .name = "gcc_qspi_core_clk",
2173                         .parent_hws = (const struct clk_hw *[]){
2174                                       &gcc_qspi_core_clk_src.clkr.hw },
2175                         .num_parents = 1,
2176                         .flags = CLK_SET_RATE_PARENT,
2177                         .ops = &clk_branch2_ops,
2178                 },
2179         },
2180 };
2181
2182 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2183         .halt_reg = 0x17144,
2184         .halt_check = BRANCH_HALT_VOTED,
2185         .clkr = {
2186                 .enable_reg = 0x5200c,
2187                 .enable_mask = BIT(10),
2188                 .hw.init = &(struct clk_init_data){
2189                         .name = "gcc_qupv3_wrap0_s0_clk",
2190                         .parent_hws = (const struct clk_hw *[]){
2191                                       &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2192                         .num_parents = 1,
2193                         .flags = CLK_SET_RATE_PARENT,
2194                         .ops = &clk_branch2_ops,
2195                 },
2196         },
2197 };
2198
2199 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2200         .halt_reg = 0x17274,
2201         .halt_check = BRANCH_HALT_VOTED,
2202         .clkr = {
2203                 .enable_reg = 0x5200c,
2204                 .enable_mask = BIT(11),
2205                 .hw.init = &(struct clk_init_data){
2206                         .name = "gcc_qupv3_wrap0_s1_clk",
2207                         .parent_hws = (const struct clk_hw *[]){
2208                                       &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2209                         .num_parents = 1,
2210                         .flags = CLK_SET_RATE_PARENT,
2211                         .ops = &clk_branch2_ops,
2212                 },
2213         },
2214 };
2215
2216 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2217         .halt_reg = 0x173a4,
2218         .halt_check = BRANCH_HALT_VOTED,
2219         .clkr = {
2220                 .enable_reg = 0x5200c,
2221                 .enable_mask = BIT(12),
2222                 .hw.init = &(struct clk_init_data){
2223                         .name = "gcc_qupv3_wrap0_s2_clk",
2224                         .parent_hws = (const struct clk_hw *[]){
2225                                       &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2226                         .num_parents = 1,
2227                         .flags = CLK_SET_RATE_PARENT,
2228                         .ops = &clk_branch2_ops,
2229                 },
2230         },
2231 };
2232
2233 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2234         .halt_reg = 0x174d4,
2235         .halt_check = BRANCH_HALT_VOTED,
2236         .clkr = {
2237                 .enable_reg = 0x5200c,
2238                 .enable_mask = BIT(13),
2239                 .hw.init = &(struct clk_init_data){
2240                         .name = "gcc_qupv3_wrap0_s3_clk",
2241                         .parent_hws = (const struct clk_hw *[]){
2242                                       &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2243                         .num_parents = 1,
2244                         .flags = CLK_SET_RATE_PARENT,
2245                         .ops = &clk_branch2_ops,
2246                 },
2247         },
2248 };
2249
2250 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2251         .halt_reg = 0x17604,
2252         .halt_check = BRANCH_HALT_VOTED,
2253         .clkr = {
2254                 .enable_reg = 0x5200c,
2255                 .enable_mask = BIT(14),
2256                 .hw.init = &(struct clk_init_data){
2257                         .name = "gcc_qupv3_wrap0_s4_clk",
2258                         .parent_hws = (const struct clk_hw *[]){
2259                                       &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2260                         .num_parents = 1,
2261                         .flags = CLK_SET_RATE_PARENT,
2262                         .ops = &clk_branch2_ops,
2263                 },
2264         },
2265 };
2266
2267 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2268         .halt_reg = 0x17734,
2269         .halt_check = BRANCH_HALT_VOTED,
2270         .clkr = {
2271                 .enable_reg = 0x5200c,
2272                 .enable_mask = BIT(15),
2273                 .hw.init = &(struct clk_init_data){
2274                         .name = "gcc_qupv3_wrap0_s5_clk",
2275                         .parent_hws = (const struct clk_hw *[]){
2276                                       &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2277                         .num_parents = 1,
2278                         .flags = CLK_SET_RATE_PARENT,
2279                         .ops = &clk_branch2_ops,
2280                 },
2281         },
2282 };
2283
2284 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2285         .halt_reg = 0x17864,
2286         .halt_check = BRANCH_HALT_VOTED,
2287         .clkr = {
2288                 .enable_reg = 0x5200c,
2289                 .enable_mask = BIT(16),
2290                 .hw.init = &(struct clk_init_data){
2291                         .name = "gcc_qupv3_wrap0_s6_clk",
2292                         .parent_hws = (const struct clk_hw *[]){
2293                                       &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
2294                         .num_parents = 1,
2295                         .flags = CLK_SET_RATE_PARENT,
2296                         .ops = &clk_branch2_ops,
2297                 },
2298         },
2299 };
2300
2301 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2302         .halt_reg = 0x17994,
2303         .halt_check = BRANCH_HALT_VOTED,
2304         .clkr = {
2305                 .enable_reg = 0x5200c,
2306                 .enable_mask = BIT(17),
2307                 .hw.init = &(struct clk_init_data){
2308                         .name = "gcc_qupv3_wrap0_s7_clk",
2309                         .parent_hws = (const struct clk_hw *[]){
2310                                       &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
2311                         .num_parents = 1,
2312                         .flags = CLK_SET_RATE_PARENT,
2313                         .ops = &clk_branch2_ops,
2314                 },
2315         },
2316 };
2317
2318 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2319         .halt_reg = 0x18144,
2320         .halt_check = BRANCH_HALT_VOTED,
2321         .clkr = {
2322                 .enable_reg = 0x5200c,
2323                 .enable_mask = BIT(22),
2324                 .hw.init = &(struct clk_init_data){
2325                         .name = "gcc_qupv3_wrap1_s0_clk",
2326                         .parent_hws = (const struct clk_hw *[]){
2327                                       &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
2328                         .num_parents = 1,
2329                         .flags = CLK_SET_RATE_PARENT,
2330                         .ops = &clk_branch2_ops,
2331                 },
2332         },
2333 };
2334
2335 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2336         .halt_reg = 0x18274,
2337         .halt_check = BRANCH_HALT_VOTED,
2338         .clkr = {
2339                 .enable_reg = 0x5200c,
2340                 .enable_mask = BIT(23),
2341                 .hw.init = &(struct clk_init_data){
2342                         .name = "gcc_qupv3_wrap1_s1_clk",
2343                         .parent_hws = (const struct clk_hw *[]){
2344                                       &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
2345                         .num_parents = 1,
2346                         .flags = CLK_SET_RATE_PARENT,
2347                         .ops = &clk_branch2_ops,
2348                 },
2349         },
2350 };
2351
2352 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2353         .halt_reg = 0x183a4,
2354         .halt_check = BRANCH_HALT_VOTED,
2355         .clkr = {
2356                 .enable_reg = 0x5200c,
2357                 .enable_mask = BIT(24),
2358                 .hw.init = &(struct clk_init_data){
2359                         .name = "gcc_qupv3_wrap1_s2_clk",
2360                         .parent_hws = (const struct clk_hw *[]){
2361                                       &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
2362                         .num_parents = 1,
2363                         .flags = CLK_SET_RATE_PARENT,
2364                         .ops = &clk_branch2_ops,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2370         .halt_reg = 0x184d4,
2371         .halt_check = BRANCH_HALT_VOTED,
2372         .clkr = {
2373                 .enable_reg = 0x5200c,
2374                 .enable_mask = BIT(25),
2375                 .hw.init = &(struct clk_init_data){
2376                         .name = "gcc_qupv3_wrap1_s3_clk",
2377                         .parent_hws = (const struct clk_hw *[]){
2378                                       &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
2379                         .num_parents = 1,
2380                         .flags = CLK_SET_RATE_PARENT,
2381                         .ops = &clk_branch2_ops,
2382                 },
2383         },
2384 };
2385
2386 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2387         .halt_reg = 0x18604,
2388         .halt_check = BRANCH_HALT_VOTED,
2389         .clkr = {
2390                 .enable_reg = 0x5200c,
2391                 .enable_mask = BIT(26),
2392                 .hw.init = &(struct clk_init_data){
2393                         .name = "gcc_qupv3_wrap1_s4_clk",
2394                         .parent_hws = (const struct clk_hw *[]){
2395                                       &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
2396                         .num_parents = 1,
2397                         .flags = CLK_SET_RATE_PARENT,
2398                         .ops = &clk_branch2_ops,
2399                 },
2400         },
2401 };
2402
2403 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2404         .halt_reg = 0x18734,
2405         .halt_check = BRANCH_HALT_VOTED,
2406         .clkr = {
2407                 .enable_reg = 0x5200c,
2408                 .enable_mask = BIT(27),
2409                 .hw.init = &(struct clk_init_data){
2410                         .name = "gcc_qupv3_wrap1_s5_clk",
2411                         .parent_hws = (const struct clk_hw *[]){
2412                                       &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
2413                         .num_parents = 1,
2414                         .flags = CLK_SET_RATE_PARENT,
2415                         .ops = &clk_branch2_ops,
2416                 },
2417         },
2418 };
2419
2420 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2421         .halt_reg = 0x1e144,
2422         .halt_check = BRANCH_HALT_VOTED,
2423         .clkr = {
2424                 .enable_reg = 0x52014,
2425                 .enable_mask = BIT(4),
2426                 .hw.init = &(struct clk_init_data){
2427                         .name = "gcc_qupv3_wrap2_s0_clk",
2428                         .parent_hws = (const struct clk_hw *[]){
2429                                       &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
2430                         .num_parents = 1,
2431                         .flags = CLK_SET_RATE_PARENT,
2432                         .ops = &clk_branch2_ops,
2433                 },
2434         },
2435 };
2436
2437 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2438         .halt_reg = 0x1e274,
2439         .halt_check = BRANCH_HALT_VOTED,
2440         .clkr = {
2441                 .enable_reg = 0x52014,
2442                 .enable_mask = BIT(5),
2443                 .hw.init = &(struct clk_init_data){
2444                         .name = "gcc_qupv3_wrap2_s1_clk",
2445                         .parent_hws = (const struct clk_hw *[]){
2446                                       &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
2447                         .num_parents = 1,
2448                         .flags = CLK_SET_RATE_PARENT,
2449                         .ops = &clk_branch2_ops,
2450                 },
2451         },
2452 };
2453
2454 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2455         .halt_reg = 0x1e3a4,
2456         .halt_check = BRANCH_HALT_VOTED,
2457         .clkr = {
2458                 .enable_reg = 0x52014,
2459                 .enable_mask = BIT(6),
2460                 .hw.init = &(struct clk_init_data){
2461                         .name = "gcc_qupv3_wrap2_s2_clk",
2462                         .parent_hws = (const struct clk_hw *[]){
2463                                       &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
2464                         .num_parents = 1,
2465                         .flags = CLK_SET_RATE_PARENT,
2466                         .ops = &clk_branch2_ops,
2467                 },
2468         },
2469 };
2470
2471 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2472         .halt_reg = 0x1e4d4,
2473         .halt_check = BRANCH_HALT_VOTED,
2474         .clkr = {
2475                 .enable_reg = 0x52014,
2476                 .enable_mask = BIT(7),
2477                 .hw.init = &(struct clk_init_data){
2478                         .name = "gcc_qupv3_wrap2_s3_clk",
2479                         .parent_hws = (const struct clk_hw *[]){
2480                                       &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
2481                         .num_parents = 1,
2482                         .flags = CLK_SET_RATE_PARENT,
2483                         .ops = &clk_branch2_ops,
2484                 },
2485         },
2486 };
2487
2488 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2489         .halt_reg = 0x1e604,
2490         .halt_check = BRANCH_HALT_VOTED,
2491         .clkr = {
2492                 .enable_reg = 0x52014,
2493                 .enable_mask = BIT(8),
2494                 .hw.init = &(struct clk_init_data){
2495                         .name = "gcc_qupv3_wrap2_s4_clk",
2496                         .parent_hws = (const struct clk_hw *[]){
2497                                       &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
2498                         .num_parents = 1,
2499                         .flags = CLK_SET_RATE_PARENT,
2500                         .ops = &clk_branch2_ops,
2501                 },
2502         },
2503 };
2504
2505 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2506         .halt_reg = 0x1e734,
2507         .halt_check = BRANCH_HALT_VOTED,
2508         .clkr = {
2509                 .enable_reg = 0x52014,
2510                 .enable_mask = BIT(9),
2511                 .hw.init = &(struct clk_init_data){
2512                         .name = "gcc_qupv3_wrap2_s5_clk",
2513                         .parent_hws = (const struct clk_hw *[]){
2514                                       &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
2515                         .num_parents = 1,
2516                         .flags = CLK_SET_RATE_PARENT,
2517                         .ops = &clk_branch2_ops,
2518                 },
2519         },
2520 };
2521
2522 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2523         .halt_reg = 0x17004,
2524         .halt_check = BRANCH_HALT_VOTED,
2525         .clkr = {
2526                 .enable_reg = 0x5200c,
2527                 .enable_mask = BIT(6),
2528                 .hw.init = &(struct clk_init_data){
2529                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2530                         .ops = &clk_branch2_ops,
2531                 },
2532         },
2533 };
2534
2535 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2536         .halt_reg = 0x17008,
2537         .halt_check = BRANCH_HALT_VOTED,
2538         .hwcg_reg = 0x17008,
2539         .hwcg_bit = 1,
2540         .clkr = {
2541                 .enable_reg = 0x5200c,
2542                 .enable_mask = BIT(7),
2543                 .hw.init = &(struct clk_init_data){
2544                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2545                         .ops = &clk_branch2_ops,
2546                 },
2547         },
2548 };
2549
2550 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2551         .halt_reg = 0x18004,
2552         .halt_check = BRANCH_HALT_VOTED,
2553         .clkr = {
2554                 .enable_reg = 0x5200c,
2555                 .enable_mask = BIT(20),
2556                 .hw.init = &(struct clk_init_data){
2557                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2558                         .ops = &clk_branch2_ops,
2559                 },
2560         },
2561 };
2562
2563 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2564         .halt_reg = 0x18008,
2565         .halt_check = BRANCH_HALT_VOTED,
2566         .hwcg_reg = 0x18008,
2567         .hwcg_bit = 1,
2568         .clkr = {
2569                 .enable_reg = 0x5200c,
2570                 .enable_mask = BIT(21),
2571                 .hw.init = &(struct clk_init_data){
2572                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2573                         .ops = &clk_branch2_ops,
2574                 },
2575         },
2576 };
2577
2578 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2579         .halt_reg = 0x1e004,
2580         .halt_check = BRANCH_HALT_VOTED,
2581         .clkr = {
2582                 .enable_reg = 0x52014,
2583                 .enable_mask = BIT(2),
2584                 .hw.init = &(struct clk_init_data){
2585                         .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2586                         .ops = &clk_branch2_ops,
2587                 },
2588         },
2589 };
2590
2591 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2592         .halt_reg = 0x1e008,
2593         .halt_check = BRANCH_HALT_VOTED,
2594         .hwcg_reg = 0x1e008,
2595         .hwcg_bit = 1,
2596         .clkr = {
2597                 .enable_reg = 0x52014,
2598                 .enable_mask = BIT(1),
2599                 .hw.init = &(struct clk_init_data){
2600                         .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2601                         .ops = &clk_branch2_ops,
2602                 },
2603         },
2604 };
2605
2606 static struct clk_branch gcc_sdcc2_ahb_clk = {
2607         .halt_reg = 0x14008,
2608         .halt_check = BRANCH_HALT,
2609         .clkr = {
2610                 .enable_reg = 0x14008,
2611                 .enable_mask = BIT(0),
2612                 .hw.init = &(struct clk_init_data){
2613                         .name = "gcc_sdcc2_ahb_clk",
2614                         .ops = &clk_branch2_ops,
2615                 },
2616         },
2617 };
2618
2619 static struct clk_branch gcc_sdcc2_apps_clk = {
2620         .halt_reg = 0x14004,
2621         .halt_check = BRANCH_HALT,
2622         .clkr = {
2623                 .enable_reg = 0x14004,
2624                 .enable_mask = BIT(0),
2625                 .hw.init = &(struct clk_init_data){
2626                         .name = "gcc_sdcc2_apps_clk",
2627                         .parent_hws = (const struct clk_hw *[]){
2628                                       &gcc_sdcc2_apps_clk_src.clkr.hw },
2629                         .num_parents = 1,
2630                         .flags = CLK_SET_RATE_PARENT,
2631                         .ops = &clk_branch2_ops,
2632                 },
2633         },
2634 };
2635
2636 static struct clk_branch gcc_sdcc4_ahb_clk = {
2637         .halt_reg = 0x16008,
2638         .halt_check = BRANCH_HALT,
2639         .clkr = {
2640                 .enable_reg = 0x16008,
2641                 .enable_mask = BIT(0),
2642                 .hw.init = &(struct clk_init_data){
2643                         .name = "gcc_sdcc4_ahb_clk",
2644                         .ops = &clk_branch2_ops,
2645                 },
2646         },
2647 };
2648
2649 static struct clk_branch gcc_sdcc4_apps_clk = {
2650         .halt_reg = 0x16004,
2651         .halt_check = BRANCH_HALT,
2652         .clkr = {
2653                 .enable_reg = 0x16004,
2654                 .enable_mask = BIT(0),
2655                 .hw.init = &(struct clk_init_data){
2656                         .name = "gcc_sdcc4_apps_clk",
2657                         .parent_hws = (const struct clk_hw *[]){
2658                                       &gcc_sdcc4_apps_clk_src.clkr.hw },
2659                         .num_parents = 1,
2660                         .flags = CLK_SET_RATE_PARENT,
2661                         .ops = &clk_branch2_ops,
2662                 },
2663         },
2664 };
2665
2666 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2667         .halt_reg = 0x4819c,
2668         .halt_check = BRANCH_HALT_VOTED,
2669         .clkr = {
2670                 .enable_reg = 0x52004,
2671                 .enable_mask = BIT(0),
2672                 .hw.init = &(struct clk_init_data){
2673                         .name = "gcc_sys_noc_cpuss_ahb_clk",
2674                         .parent_hws = (const struct clk_hw *[]){
2675                                       &gcc_cpuss_ahb_clk_src.clkr.hw },
2676                         .num_parents = 1,
2677                         /* required for cpuss */
2678                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2679                         .ops = &clk_branch2_ops,
2680                 },
2681         },
2682 };
2683
2684 static struct clk_branch gcc_tsif_ahb_clk = {
2685         .halt_reg = 0x36004,
2686         .halt_check = BRANCH_HALT,
2687         .clkr = {
2688                 .enable_reg = 0x36004,
2689                 .enable_mask = BIT(0),
2690                 .hw.init = &(struct clk_init_data){
2691                         .name = "gcc_tsif_ahb_clk",
2692                         .ops = &clk_branch2_ops,
2693                 },
2694         },
2695 };
2696
2697 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2698         .halt_reg = 0x3600c,
2699         .halt_check = BRANCH_HALT,
2700         .clkr = {
2701                 .enable_reg = 0x3600c,
2702                 .enable_mask = BIT(0),
2703                 .hw.init = &(struct clk_init_data){
2704                         .name = "gcc_tsif_inactivity_timers_clk",
2705                         .ops = &clk_branch2_ops,
2706                 },
2707         },
2708 };
2709
2710 static struct clk_branch gcc_tsif_ref_clk = {
2711         .halt_reg = 0x36008,
2712         .halt_check = BRANCH_HALT,
2713         .clkr = {
2714                 .enable_reg = 0x36008,
2715                 .enable_mask = BIT(0),
2716                 .hw.init = &(struct clk_init_data){
2717                         .name = "gcc_tsif_ref_clk",
2718                         .parent_hws = (const struct clk_hw *[]){
2719                                       &gcc_tsif_ref_clk_src.clkr.hw },
2720                         .num_parents = 1,
2721                         .flags = CLK_SET_RATE_PARENT,
2722                         .ops = &clk_branch2_ops,
2723                 },
2724         },
2725 };
2726
2727 static struct clk_branch gcc_ufs_card_ahb_clk = {
2728         .halt_reg = 0x75014,
2729         .halt_check = BRANCH_HALT,
2730         .hwcg_reg = 0x75014,
2731         .hwcg_bit = 1,
2732         .clkr = {
2733                 .enable_reg = 0x75014,
2734                 .enable_mask = BIT(0),
2735                 .hw.init = &(struct clk_init_data){
2736                         .name = "gcc_ufs_card_ahb_clk",
2737                         .ops = &clk_branch2_ops,
2738                 },
2739         },
2740 };
2741
2742 static struct clk_branch gcc_ufs_card_axi_clk = {
2743         .halt_reg = 0x75010,
2744         .halt_check = BRANCH_HALT,
2745         .hwcg_reg = 0x75010,
2746         .hwcg_bit = 1,
2747         .clkr = {
2748                 .enable_reg = 0x75010,
2749                 .enable_mask = BIT(0),
2750                 .hw.init = &(struct clk_init_data){
2751                         .name = "gcc_ufs_card_axi_clk",
2752                         .parent_hws = (const struct clk_hw *[]){
2753                                       &gcc_ufs_card_axi_clk_src.clkr.hw },
2754                         .num_parents = 1,
2755                         .flags = CLK_SET_RATE_PARENT,
2756                         .ops = &clk_branch2_ops,
2757                 },
2758         },
2759 };
2760
2761 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2762         .halt_reg = 0x75010,
2763         .halt_check = BRANCH_HALT,
2764         .hwcg_reg = 0x75010,
2765         .hwcg_bit = 1,
2766         .clkr = {
2767                 .enable_reg = 0x75010,
2768                 .enable_mask = BIT(1),
2769                 .hw.init = &(struct clk_init_data){
2770                         .name = "gcc_ufs_card_axi_hw_ctl_clk",
2771                         .parent_hws = (const struct clk_hw *[]){
2772                                       &gcc_ufs_card_axi_clk.clkr.hw },
2773                         .num_parents = 1,
2774                         .flags = CLK_SET_RATE_PARENT,
2775                         .ops = &clk_branch_simple_ops,
2776                 },
2777         },
2778 };
2779
2780 static struct clk_branch gcc_ufs_card_clkref_clk = {
2781         .halt_reg = 0x8c004,
2782         .halt_check = BRANCH_HALT,
2783         .clkr = {
2784                 .enable_reg = 0x8c004,
2785                 .enable_mask = BIT(0),
2786                 .hw.init = &(struct clk_init_data){
2787                         .name = "gcc_ufs_card_clkref_clk",
2788                         .ops = &clk_branch2_ops,
2789                 },
2790         },
2791 };
2792
2793 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2794         .halt_reg = 0x7505c,
2795         .halt_check = BRANCH_HALT,
2796         .hwcg_reg = 0x7505c,
2797         .hwcg_bit = 1,
2798         .clkr = {
2799                 .enable_reg = 0x7505c,
2800                 .enable_mask = BIT(0),
2801                 .hw.init = &(struct clk_init_data){
2802                         .name = "gcc_ufs_card_ice_core_clk",
2803                         .parent_hws = (const struct clk_hw *[]){
2804                                       &gcc_ufs_card_ice_core_clk_src.clkr.hw },
2805                         .num_parents = 1,
2806                         .flags = CLK_SET_RATE_PARENT,
2807                         .ops = &clk_branch2_ops,
2808                 },
2809         },
2810 };
2811
2812 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2813         .halt_reg = 0x7505c,
2814         .halt_check = BRANCH_HALT,
2815         .hwcg_reg = 0x7505c,
2816         .hwcg_bit = 1,
2817         .clkr = {
2818                 .enable_reg = 0x7505c,
2819                 .enable_mask = BIT(1),
2820                 .hw.init = &(struct clk_init_data){
2821                         .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2822                         .parent_hws = (const struct clk_hw *[]){
2823                                       &gcc_ufs_card_ice_core_clk.clkr.hw },
2824                         .num_parents = 1,
2825                         .flags = CLK_SET_RATE_PARENT,
2826                         .ops = &clk_branch_simple_ops,
2827                 },
2828         },
2829 };
2830
2831 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2832         .halt_reg = 0x75090,
2833         .halt_check = BRANCH_HALT,
2834         .hwcg_reg = 0x75090,
2835         .hwcg_bit = 1,
2836         .clkr = {
2837                 .enable_reg = 0x75090,
2838                 .enable_mask = BIT(0),
2839                 .hw.init = &(struct clk_init_data){
2840                         .name = "gcc_ufs_card_phy_aux_clk",
2841                         .parent_hws = (const struct clk_hw *[]){
2842                                       &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
2843                         .num_parents = 1,
2844                         .flags = CLK_SET_RATE_PARENT,
2845                         .ops = &clk_branch2_ops,
2846                 },
2847         },
2848 };
2849
2850 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2851         .halt_reg = 0x75090,
2852         .halt_check = BRANCH_HALT,
2853         .hwcg_reg = 0x75090,
2854         .hwcg_bit = 1,
2855         .clkr = {
2856                 .enable_reg = 0x75090,
2857                 .enable_mask = BIT(1),
2858                 .hw.init = &(struct clk_init_data){
2859                         .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2860                         .parent_hws = (const struct clk_hw *[]){
2861                                       &gcc_ufs_card_phy_aux_clk.clkr.hw },
2862                         .num_parents = 1,
2863                         .flags = CLK_SET_RATE_PARENT,
2864                         .ops = &clk_branch_simple_ops,
2865                 },
2866         },
2867 };
2868
2869 /* external clocks so add BRANCH_HALT_SKIP */
2870 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2871         .halt_check = BRANCH_HALT_SKIP,
2872         .clkr = {
2873                 .enable_reg = 0x7501c,
2874                 .enable_mask = BIT(0),
2875                 .hw.init = &(struct clk_init_data){
2876                         .name = "gcc_ufs_card_rx_symbol_0_clk",
2877                         .ops = &clk_branch2_ops,
2878                 },
2879         },
2880 };
2881
2882 /* external clocks so add BRANCH_HALT_SKIP */
2883 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2884         .halt_check = BRANCH_HALT_SKIP,
2885         .clkr = {
2886                 .enable_reg = 0x750ac,
2887                 .enable_mask = BIT(0),
2888                 .hw.init = &(struct clk_init_data){
2889                         .name = "gcc_ufs_card_rx_symbol_1_clk",
2890                         .ops = &clk_branch2_ops,
2891                 },
2892         },
2893 };
2894
2895 /* external clocks so add BRANCH_HALT_SKIP */
2896 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2897         .halt_check = BRANCH_HALT_SKIP,
2898         .clkr = {
2899                 .enable_reg = 0x75018,
2900                 .enable_mask = BIT(0),
2901                 .hw.init = &(struct clk_init_data){
2902                         .name = "gcc_ufs_card_tx_symbol_0_clk",
2903                         .ops = &clk_branch2_ops,
2904                 },
2905         },
2906 };
2907
2908 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2909         .halt_reg = 0x75058,
2910         .halt_check = BRANCH_HALT,
2911         .hwcg_reg = 0x75058,
2912         .hwcg_bit = 1,
2913         .clkr = {
2914                 .enable_reg = 0x75058,
2915                 .enable_mask = BIT(0),
2916                 .hw.init = &(struct clk_init_data){
2917                         .name = "gcc_ufs_card_unipro_core_clk",
2918                         .parent_hws = (const struct clk_hw *[]){
2919                                 &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
2920                         .num_parents = 1,
2921                         .flags = CLK_SET_RATE_PARENT,
2922                         .ops = &clk_branch2_ops,
2923                 },
2924         },
2925 };
2926
2927 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2928         .halt_reg = 0x75058,
2929         .halt_check = BRANCH_HALT,
2930         .hwcg_reg = 0x75058,
2931         .hwcg_bit = 1,
2932         .clkr = {
2933                 .enable_reg = 0x75058,
2934                 .enable_mask = BIT(1),
2935                 .hw.init = &(struct clk_init_data){
2936                         .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2937                         .parent_hws = (const struct clk_hw *[]){
2938                                       &gcc_ufs_card_unipro_core_clk.clkr.hw },
2939                         .num_parents = 1,
2940                         .flags = CLK_SET_RATE_PARENT,
2941                         .ops = &clk_branch_simple_ops,
2942                 },
2943         },
2944 };
2945
2946 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2947         .halt_reg = 0x8c000,
2948         .halt_check = BRANCH_HALT,
2949         .clkr = {
2950                 .enable_reg = 0x8c000,
2951                 .enable_mask = BIT(0),
2952                 .hw.init = &(struct clk_init_data){
2953                         .name = "gcc_ufs_mem_clkref_clk",
2954                         .ops = &clk_branch2_ops,
2955                 },
2956         },
2957 };
2958
2959 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2960         .halt_reg = 0x77014,
2961         .halt_check = BRANCH_HALT,
2962         .hwcg_reg = 0x77014,
2963         .hwcg_bit = 1,
2964         .clkr = {
2965                 .enable_reg = 0x77014,
2966                 .enable_mask = BIT(0),
2967                 .hw.init = &(struct clk_init_data){
2968                         .name = "gcc_ufs_phy_ahb_clk",
2969                         .ops = &clk_branch2_ops,
2970                 },
2971         },
2972 };
2973
2974 static struct clk_branch gcc_ufs_phy_axi_clk = {
2975         .halt_reg = 0x77010,
2976         .halt_check = BRANCH_HALT,
2977         .hwcg_reg = 0x77010,
2978         .hwcg_bit = 1,
2979         .clkr = {
2980                 .enable_reg = 0x77010,
2981                 .enable_mask = BIT(0),
2982                 .hw.init = &(struct clk_init_data){
2983                         .name = "gcc_ufs_phy_axi_clk",
2984                         .parent_hws = (const struct clk_hw *[]){
2985                                 &gcc_ufs_phy_axi_clk_src.clkr.hw },
2986                         .num_parents = 1,
2987                         .flags = CLK_SET_RATE_PARENT,
2988                         .ops = &clk_branch2_ops,
2989                 },
2990         },
2991 };
2992
2993 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2994         .halt_reg = 0x77010,
2995         .halt_check = BRANCH_HALT,
2996         .hwcg_reg = 0x77010,
2997         .hwcg_bit = 1,
2998         .clkr = {
2999                 .enable_reg = 0x77010,
3000                 .enable_mask = BIT(1),
3001                 .hw.init = &(struct clk_init_data){
3002                         .name = "gcc_ufs_phy_axi_hw_ctl_clk",
3003                         .parent_hws = (const struct clk_hw *[]){
3004                                       &gcc_ufs_phy_axi_clk.clkr.hw },
3005                         .num_parents = 1,
3006                         .flags = CLK_SET_RATE_PARENT,
3007                         .ops = &clk_branch_simple_ops,
3008                 },
3009         },
3010 };
3011
3012 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3013         .halt_reg = 0x7705c,
3014         .halt_check = BRANCH_HALT,
3015         .hwcg_reg = 0x7705c,
3016         .hwcg_bit = 1,
3017         .clkr = {
3018                 .enable_reg = 0x7705c,
3019                 .enable_mask = BIT(0),
3020                 .hw.init = &(struct clk_init_data){
3021                         .name = "gcc_ufs_phy_ice_core_clk",
3022                         .parent_hws = (const struct clk_hw *[]){
3023                                       &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
3024                         .num_parents = 1,
3025                         .flags = CLK_SET_RATE_PARENT,
3026                         .ops = &clk_branch2_ops,
3027                 },
3028         },
3029 };
3030
3031 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3032         .halt_reg = 0x7705c,
3033         .halt_check = BRANCH_HALT,
3034         .hwcg_reg = 0x7705c,
3035         .hwcg_bit = 1,
3036         .clkr = {
3037                 .enable_reg = 0x7705c,
3038                 .enable_mask = BIT(1),
3039                 .hw.init = &(struct clk_init_data){
3040                         .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3041                         .parent_hws = (const struct clk_hw *[]){
3042                                       &gcc_ufs_phy_ice_core_clk.clkr.hw },
3043                         .num_parents = 1,
3044                         .flags = CLK_SET_RATE_PARENT,
3045                         .ops = &clk_branch_simple_ops,
3046                 },
3047         },
3048 };
3049
3050 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3051         .halt_reg = 0x77090,
3052         .halt_check = BRANCH_HALT,
3053         .hwcg_reg = 0x77090,
3054         .hwcg_bit = 1,
3055         .clkr = {
3056                 .enable_reg = 0x77090,
3057                 .enable_mask = BIT(0),
3058                 .hw.init = &(struct clk_init_data){
3059                         .name = "gcc_ufs_phy_phy_aux_clk",
3060                         .parent_hws = (const struct clk_hw *[]){
3061                                       &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
3062                         .num_parents = 1,
3063                         .flags = CLK_SET_RATE_PARENT,
3064                         .ops = &clk_branch2_ops,
3065                 },
3066         },
3067 };
3068
3069 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3070         .halt_reg = 0x77090,
3071         .halt_check = BRANCH_HALT,
3072         .hwcg_reg = 0x77090,
3073         .hwcg_bit = 1,
3074         .clkr = {
3075                 .enable_reg = 0x77090,
3076                 .enable_mask = BIT(1),
3077                 .hw.init = &(struct clk_init_data){
3078                         .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3079                         .parent_hws = (const struct clk_hw *[]){
3080                                       &gcc_ufs_phy_phy_aux_clk.clkr.hw },
3081                         .num_parents = 1,
3082                         .flags = CLK_SET_RATE_PARENT,
3083                         .ops = &clk_branch_simple_ops,
3084                 },
3085         },
3086 };
3087
3088 /* external clocks so add BRANCH_HALT_SKIP */
3089 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3090         .halt_check = BRANCH_HALT_SKIP,
3091         .clkr = {
3092                 .enable_reg = 0x7701c,
3093                 .enable_mask = BIT(0),
3094                 .hw.init = &(struct clk_init_data){
3095                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
3096                         .ops = &clk_branch2_ops,
3097                 },
3098         },
3099 };
3100
3101 /* external clocks so add BRANCH_HALT_SKIP */
3102 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3103         .halt_check = BRANCH_HALT_SKIP,
3104         .clkr = {
3105                 .enable_reg = 0x770ac,
3106                 .enable_mask = BIT(0),
3107                 .hw.init = &(struct clk_init_data){
3108                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
3109                         .ops = &clk_branch2_ops,
3110                 },
3111         },
3112 };
3113
3114 /* external clocks so add BRANCH_HALT_SKIP */
3115 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3116         .halt_check = BRANCH_HALT_SKIP,
3117         .clkr = {
3118                 .enable_reg = 0x77018,
3119                 .enable_mask = BIT(0),
3120                 .hw.init = &(struct clk_init_data){
3121                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
3122                         .ops = &clk_branch2_ops,
3123                 },
3124         },
3125 };
3126
3127 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3128         .halt_reg = 0x77058,
3129         .halt_check = BRANCH_HALT,
3130         .hwcg_reg = 0x77058,
3131         .hwcg_bit = 1,
3132         .clkr = {
3133                 .enable_reg = 0x77058,
3134                 .enable_mask = BIT(0),
3135                 .hw.init = &(struct clk_init_data){
3136                         .name = "gcc_ufs_phy_unipro_core_clk",
3137                         .parent_hws = (const struct clk_hw *[]){
3138                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
3139                         .num_parents = 1,
3140                         .flags = CLK_SET_RATE_PARENT,
3141                         .ops = &clk_branch2_ops,
3142                 },
3143         },
3144 };
3145
3146 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3147         .halt_reg = 0x77058,
3148         .halt_check = BRANCH_HALT,
3149         .hwcg_reg = 0x77058,
3150         .hwcg_bit = 1,
3151         .clkr = {
3152                 .enable_reg = 0x77058,
3153                 .enable_mask = BIT(1),
3154                 .hw.init = &(struct clk_init_data){
3155                         .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3156                         .parent_hws = (const struct clk_hw *[]){
3157                                       &gcc_ufs_phy_unipro_core_clk.clkr.hw },
3158                         .num_parents = 1,
3159                         .flags = CLK_SET_RATE_PARENT,
3160                         .ops = &clk_branch_simple_ops,
3161                 },
3162         },
3163 };
3164
3165 static struct clk_branch gcc_usb30_prim_master_clk = {
3166         .halt_reg = 0xf010,
3167         .halt_check = BRANCH_HALT,
3168         .clkr = {
3169                 .enable_reg = 0xf010,
3170                 .enable_mask = BIT(0),
3171                 .hw.init = &(struct clk_init_data){
3172                         .name = "gcc_usb30_prim_master_clk",
3173                         .parent_hws = (const struct clk_hw *[]){
3174                                       &gcc_usb30_prim_master_clk_src.clkr.hw },
3175                         .num_parents = 1,
3176                         .flags = CLK_SET_RATE_PARENT,
3177                         .ops = &clk_branch2_ops,
3178                 },
3179         },
3180 };
3181
3182 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3183         .halt_reg = 0xf018,
3184         .halt_check = BRANCH_HALT,
3185         .clkr = {
3186                 .enable_reg = 0xf018,
3187                 .enable_mask = BIT(0),
3188                 .hw.init = &(struct clk_init_data){
3189                         .name = "gcc_usb30_prim_mock_utmi_clk",
3190                         .parent_hws = (const struct clk_hw *[]){
3191                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
3192                         .num_parents = 1,
3193                         .flags = CLK_SET_RATE_PARENT,
3194                         .ops = &clk_branch2_ops,
3195                 },
3196         },
3197 };
3198
3199 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3200         .halt_reg = 0xf014,
3201         .halt_check = BRANCH_HALT,
3202         .clkr = {
3203                 .enable_reg = 0xf014,
3204                 .enable_mask = BIT(0),
3205                 .hw.init = &(struct clk_init_data){
3206                         .name = "gcc_usb30_prim_sleep_clk",
3207                         .ops = &clk_branch2_ops,
3208                 },
3209         },
3210 };
3211
3212 static struct clk_branch gcc_usb30_sec_master_clk = {
3213         .halt_reg = 0x10010,
3214         .halt_check = BRANCH_HALT,
3215         .clkr = {
3216                 .enable_reg = 0x10010,
3217                 .enable_mask = BIT(0),
3218                 .hw.init = &(struct clk_init_data){
3219                         .name = "gcc_usb30_sec_master_clk",
3220                         .parent_hws = (const struct clk_hw *[]){
3221                                       &gcc_usb30_sec_master_clk_src.clkr.hw },
3222                         .num_parents = 1,
3223                         .flags = CLK_SET_RATE_PARENT,
3224                         .ops = &clk_branch2_ops,
3225                 },
3226         },
3227 };
3228
3229 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3230         .halt_reg = 0x10018,
3231         .halt_check = BRANCH_HALT,
3232         .clkr = {
3233                 .enable_reg = 0x10018,
3234                 .enable_mask = BIT(0),
3235                 .hw.init = &(struct clk_init_data){
3236                         .name = "gcc_usb30_sec_mock_utmi_clk",
3237                         .parent_hws = (const struct clk_hw *[]){
3238                                 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
3239                         .num_parents = 1,
3240                         .flags = CLK_SET_RATE_PARENT,
3241                         .ops = &clk_branch2_ops,
3242                 },
3243         },
3244 };
3245
3246 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3247         .halt_reg = 0x10014,
3248         .halt_check = BRANCH_HALT,
3249         .clkr = {
3250                 .enable_reg = 0x10014,
3251                 .enable_mask = BIT(0),
3252                 .hw.init = &(struct clk_init_data){
3253                         .name = "gcc_usb30_sec_sleep_clk",
3254                         .ops = &clk_branch2_ops,
3255                 },
3256         },
3257 };
3258
3259 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3260         .halt_reg = 0x8c008,
3261         .halt_check = BRANCH_HALT,
3262         .clkr = {
3263                 .enable_reg = 0x8c008,
3264                 .enable_mask = BIT(0),
3265                 .hw.init = &(struct clk_init_data){
3266                         .name = "gcc_usb3_prim_clkref_clk",
3267                         .ops = &clk_branch2_ops,
3268                 },
3269         },
3270 };
3271
3272 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3273         .halt_reg = 0xf050,
3274         .halt_check = BRANCH_HALT,
3275         .clkr = {
3276                 .enable_reg = 0xf050,
3277                 .enable_mask = BIT(0),
3278                 .hw.init = &(struct clk_init_data){
3279                         .name = "gcc_usb3_prim_phy_aux_clk",
3280                         .parent_hws = (const struct clk_hw *[]){
3281                                       &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3282                         .num_parents = 1,
3283                         .flags = CLK_SET_RATE_PARENT,
3284                         .ops = &clk_branch2_ops,
3285                 },
3286         },
3287 };
3288
3289 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3290         .halt_reg = 0xf054,
3291         .halt_check = BRANCH_HALT,
3292         .clkr = {
3293                 .enable_reg = 0xf054,
3294                 .enable_mask = BIT(0),
3295                 .hw.init = &(struct clk_init_data){
3296                         .name = "gcc_usb3_prim_phy_com_aux_clk",
3297                         .parent_hws = (const struct clk_hw *[]){
3298                                       &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3299                         .num_parents = 1,
3300                         .flags = CLK_SET_RATE_PARENT,
3301                         .ops = &clk_branch2_ops,
3302                 },
3303         },
3304 };
3305
3306 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3307         .halt_check = BRANCH_HALT_SKIP,
3308         .clkr = {
3309                 .enable_reg = 0xf058,
3310                 .enable_mask = BIT(0),
3311                 .hw.init = &(struct clk_init_data){
3312                         .name = "gcc_usb3_prim_phy_pipe_clk",
3313                         .ops = &clk_branch2_ops,
3314                 },
3315         },
3316 };
3317
3318 static struct clk_branch gcc_usb3_sec_clkref_clk = {
3319         .halt_reg = 0x8c028,
3320         .halt_check = BRANCH_HALT,
3321         .clkr = {
3322                 .enable_reg = 0x8c028,
3323                 .enable_mask = BIT(0),
3324                 .hw.init = &(struct clk_init_data){
3325                         .name = "gcc_usb3_sec_clkref_clk",
3326                         .ops = &clk_branch2_ops,
3327                 },
3328         },
3329 };
3330
3331 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3332         .halt_reg = 0x10050,
3333         .halt_check = BRANCH_HALT,
3334         .clkr = {
3335                 .enable_reg = 0x10050,
3336                 .enable_mask = BIT(0),
3337                 .hw.init = &(struct clk_init_data){
3338                         .name = "gcc_usb3_sec_phy_aux_clk",
3339                         .parent_hws = (const struct clk_hw *[]){
3340                                       &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3341                         .num_parents = 1,
3342                         .flags = CLK_SET_RATE_PARENT,
3343                         .ops = &clk_branch2_ops,
3344                 },
3345         },
3346 };
3347
3348 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3349         .halt_reg = 0x10054,
3350         .halt_check = BRANCH_HALT,
3351         .clkr = {
3352                 .enable_reg = 0x10054,
3353                 .enable_mask = BIT(0),
3354                 .hw.init = &(struct clk_init_data){
3355                         .name = "gcc_usb3_sec_phy_com_aux_clk",
3356                         .parent_hws = (const struct clk_hw *[]){
3357                                       &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3358                         .num_parents = 1,
3359                         .flags = CLK_SET_RATE_PARENT,
3360                         .ops = &clk_branch2_ops,
3361                 },
3362         },
3363 };
3364
3365 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3366         .halt_check = BRANCH_HALT_SKIP,
3367         .clkr = {
3368                 .enable_reg = 0x10058,
3369                 .enable_mask = BIT(0),
3370                 .hw.init = &(struct clk_init_data){
3371                         .name = "gcc_usb3_sec_phy_pipe_clk",
3372                         .ops = &clk_branch2_ops,
3373                 },
3374         },
3375 };
3376
3377 /*
3378  * Clock ON depends on external parent 'config noc', so cant poll
3379  * delay and also mark as crtitical for video boot
3380  */
3381 static struct clk_branch gcc_video_ahb_clk = {
3382         .halt_reg = 0xb004,
3383         .halt_check = BRANCH_HALT_DELAY,
3384         .hwcg_reg = 0xb004,
3385         .hwcg_bit = 1,
3386         .clkr = {
3387                 .enable_reg = 0xb004,
3388                 .enable_mask = BIT(0),
3389                 .hw.init = &(struct clk_init_data){
3390                         .name = "gcc_video_ahb_clk",
3391                         .flags = CLK_IS_CRITICAL,
3392                         .ops = &clk_branch2_ops,
3393                 },
3394         },
3395 };
3396
3397 static struct clk_branch gcc_video_axi0_clk = {
3398         .halt_reg = 0xb024,
3399         .halt_check = BRANCH_HALT,
3400         .clkr = {
3401                 .enable_reg = 0xb024,
3402                 .enable_mask = BIT(0),
3403                 .hw.init = &(struct clk_init_data){
3404                         .name = "gcc_video_axi0_clk",
3405                         .ops = &clk_branch2_ops,
3406                 },
3407         },
3408 };
3409
3410 static struct clk_branch gcc_video_axi1_clk = {
3411         .halt_reg = 0xb028,
3412         .halt_check = BRANCH_HALT,
3413         .clkr = {
3414                 .enable_reg = 0xb028,
3415                 .enable_mask = BIT(0),
3416                 .hw.init = &(struct clk_init_data){
3417                         .name = "gcc_video_axi1_clk",
3418                         .ops = &clk_branch2_ops,
3419                 },
3420         },
3421 };
3422
3423 static struct clk_branch gcc_video_axic_clk = {
3424         .halt_reg = 0xb02c,
3425         .halt_check = BRANCH_HALT,
3426         .clkr = {
3427                 .enable_reg = 0xb02c,
3428                 .enable_mask = BIT(0),
3429                 .hw.init = &(struct clk_init_data){
3430                         .name = "gcc_video_axic_clk",
3431                         .ops = &clk_branch2_ops,
3432                 },
3433         },
3434 };
3435
3436 /* XO critical input to video, so no need to poll */
3437 static struct clk_branch gcc_video_xo_clk = {
3438         .halt_reg = 0xb040,
3439         .halt_check = BRANCH_HALT_DELAY,
3440         .clkr = {
3441                 .enable_reg = 0xb040,
3442                 .enable_mask = BIT(0),
3443                 .hw.init = &(struct clk_init_data){
3444                         .name = "gcc_video_xo_clk",
3445                         .flags = CLK_IS_CRITICAL,
3446                         .ops = &clk_branch2_ops,
3447                 },
3448         },
3449 };
3450
3451 static struct gdsc usb30_prim_gdsc = {
3452                 .gdscr = 0xf004,
3453                 .pd = {
3454                         .name = "usb30_prim_gdsc",
3455                 },
3456                 .pwrsts = PWRSTS_OFF_ON,
3457                 .flags = POLL_CFG_GDSCR,
3458 };
3459
3460 static struct gdsc usb30_sec_gdsc = {
3461                 .gdscr = 0x10004,
3462                 .pd = {
3463                         .name = "usb30_sec_gdsc",
3464                 },
3465                 .pwrsts = PWRSTS_OFF_ON,
3466                 .flags = POLL_CFG_GDSCR,
3467 };
3468
3469 static struct clk_regmap *gcc_sm8150_clocks[] = {
3470         [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3471         [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3472         [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
3473                 &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3474         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3475         [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
3476                 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3477         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3478         [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3479         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3480         [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3481         [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3482         [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3483         [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3484         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3485         [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3486         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3487         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3488         [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3489         [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3490         [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3491         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3492         [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3493         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3494         [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3495         [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3496         [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
3497         [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
3498         [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
3499         [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
3500         [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
3501         [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
3502         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3503         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3504         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3505         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3506         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3507         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3508         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3509         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3510         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3511         [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3512         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3513         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3514         [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
3515         [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
3516         [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
3517         [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
3518         [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
3519         [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
3520         [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
3521         [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
3522         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3523         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3524         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3525         [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3526         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3527         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3528         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3529         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3530         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3531         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3532         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3533         [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3534         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3535         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3536         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3537         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3538         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3539         [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3540         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3541         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3542         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3543         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3544         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3545         [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3546         [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3547         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3548         [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3549         [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3550         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3551         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3552         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3553         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3554         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3555         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3556         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3557         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3558         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3559         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3560         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3561         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3562         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3563         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3564         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3565         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3566         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3567         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3568         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3569         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3570         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3571         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3572         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3573         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3574         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3575         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3576         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3577         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3578         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3579         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3580         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3581         [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3582         [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3583         [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3584         [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3585         [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3586         [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3587         [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3588         [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3589         [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3590         [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3591         [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3592         [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3593         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3594         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3595         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3596         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3597         [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3598         [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3599         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3600         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3601         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3602         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3603         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3604         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3605         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3606         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3607         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3608         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3609         [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3610         [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3611         [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3612         [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3613         [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3614         [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3615         [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3616         [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3617         [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
3618                 &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3619         [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3620         [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3621         [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
3622                 &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3623         [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3624         [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3625         [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3626         [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3627         [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3628                 &gcc_ufs_card_unipro_core_clk_src.clkr,
3629         [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
3630                 &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3631         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3632         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3633         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3634         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3635         [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3636         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3637         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3638         [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
3639                 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3640         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3641         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3642         [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3643         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3644         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3645         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3646         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3647         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3648                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3649         [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
3650                 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3651         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3652         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3653         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3654         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3655                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3656         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3657         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3658         [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3659         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3660         [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3661                 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3662         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3663         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3664         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3665         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3666         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3667         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3668         [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3669         [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3670         [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3671         [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3672         [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3673         [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3674         [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3675         [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3676         [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
3677         [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3678         [GPLL0] = &gpll0.clkr,
3679         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3680         [GPLL7] = &gpll7.clkr,
3681         [GPLL9] = &gpll9.clkr,
3682 };
3683
3684 static const struct qcom_reset_map gcc_sm8150_resets[] = {
3685         [GCC_EMAC_BCR] = { 0x6000 },
3686         [GCC_GPU_BCR] = { 0x71000 },
3687         [GCC_MMSS_BCR] = { 0xb000 },
3688         [GCC_NPU_BCR] = { 0x4d000 },
3689         [GCC_PCIE_0_BCR] = { 0x6b000 },
3690         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3691         [GCC_PCIE_1_BCR] = { 0x8d000 },
3692         [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3693         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3694         [GCC_PDM_BCR] = { 0x33000 },
3695         [GCC_PRNG_BCR] = { 0x34000 },
3696         [GCC_QSPI_BCR] = { 0x24008 },
3697         [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3698         [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3699         [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3700         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3701         [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3702         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3703         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3704         [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3705         [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3706         [GCC_SDCC2_BCR] = { 0x14000 },
3707         [GCC_SDCC4_BCR] = { 0x16000 },
3708         [GCC_TSIF_BCR] = { 0x36000 },
3709         [GCC_UFS_CARD_BCR] = { 0x75000 },
3710         [GCC_UFS_PHY_BCR] = { 0x77000 },
3711         [GCC_USB30_PRIM_BCR] = { 0xf000 },
3712         [GCC_USB30_SEC_BCR] = { 0x10000 },
3713         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3714 };
3715
3716 static struct gdsc *gcc_sm8150_gdscs[] = {
3717         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3718         [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3719 };
3720
3721 static const struct regmap_config gcc_sm8150_regmap_config = {
3722         .reg_bits       = 32,
3723         .reg_stride     = 4,
3724         .val_bits       = 32,
3725         .max_register   = 0x9c040,
3726         .fast_io        = true,
3727 };
3728
3729 static const struct qcom_cc_desc gcc_sm8150_desc = {
3730         .config = &gcc_sm8150_regmap_config,
3731         .clks = gcc_sm8150_clocks,
3732         .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
3733         .resets = gcc_sm8150_resets,
3734         .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
3735         .gdscs = gcc_sm8150_gdscs,
3736         .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
3737 };
3738
3739 static const struct of_device_id gcc_sm8150_match_table[] = {
3740         { .compatible = "qcom,gcc-sm8150" },
3741         { }
3742 };
3743 MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
3744
3745 static int gcc_sm8150_probe(struct platform_device *pdev)
3746 {
3747         struct regmap *regmap;
3748
3749         regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
3750         if (IS_ERR(regmap))
3751                 return PTR_ERR(regmap);
3752
3753         /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
3754         regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
3755         regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3756
3757         return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
3758 }
3759
3760 static struct platform_driver gcc_sm8150_driver = {
3761         .probe          = gcc_sm8150_probe,
3762         .driver         = {
3763                 .name   = "gcc-sm8150",
3764                 .of_match_table = gcc_sm8150_match_table,
3765         },
3766 };
3767
3768 static int __init gcc_sm8150_init(void)
3769 {
3770         return platform_driver_register(&gcc_sm8150_driver);
3771 }
3772 subsys_initcall(gcc_sm8150_init);
3773
3774 static void __exit gcc_sm8150_exit(void)
3775 {
3776         platform_driver_unregister(&gcc_sm8150_driver);
3777 }
3778 module_exit(gcc_sm8150_exit);
3779
3780 MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
3781 MODULE_LICENSE("GPL v2");