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Merge tag 'trace-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[linux/fpc-iii.git] / drivers / clk / qcom / mmcc-msm8998.c
blobdd68983fe22efa9357e32a718e2bd4c816892bcd
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16
17 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
18
19 #include "common.h"
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28 enum {
29 P_XO,
30 P_GPLL0,
31 P_GPLL0_DIV,
32 P_MMPLL0_OUT_EVEN,
33 P_MMPLL1_OUT_EVEN,
34 P_MMPLL3_OUT_EVEN,
35 P_MMPLL4_OUT_EVEN,
36 P_MMPLL5_OUT_EVEN,
37 P_MMPLL6_OUT_EVEN,
38 P_MMPLL7_OUT_EVEN,
39 P_MMPLL10_OUT_EVEN,
40 P_DSI0PLL,
41 P_DSI1PLL,
42 P_DSI0PLL_BYTE,
43 P_DSI1PLL_BYTE,
44 P_HDMIPLL,
45 P_DPVCO,
46 P_DPLINK,
47 P_CORE_BI_PLL_TEST_SE,
48 };
49
50 static struct clk_fixed_factor gpll0_div = {
51 .mult = 1,
52 .div = 2,
53 .hw.init = &(struct clk_init_data){
54 .name = "mmss_gpll0_div",
55 .parent_data = &(const struct clk_parent_data){
56 .fw_name = "gpll0",
57 .name = "gpll0"
58 },
59 .num_parents = 1,
60 .ops = &clk_fixed_factor_ops,
61 },
62 };
63
64 static const struct clk_div_table post_div_table_fabia_even[] = {
65 { 0x0, 1 },
66 { 0x1, 2 },
67 { 0x3, 4 },
68 { 0x7, 8 },
69 { }
70 };
71
72 static struct clk_alpha_pll mmpll0 = {
73 .offset = 0xc000,
74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
75 .clkr = {
76 .enable_reg = 0x1e0,
77 .enable_mask = BIT(0),
78 .hw.init = &(struct clk_init_data){
79 .name = "mmpll0",
80 .parent_data = &(const struct clk_parent_data){
81 .fw_name = "xo",
82 .name = "xo"
83 },
84 .num_parents = 1,
85 .ops = &clk_alpha_pll_fixed_fabia_ops,
86 },
87 },
88 };
89
90 static struct clk_alpha_pll_postdiv mmpll0_out_even = {
91 .offset = 0xc000,
92 .post_div_shift = 8,
93 .post_div_table = post_div_table_fabia_even,
94 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
95 .width = 4,
96 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
97 .clkr.hw.init = &(struct clk_init_data){
98 .name = "mmpll0_out_even",
99 .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
100 .num_parents = 1,
101 .ops = &clk_alpha_pll_postdiv_fabia_ops,
102 },
103 };
104
105 static struct clk_alpha_pll mmpll1 = {
106 .offset = 0xc050,
107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
108 .clkr = {
109 .enable_reg = 0x1e0,
110 .enable_mask = BIT(1),
111 .hw.init = &(struct clk_init_data){
112 .name = "mmpll1",
113 .parent_data = &(const struct clk_parent_data){
114 .fw_name = "xo",
115 .name = "xo"
116 },
117 .num_parents = 1,
118 .ops = &clk_alpha_pll_fixed_fabia_ops,
119 },
120 },
121 };
122
123 static struct clk_alpha_pll_postdiv mmpll1_out_even = {
124 .offset = 0xc050,
125 .post_div_shift = 8,
126 .post_div_table = post_div_table_fabia_even,
127 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
128 .width = 4,
129 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
130 .clkr.hw.init = &(struct clk_init_data){
131 .name = "mmpll1_out_even",
132 .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
133 .num_parents = 1,
134 .ops = &clk_alpha_pll_postdiv_fabia_ops,
135 },
136 };
137
138 static struct clk_alpha_pll mmpll3 = {
139 .offset = 0x0,
140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
141 .clkr.hw.init = &(struct clk_init_data){
142 .name = "mmpll3",
143 .parent_data = &(const struct clk_parent_data){
144 .fw_name = "xo",
145 .name = "xo"
146 },
147 .num_parents = 1,
148 .ops = &clk_alpha_pll_fixed_fabia_ops,
149 },
150 };
151
152 static struct clk_alpha_pll_postdiv mmpll3_out_even = {
153 .offset = 0x0,
154 .post_div_shift = 8,
155 .post_div_table = post_div_table_fabia_even,
156 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
157 .width = 4,
158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
159 .clkr.hw.init = &(struct clk_init_data){
160 .name = "mmpll3_out_even",
161 .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
162 .num_parents = 1,
163 .ops = &clk_alpha_pll_postdiv_fabia_ops,
164 },
165 };
166
167 static struct clk_alpha_pll mmpll4 = {
168 .offset = 0x50,
169 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
170 .clkr.hw.init = &(struct clk_init_data){
171 .name = "mmpll4",
172 .parent_data = &(const struct clk_parent_data){
173 .fw_name = "xo",
174 .name = "xo"
175 },
176 .num_parents = 1,
177 .ops = &clk_alpha_pll_fixed_fabia_ops,
178 },
179 };
180
181 static struct clk_alpha_pll_postdiv mmpll4_out_even = {
182 .offset = 0x50,
183 .post_div_shift = 8,
184 .post_div_table = post_div_table_fabia_even,
185 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
186 .width = 4,
187 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "mmpll4_out_even",
190 .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
191 .num_parents = 1,
192 .ops = &clk_alpha_pll_postdiv_fabia_ops,
193 },
194 };
195
196 static struct clk_alpha_pll mmpll5 = {
197 .offset = 0xa0,
198 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
199 .clkr.hw.init = &(struct clk_init_data){
200 .name = "mmpll5",
201 .parent_data = &(const struct clk_parent_data){
202 .fw_name = "xo",
203 .name = "xo"
204 },
205 .num_parents = 1,
206 .ops = &clk_alpha_pll_fixed_fabia_ops,
207 },
208 };
209
210 static struct clk_alpha_pll_postdiv mmpll5_out_even = {
211 .offset = 0xa0,
212 .post_div_shift = 8,
213 .post_div_table = post_div_table_fabia_even,
214 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
215 .width = 4,
216 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
217 .clkr.hw.init = &(struct clk_init_data){
218 .name = "mmpll5_out_even",
219 .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
220 .num_parents = 1,
221 .ops = &clk_alpha_pll_postdiv_fabia_ops,
222 },
223 };
224
225 static struct clk_alpha_pll mmpll6 = {
226 .offset = 0xf0,
227 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
228 .clkr.hw.init = &(struct clk_init_data){
229 .name = "mmpll6",
230 .parent_data = &(const struct clk_parent_data){
231 .fw_name = "xo",
232 .name = "xo"
233 },
234 .num_parents = 1,
235 .ops = &clk_alpha_pll_fixed_fabia_ops,
236 },
237 };
238
239 static struct clk_alpha_pll_postdiv mmpll6_out_even = {
240 .offset = 0xf0,
241 .post_div_shift = 8,
242 .post_div_table = post_div_table_fabia_even,
243 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
244 .width = 4,
245 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
246 .clkr.hw.init = &(struct clk_init_data){
247 .name = "mmpll6_out_even",
248 .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
249 .num_parents = 1,
250 .ops = &clk_alpha_pll_postdiv_fabia_ops,
251 },
252 };
253
254 static struct clk_alpha_pll mmpll7 = {
255 .offset = 0x140,
256 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
257 .clkr.hw.init = &(struct clk_init_data){
258 .name = "mmpll7",
259 .parent_data = &(const struct clk_parent_data){
260 .fw_name = "xo",
261 .name = "xo"
262 },
263 .num_parents = 1,
264 .ops = &clk_alpha_pll_fixed_fabia_ops,
265 },
266 };
267
268 static struct clk_alpha_pll_postdiv mmpll7_out_even = {
269 .offset = 0x140,
270 .post_div_shift = 8,
271 .post_div_table = post_div_table_fabia_even,
272 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
273 .width = 4,
274 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
275 .clkr.hw.init = &(struct clk_init_data){
276 .name = "mmpll7_out_even",
277 .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
278 .num_parents = 1,
279 .ops = &clk_alpha_pll_postdiv_fabia_ops,
280 },
281 };
282
283 static struct clk_alpha_pll mmpll10 = {
284 .offset = 0x190,
285 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
286 .clkr.hw.init = &(struct clk_init_data){
287 .name = "mmpll10",
288 .parent_data = &(const struct clk_parent_data){
289 .fw_name = "xo",
290 .name = "xo"
291 },
292 .num_parents = 1,
293 .ops = &clk_alpha_pll_fixed_fabia_ops,
294 },
295 };
296
297 static struct clk_alpha_pll_postdiv mmpll10_out_even = {
298 .offset = 0x190,
299 .post_div_shift = 8,
300 .post_div_table = post_div_table_fabia_even,
301 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
302 .width = 4,
303 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
304 .clkr.hw.init = &(struct clk_init_data){
305 .name = "mmpll10_out_even",
306 .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
307 .num_parents = 1,
308 .ops = &clk_alpha_pll_postdiv_fabia_ops,
309 },
310 };
311
312 static const struct parent_map mmss_xo_hdmi_map[] = {
313 { P_XO, 0 },
314 { P_HDMIPLL, 1 },
315 { P_CORE_BI_PLL_TEST_SE, 7 }
316 };
317
318 static const struct clk_parent_data mmss_xo_hdmi[] = {
319 { .fw_name = "xo", .name = "xo" },
320 { .fw_name = "hdmipll", .name = "hdmipll" },
321 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
322 };
323
324 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
325 { P_XO, 0 },
326 { P_DSI0PLL, 1 },
327 { P_DSI1PLL, 2 },
328 { P_CORE_BI_PLL_TEST_SE, 7 }
329 };
330
331 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
332 { .fw_name = "xo", .name = "xo" },
333 { .fw_name = "dsi0dsi", .name = "dsi0dsi" },
334 { .fw_name = "dsi1dsi", .name = "dsi1dsi" },
335 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
336 };
337
338 static const struct parent_map mmss_xo_dsibyte_map[] = {
339 { P_XO, 0 },
340 { P_DSI0PLL_BYTE, 1 },
341 { P_DSI1PLL_BYTE, 2 },
342 { P_CORE_BI_PLL_TEST_SE, 7 }
343 };
344
345 static const struct clk_parent_data mmss_xo_dsibyte[] = {
346 { .fw_name = "xo", .name = "xo" },
347 { .fw_name = "dsi0byte", .name = "dsi0byte" },
348 { .fw_name = "dsi1byte", .name = "dsi1byte" },
349 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
350 };
351
352 static const struct parent_map mmss_xo_dp_map[] = {
353 { P_XO, 0 },
354 { P_DPLINK, 1 },
355 { P_DPVCO, 2 },
356 { P_CORE_BI_PLL_TEST_SE, 7 }
357 };
358
359 static const struct clk_parent_data mmss_xo_dp[] = {
360 { .fw_name = "xo", .name = "xo" },
361 { .fw_name = "dplink", .name = "dplink" },
362 { .fw_name = "dpvco", .name = "dpvco" },
363 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
364 };
365
366 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
367 { P_XO, 0 },
368 { P_GPLL0, 5 },
369 { P_GPLL0_DIV, 6 },
370 { P_CORE_BI_PLL_TEST_SE, 7 }
371 };
372
373 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
374 { .fw_name = "xo", .name = "xo" },
375 { .fw_name = "gpll0", .name = "gpll0" },
376 { .hw = &gpll0_div.hw },
377 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
378 };
379
380 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
381 { P_XO, 0 },
382 { P_MMPLL0_OUT_EVEN, 1 },
383 { P_GPLL0, 5 },
384 { P_GPLL0_DIV, 6 },
385 { P_CORE_BI_PLL_TEST_SE, 7 }
386 };
387
388 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
389 { .fw_name = "xo", .name = "xo" },
390 { .hw = &mmpll0_out_even.clkr.hw },
391 { .fw_name = "gpll0", .name = "gpll0" },
392 { .hw = &gpll0_div.hw },
393 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
394 };
395
396 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
397 { P_XO, 0 },
398 { P_MMPLL0_OUT_EVEN, 1 },
399 { P_MMPLL1_OUT_EVEN, 2 },
400 { P_GPLL0, 5 },
401 { P_GPLL0_DIV, 6 },
402 { P_CORE_BI_PLL_TEST_SE, 7 }
403 };
404
405 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
406 { .fw_name = "xo", .name = "xo" },
407 { .hw = &mmpll0_out_even.clkr.hw },
408 { .hw = &mmpll1_out_even.clkr.hw },
409 { .fw_name = "gpll0", .name = "gpll0" },
410 { .hw = &gpll0_div.hw },
411 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
412 };
413
414 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
415 { P_XO, 0 },
416 { P_MMPLL0_OUT_EVEN, 1 },
417 { P_MMPLL5_OUT_EVEN, 2 },
418 { P_GPLL0, 5 },
419 { P_GPLL0_DIV, 6 },
420 { P_CORE_BI_PLL_TEST_SE, 7 }
421 };
422
423 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
424 { .fw_name = "xo", .name = "xo" },
425 { .hw = &mmpll0_out_even.clkr.hw },
426 { .hw = &mmpll5_out_even.clkr.hw },
427 { .fw_name = "gpll0", .name = "gpll0" },
428 { .hw = &gpll0_div.hw },
429 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
430 };
431
432 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
433 { P_XO, 0 },
434 { P_MMPLL0_OUT_EVEN, 1 },
435 { P_MMPLL3_OUT_EVEN, 3 },
436 { P_MMPLL6_OUT_EVEN, 4 },
437 { P_GPLL0, 5 },
438 { P_GPLL0_DIV, 6 },
439 { P_CORE_BI_PLL_TEST_SE, 7 }
440 };
441
442 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
443 { .fw_name = "xo", .name = "xo" },
444 { .hw = &mmpll0_out_even.clkr.hw },
445 { .hw = &mmpll3_out_even.clkr.hw },
446 { .hw = &mmpll6_out_even.clkr.hw },
447 { .fw_name = "gpll0", .name = "gpll0" },
448 { .hw = &gpll0_div.hw },
449 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
450 };
451
452 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
453 { P_XO, 0 },
454 { P_MMPLL4_OUT_EVEN, 1 },
455 { P_MMPLL7_OUT_EVEN, 2 },
456 { P_MMPLL10_OUT_EVEN, 3 },
457 { P_GPLL0, 5 },
458 { P_GPLL0_DIV, 6 },
459 { P_CORE_BI_PLL_TEST_SE, 7 }
460 };
461
462 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
463 { .fw_name = "xo", .name = "xo" },
464 { .hw = &mmpll4_out_even.clkr.hw },
465 { .hw = &mmpll7_out_even.clkr.hw },
466 { .hw = &mmpll10_out_even.clkr.hw },
467 { .fw_name = "gpll0", .name = "gpll0" },
468 { .hw = &gpll0_div.hw },
469 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
470 };
471
472 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
473 { P_XO, 0 },
474 { P_MMPLL0_OUT_EVEN, 1 },
475 { P_MMPLL7_OUT_EVEN, 2 },
476 { P_MMPLL10_OUT_EVEN, 3 },
477 { P_GPLL0, 5 },
478 { P_GPLL0_DIV, 6 },
479 { P_CORE_BI_PLL_TEST_SE, 7 }
480 };
481
482 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
483 { .fw_name = "xo", .name = "xo" },
484 { .hw = &mmpll0_out_even.clkr.hw },
485 { .hw = &mmpll7_out_even.clkr.hw },
486 { .hw = &mmpll10_out_even.clkr.hw },
487 { .fw_name = "gpll0", .name = "gpll0" },
488 { .hw = &gpll0_div.hw },
489 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
490 };
491
492 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
493 { P_XO, 0 },
494 { P_MMPLL0_OUT_EVEN, 1 },
495 { P_MMPLL4_OUT_EVEN, 2 },
496 { P_MMPLL7_OUT_EVEN, 3 },
497 { P_MMPLL10_OUT_EVEN, 4 },
498 { P_GPLL0, 5 },
499 { P_GPLL0_DIV, 6 },
500 { P_CORE_BI_PLL_TEST_SE, 7 }
501 };
502
503 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
504 { .fw_name = "xo", .name = "xo" },
505 { .hw = &mmpll0_out_even.clkr.hw },
506 { .hw = &mmpll4_out_even.clkr.hw },
507 { .hw = &mmpll7_out_even.clkr.hw },
508 { .hw = &mmpll10_out_even.clkr.hw },
509 { .fw_name = "gpll0", .name = "gpll0" },
510 { .hw = &gpll0_div.hw },
511 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
512 };
513
514 static struct clk_rcg2 byte0_clk_src = {
515 .cmd_rcgr = 0x2120,
516 .hid_width = 5,
517 .parent_map = mmss_xo_dsibyte_map,
518 .clkr.hw.init = &(struct clk_init_data){
519 .name = "byte0_clk_src",
520 .parent_data = mmss_xo_dsibyte,
521 .num_parents = 4,
522 .ops = &clk_byte2_ops,
523 .flags = CLK_SET_RATE_PARENT,
524 },
525 };
526
527 static struct clk_rcg2 byte1_clk_src = {
528 .cmd_rcgr = 0x2140,
529 .hid_width = 5,
530 .parent_map = mmss_xo_dsibyte_map,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "byte1_clk_src",
533 .parent_data = mmss_xo_dsibyte,
534 .num_parents = 4,
535 .ops = &clk_byte2_ops,
536 .flags = CLK_SET_RATE_PARENT,
537 },
538 };
539
540 static const struct freq_tbl ftbl_cci_clk_src[] = {
541 F(37500000, P_GPLL0, 16, 0, 0),
542 F(50000000, P_GPLL0, 12, 0, 0),
543 F(100000000, P_GPLL0, 6, 0, 0),
544 { }
545 };
546
547 static struct clk_rcg2 cci_clk_src = {
548 .cmd_rcgr = 0x3300,
549 .hid_width = 5,
550 .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
551 .freq_tbl = ftbl_cci_clk_src,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "cci_clk_src",
554 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
555 .num_parents = 7,
556 .ops = &clk_rcg2_ops,
557 },
558 };
559
560 static const struct freq_tbl ftbl_cpp_clk_src[] = {
561 F(100000000, P_GPLL0, 6, 0, 0),
562 F(200000000, P_GPLL0, 3, 0, 0),
563 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
564 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
565 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
566 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
567 F(600000000, P_GPLL0, 1, 0, 0),
568 { }
569 };
570
571 static struct clk_rcg2 cpp_clk_src = {
572 .cmd_rcgr = 0x3640,
573 .hid_width = 5,
574 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
575 .freq_tbl = ftbl_cpp_clk_src,
576 .clkr.hw.init = &(struct clk_init_data){
577 .name = "cpp_clk_src",
578 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
579 .num_parents = 8,
580 .ops = &clk_rcg2_ops,
581 },
582 };
583
584 static const struct freq_tbl ftbl_csi_clk_src[] = {
585 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
586 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
587 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
588 F(300000000, P_GPLL0, 2, 0, 0),
589 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
590 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
591 { }
592 };
593
594 static struct clk_rcg2 csi0_clk_src = {
595 .cmd_rcgr = 0x3090,
596 .hid_width = 5,
597 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
598 .freq_tbl = ftbl_csi_clk_src,
599 .clkr.hw.init = &(struct clk_init_data){
600 .name = "csi0_clk_src",
601 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
602 .num_parents = 8,
603 .ops = &clk_rcg2_ops,
604 },
605 };
606
607 static struct clk_rcg2 csi1_clk_src = {
608 .cmd_rcgr = 0x3100,
609 .hid_width = 5,
610 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
611 .freq_tbl = ftbl_csi_clk_src,
612 .clkr.hw.init = &(struct clk_init_data){
613 .name = "csi1_clk_src",
614 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
615 .num_parents = 8,
616 .ops = &clk_rcg2_ops,
617 },
618 };
619
620 static struct clk_rcg2 csi2_clk_src = {
621 .cmd_rcgr = 0x3160,
622 .hid_width = 5,
623 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
624 .freq_tbl = ftbl_csi_clk_src,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "csi2_clk_src",
627 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
628 .num_parents = 8,
629 .ops = &clk_rcg2_ops,
630 },
631 };
632
633 static struct clk_rcg2 csi3_clk_src = {
634 .cmd_rcgr = 0x31c0,
635 .hid_width = 5,
636 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
637 .freq_tbl = ftbl_csi_clk_src,
638 .clkr.hw.init = &(struct clk_init_data){
639 .name = "csi3_clk_src",
640 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
641 .num_parents = 8,
642 .ops = &clk_rcg2_ops,
643 },
644 };
645
646 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
647 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
648 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
649 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
650 F(300000000, P_GPLL0, 2, 0, 0),
651 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
652 { }
653 };
654
655 static struct clk_rcg2 csiphy_clk_src = {
656 .cmd_rcgr = 0x3800,
657 .hid_width = 5,
658 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
659 .freq_tbl = ftbl_csiphy_clk_src,
660 .clkr.hw.init = &(struct clk_init_data){
661 .name = "csiphy_clk_src",
662 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
663 .num_parents = 8,
664 .ops = &clk_rcg2_ops,
665 },
666 };
667
668 static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
669 F(200000000, P_GPLL0, 3, 0, 0),
670 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
671 { }
672 };
673
674 static struct clk_rcg2 csi0phytimer_clk_src = {
675 .cmd_rcgr = 0x3000,
676 .hid_width = 5,
677 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
678 .freq_tbl = ftbl_csiphytimer_clk_src,
679 .clkr.hw.init = &(struct clk_init_data){
680 .name = "csi0phytimer_clk_src",
681 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
682 .num_parents = 8,
683 .ops = &clk_rcg2_ops,
684 },
685 };
686
687 static struct clk_rcg2 csi1phytimer_clk_src = {
688 .cmd_rcgr = 0x3030,
689 .hid_width = 5,
690 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
691 .freq_tbl = ftbl_csiphytimer_clk_src,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "csi1phytimer_clk_src",
694 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
695 .num_parents = 8,
696 .ops = &clk_rcg2_ops,
697 },
698 };
699
700 static struct clk_rcg2 csi2phytimer_clk_src = {
701 .cmd_rcgr = 0x3060,
702 .hid_width = 5,
703 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
704 .freq_tbl = ftbl_csiphytimer_clk_src,
705 .clkr.hw.init = &(struct clk_init_data){
706 .name = "csi2phytimer_clk_src",
707 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
708 .num_parents = 8,
709 .ops = &clk_rcg2_ops,
710 },
711 };
712
713 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
714 F(19200000, P_XO, 1, 0, 0),
715 { }
716 };
717
718 static struct clk_rcg2 dp_aux_clk_src = {
719 .cmd_rcgr = 0x2260,
720 .hid_width = 5,
721 .parent_map = mmss_xo_gpll0_gpll0_div_map,
722 .freq_tbl = ftbl_dp_aux_clk_src,
723 .clkr.hw.init = &(struct clk_init_data){
724 .name = "dp_aux_clk_src",
725 .parent_data = mmss_xo_gpll0_gpll0_div,
726 .num_parents = 4,
727 .ops = &clk_rcg2_ops,
728 },
729 };
730
731 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
732 F(101250, P_DPLINK, 1, 5, 16),
733 F(168750, P_DPLINK, 1, 5, 16),
734 F(337500, P_DPLINK, 1, 5, 16),
735 { }
736 };
737
738 static struct clk_rcg2 dp_crypto_clk_src = {
739 .cmd_rcgr = 0x2220,
740 .hid_width = 5,
741 .parent_map = mmss_xo_dp_map,
742 .freq_tbl = ftbl_dp_crypto_clk_src,
743 .clkr.hw.init = &(struct clk_init_data){
744 .name = "dp_crypto_clk_src",
745 .parent_data = mmss_xo_dp,
746 .num_parents = 4,
747 .ops = &clk_rcg2_ops,
748 },
749 };
750
751 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
752 F(162000, P_DPLINK, 2, 0, 0),
753 F(270000, P_DPLINK, 2, 0, 0),
754 F(540000, P_DPLINK, 2, 0, 0),
755 { }
756 };
757
758 static struct clk_rcg2 dp_link_clk_src = {
759 .cmd_rcgr = 0x2200,
760 .hid_width = 5,
761 .parent_map = mmss_xo_dp_map,
762 .freq_tbl = ftbl_dp_link_clk_src,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "dp_link_clk_src",
765 .parent_data = mmss_xo_dp,
766 .num_parents = 4,
767 .ops = &clk_rcg2_ops,
768 },
769 };
770
771 static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
772 F(154000000, P_DPVCO, 1, 0, 0),
773 F(337500000, P_DPVCO, 2, 0, 0),
774 F(675000000, P_DPVCO, 2, 0, 0),
775 { }
776 };
777
778 static struct clk_rcg2 dp_pixel_clk_src = {
779 .cmd_rcgr = 0x2240,
780 .hid_width = 5,
781 .parent_map = mmss_xo_dp_map,
782 .freq_tbl = ftbl_dp_pixel_clk_src,
783 .clkr.hw.init = &(struct clk_init_data){
784 .name = "dp_pixel_clk_src",
785 .parent_data = mmss_xo_dp,
786 .num_parents = 4,
787 .ops = &clk_rcg2_ops,
788 },
789 };
790
791 static const struct freq_tbl ftbl_esc_clk_src[] = {
792 F(19200000, P_XO, 1, 0, 0),
793 { }
794 };
795
796 static struct clk_rcg2 esc0_clk_src = {
797 .cmd_rcgr = 0x2160,
798 .hid_width = 5,
799 .parent_map = mmss_xo_dsibyte_map,
800 .freq_tbl = ftbl_esc_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "esc0_clk_src",
803 .parent_data = mmss_xo_dsibyte,
804 .num_parents = 4,
805 .ops = &clk_rcg2_ops,
806 },
807 };
808
809 static struct clk_rcg2 esc1_clk_src = {
810 .cmd_rcgr = 0x2180,
811 .hid_width = 5,
812 .parent_map = mmss_xo_dsibyte_map,
813 .freq_tbl = ftbl_esc_clk_src,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "esc1_clk_src",
816 .parent_data = mmss_xo_dsibyte,
817 .num_parents = 4,
818 .ops = &clk_rcg2_ops,
819 },
820 };
821
822 static const struct freq_tbl ftbl_extpclk_clk_src[] = {
823 { .src = P_HDMIPLL },
824 { }
825 };
826
827 static struct clk_rcg2 extpclk_clk_src = {
828 .cmd_rcgr = 0x2060,
829 .hid_width = 5,
830 .parent_map = mmss_xo_hdmi_map,
831 .freq_tbl = ftbl_extpclk_clk_src,
832 .clkr.hw.init = &(struct clk_init_data){
833 .name = "extpclk_clk_src",
834 .parent_data = mmss_xo_hdmi,
835 .num_parents = 3,
836 .ops = &clk_byte_ops,
837 .flags = CLK_SET_RATE_PARENT,
838 },
839 };
840
841 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
842 F(100000000, P_GPLL0, 6, 0, 0),
843 F(200000000, P_GPLL0, 3, 0, 0),
844 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
845 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
846 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
847 { }
848 };
849
850 static struct clk_rcg2 fd_core_clk_src = {
851 .cmd_rcgr = 0x3b00,
852 .hid_width = 5,
853 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
854 .freq_tbl = ftbl_fd_core_clk_src,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "fd_core_clk_src",
857 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
858 .num_parents = 8,
859 .ops = &clk_rcg2_ops,
860 },
861 };
862
863 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
864 F(19200000, P_XO, 1, 0, 0),
865 { }
866 };
867
868 static struct clk_rcg2 hdmi_clk_src = {
869 .cmd_rcgr = 0x2100,
870 .hid_width = 5,
871 .parent_map = mmss_xo_gpll0_gpll0_div_map,
872 .freq_tbl = ftbl_hdmi_clk_src,
873 .clkr.hw.init = &(struct clk_init_data){
874 .name = "hdmi_clk_src",
875 .parent_data = mmss_xo_gpll0_gpll0_div,
876 .num_parents = 4,
877 .ops = &clk_rcg2_ops,
878 },
879 };
880
881 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
882 F(75000000, P_GPLL0, 8, 0, 0),
883 F(150000000, P_GPLL0, 4, 0, 0),
884 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
885 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
886 { }
887 };
888
889 static struct clk_rcg2 jpeg0_clk_src = {
890 .cmd_rcgr = 0x3500,
891 .hid_width = 5,
892 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
893 .freq_tbl = ftbl_jpeg0_clk_src,
894 .clkr.hw.init = &(struct clk_init_data){
895 .name = "jpeg0_clk_src",
896 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
897 .num_parents = 8,
898 .ops = &clk_rcg2_ops,
899 },
900 };
901
902 static const struct freq_tbl ftbl_maxi_clk_src[] = {
903 F(19200000, P_XO, 1, 0, 0),
904 F(75000000, P_GPLL0_DIV, 4, 0, 0),
905 F(171428571, P_GPLL0, 3.5, 0, 0),
906 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
907 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
908 { }
909 };
910
911 static struct clk_rcg2 maxi_clk_src = {
912 .cmd_rcgr = 0xf020,
913 .hid_width = 5,
914 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
915 .freq_tbl = ftbl_maxi_clk_src,
916 .clkr.hw.init = &(struct clk_init_data){
917 .name = "maxi_clk_src",
918 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
919 .num_parents = 6,
920 .ops = &clk_rcg2_ops,
921 },
922 };
923
924 static const struct freq_tbl ftbl_mclk_clk_src[] = {
925 F(4800000, P_XO, 4, 0, 0),
926 F(6000000, P_GPLL0_DIV, 10, 1, 5),
927 F(8000000, P_GPLL0_DIV, 1, 2, 75),
928 F(9600000, P_XO, 2, 0, 0),
929 F(16666667, P_GPLL0_DIV, 2, 1, 9),
930 F(19200000, P_XO, 1, 0, 0),
931 F(24000000, P_GPLL0_DIV, 1, 2, 25),
932 F(33333333, P_GPLL0_DIV, 1, 2, 9),
933 F(48000000, P_GPLL0, 1, 2, 25),
934 F(66666667, P_GPLL0, 1, 2, 9),
935 { }
936 };
937
938 static struct clk_rcg2 mclk0_clk_src = {
939 .cmd_rcgr = 0x3360,
940 .hid_width = 5,
941 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
942 .freq_tbl = ftbl_mclk_clk_src,
943 .clkr.hw.init = &(struct clk_init_data){
944 .name = "mclk0_clk_src",
945 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
946 .num_parents = 7,
947 .ops = &clk_rcg2_ops,
948 },
949 };
950
951 static struct clk_rcg2 mclk1_clk_src = {
952 .cmd_rcgr = 0x3390,
953 .hid_width = 5,
954 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
955 .freq_tbl = ftbl_mclk_clk_src,
956 .clkr.hw.init = &(struct clk_init_data){
957 .name = "mclk1_clk_src",
958 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
959 .num_parents = 7,
960 .ops = &clk_rcg2_ops,
961 },
962 };
963
964 static struct clk_rcg2 mclk2_clk_src = {
965 .cmd_rcgr = 0x33c0,
966 .hid_width = 5,
967 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
968 .freq_tbl = ftbl_mclk_clk_src,
969 .clkr.hw.init = &(struct clk_init_data){
970 .name = "mclk2_clk_src",
971 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
972 .num_parents = 7,
973 .ops = &clk_rcg2_ops,
974 },
975 };
976
977 static struct clk_rcg2 mclk3_clk_src = {
978 .cmd_rcgr = 0x33f0,
979 .hid_width = 5,
980 .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
981 .freq_tbl = ftbl_mclk_clk_src,
982 .clkr.hw.init = &(struct clk_init_data){
983 .name = "mclk3_clk_src",
984 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
985 .num_parents = 7,
986 .ops = &clk_rcg2_ops,
987 },
988 };
989
990 static const struct freq_tbl ftbl_mdp_clk_src[] = {
991 F(85714286, P_GPLL0, 7, 0, 0),
992 F(100000000, P_GPLL0, 6, 0, 0),
993 F(150000000, P_GPLL0, 4, 0, 0),
994 F(171428571, P_GPLL0, 3.5, 0, 0),
995 F(200000000, P_GPLL0, 3, 0, 0),
996 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
997 F(300000000, P_GPLL0, 2, 0, 0),
998 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
999 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1000 { }
1001 };
1002
1003 static struct clk_rcg2 mdp_clk_src = {
1004 .cmd_rcgr = 0x2040,
1005 .hid_width = 5,
1006 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1007 .freq_tbl = ftbl_mdp_clk_src,
1008 .clkr.hw.init = &(struct clk_init_data){
1009 .name = "mdp_clk_src",
1010 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1011 .num_parents = 6,
1012 .ops = &clk_rcg2_ops,
1013 },
1014 };
1015
1016 static const struct freq_tbl ftbl_vsync_clk_src[] = {
1017 F(19200000, P_XO, 1, 0, 0),
1018 { }
1019 };
1020
1021 static struct clk_rcg2 vsync_clk_src = {
1022 .cmd_rcgr = 0x2080,
1023 .hid_width = 5,
1024 .parent_map = mmss_xo_gpll0_gpll0_div_map,
1025 .freq_tbl = ftbl_vsync_clk_src,
1026 .clkr.hw.init = &(struct clk_init_data){
1027 .name = "vsync_clk_src",
1028 .parent_data = mmss_xo_gpll0_gpll0_div,
1029 .num_parents = 4,
1030 .ops = &clk_rcg2_ops,
1031 },
1032 };
1033
1034 static const struct freq_tbl ftbl_ahb_clk_src[] = {
1035 F(19200000, P_XO, 1, 0, 0),
1036 F(40000000, P_GPLL0, 15, 0, 0),
1037 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
1038 { }
1039 };
1040
1041 static struct clk_rcg2 ahb_clk_src = {
1042 .cmd_rcgr = 0x5000,
1043 .hid_width = 5,
1044 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
1045 .freq_tbl = ftbl_ahb_clk_src,
1046 .clkr.hw.init = &(struct clk_init_data){
1047 .name = "ahb_clk_src",
1048 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
1049 .num_parents = 5,
1050 .ops = &clk_rcg2_ops,
1051 },
1052 };
1053
1054 static const struct freq_tbl ftbl_axi_clk_src[] = {
1055 F(75000000, P_GPLL0, 8, 0, 0),
1056 F(171428571, P_GPLL0, 3.5, 0, 0),
1057 F(240000000, P_GPLL0, 2.5, 0, 0),
1058 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1059 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1060 { }
1061 };
1062
1063 /* RO to linux */
1064 static struct clk_rcg2 axi_clk_src = {
1065 .cmd_rcgr = 0xd000,
1066 .hid_width = 5,
1067 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
1068 .freq_tbl = ftbl_axi_clk_src,
1069 .clkr.hw.init = &(struct clk_init_data){
1070 .name = "axi_clk_src",
1071 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
1072 .num_parents = 6,
1073 .ops = &clk_rcg2_ops,
1074 },
1075 };
1076
1077 static struct clk_rcg2 pclk0_clk_src = {
1078 .cmd_rcgr = 0x2000,
1079 .mnd_width = 8,
1080 .hid_width = 5,
1081 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1082 .clkr.hw.init = &(struct clk_init_data){
1083 .name = "pclk0_clk_src",
1084 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1085 .num_parents = 4,
1086 .ops = &clk_pixel_ops,
1087 .flags = CLK_SET_RATE_PARENT,
1088 },
1089 };
1090
1091 static struct clk_rcg2 pclk1_clk_src = {
1092 .cmd_rcgr = 0x2020,
1093 .mnd_width = 8,
1094 .hid_width = 5,
1095 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1096 .clkr.hw.init = &(struct clk_init_data){
1097 .name = "pclk1_clk_src",
1098 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1099 .num_parents = 4,
1100 .ops = &clk_pixel_ops,
1101 .flags = CLK_SET_RATE_PARENT,
1102 },
1103 };
1104
1105 static const struct freq_tbl ftbl_rot_clk_src[] = {
1106 F(171428571, P_GPLL0, 3.5, 0, 0),
1107 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1108 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1109 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1110 { }
1111 };
1112
1113 static struct clk_rcg2 rot_clk_src = {
1114 .cmd_rcgr = 0x21a0,
1115 .hid_width = 5,
1116 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1117 .freq_tbl = ftbl_rot_clk_src,
1118 .clkr.hw.init = &(struct clk_init_data){
1119 .name = "rot_clk_src",
1120 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1121 .num_parents = 6,
1122 .ops = &clk_rcg2_ops,
1123 },
1124 };
1125
1126 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1127 F(200000000, P_GPLL0, 3, 0, 0),
1128 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1129 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1130 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1131 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1132 { }
1133 };
1134
1135 static struct clk_rcg2 video_core_clk_src = {
1136 .cmd_rcgr = 0x1000,
1137 .hid_width = 5,
1138 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1139 .freq_tbl = ftbl_video_core_clk_src,
1140 .clkr.hw.init = &(struct clk_init_data){
1141 .name = "video_core_clk_src",
1142 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1143 .num_parents = 7,
1144 .ops = &clk_rcg2_ops,
1145 },
1146 };
1147
1148 static struct clk_rcg2 video_subcore0_clk_src = {
1149 .cmd_rcgr = 0x1060,
1150 .hid_width = 5,
1151 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1152 .freq_tbl = ftbl_video_core_clk_src,
1153 .clkr.hw.init = &(struct clk_init_data){
1154 .name = "video_subcore0_clk_src",
1155 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1156 .num_parents = 7,
1157 .ops = &clk_rcg2_ops,
1158 },
1159 };
1160
1161 static struct clk_rcg2 video_subcore1_clk_src = {
1162 .cmd_rcgr = 0x1080,
1163 .hid_width = 5,
1164 .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1165 .freq_tbl = ftbl_video_core_clk_src,
1166 .clkr.hw.init = &(struct clk_init_data){
1167 .name = "video_subcore1_clk_src",
1168 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1169 .num_parents = 7,
1170 .ops = &clk_rcg2_ops,
1171 },
1172 };
1173
1174 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1175 F(200000000, P_GPLL0, 3, 0, 0),
1176 F(300000000, P_GPLL0, 2, 0, 0),
1177 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1178 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1179 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1180 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1181 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1182 F(600000000, P_GPLL0, 1, 0, 0),
1183 { }
1184 };
1185
1186 static struct clk_rcg2 vfe0_clk_src = {
1187 .cmd_rcgr = 0x3600,
1188 .hid_width = 5,
1189 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1190 .freq_tbl = ftbl_vfe_clk_src,
1191 .clkr.hw.init = &(struct clk_init_data){
1192 .name = "vfe0_clk_src",
1193 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1194 .num_parents = 8,
1195 .ops = &clk_rcg2_ops,
1196 },
1197 };
1198
1199 static struct clk_rcg2 vfe1_clk_src = {
1200 .cmd_rcgr = 0x3620,
1201 .hid_width = 5,
1202 .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1203 .freq_tbl = ftbl_vfe_clk_src,
1204 .clkr.hw.init = &(struct clk_init_data){
1205 .name = "vfe1_clk_src",
1206 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1207 .num_parents = 8,
1208 .ops = &clk_rcg2_ops,
1209 },
1210 };
1211
1212 static struct clk_branch misc_ahb_clk = {
1213 .halt_reg = 0x328,
1214 .clkr = {
1215 .enable_reg = 0x328,
1216 .enable_mask = BIT(0),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "misc_ahb_clk",
1219 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1220 .num_parents = 1,
1221 .ops = &clk_branch2_ops,
1222 .flags = CLK_SET_RATE_PARENT,
1223 },
1224 },
1225 };
1226
1227 static struct clk_branch video_core_clk = {
1228 .halt_reg = 0x1028,
1229 .clkr = {
1230 .enable_reg = 0x1028,
1231 .enable_mask = BIT(0),
1232 .hw.init = &(struct clk_init_data){
1233 .name = "video_core_clk",
1234 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
1235 .num_parents = 1,
1236 .ops = &clk_branch2_ops,
1237 .flags = CLK_SET_RATE_PARENT,
1238 },
1239 },
1240 };
1241
1242 static struct clk_branch video_ahb_clk = {
1243 .halt_reg = 0x1030,
1244 .clkr = {
1245 .enable_reg = 0x1030,
1246 .enable_mask = BIT(0),
1247 .hw.init = &(struct clk_init_data){
1248 .name = "video_ahb_clk",
1249 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1250 .num_parents = 1,
1251 .ops = &clk_branch2_ops,
1252 .flags = CLK_SET_RATE_PARENT,
1253 },
1254 },
1255 };
1256
1257 static struct clk_branch video_axi_clk = {
1258 .halt_reg = 0x1034,
1259 .clkr = {
1260 .enable_reg = 0x1034,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "video_axi_clk",
1264 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1265 .num_parents = 1,
1266 .ops = &clk_branch2_ops,
1267 },
1268 },
1269 };
1270
1271 static struct clk_branch video_maxi_clk = {
1272 .halt_reg = 0x1038,
1273 .clkr = {
1274 .enable_reg = 0x1038,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "video_maxi_clk",
1278 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
1279 .num_parents = 1,
1280 .ops = &clk_branch2_ops,
1281 .flags = CLK_SET_RATE_PARENT,
1282 },
1283 },
1284 };
1285
1286 static struct clk_branch video_subcore0_clk = {
1287 .halt_reg = 0x1048,
1288 .clkr = {
1289 .enable_reg = 0x1048,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "video_subcore0_clk",
1293 .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
1294 .num_parents = 1,
1295 .ops = &clk_branch2_ops,
1296 .flags = CLK_SET_RATE_PARENT,
1297 },
1298 },
1299 };
1300
1301 static struct clk_branch video_subcore1_clk = {
1302 .halt_reg = 0x104c,
1303 .clkr = {
1304 .enable_reg = 0x104c,
1305 .enable_mask = BIT(0),
1306 .hw.init = &(struct clk_init_data){
1307 .name = "video_subcore1_clk",
1308 .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
1309 .num_parents = 1,
1310 .ops = &clk_branch2_ops,
1311 .flags = CLK_SET_RATE_PARENT,
1312 },
1313 },
1314 };
1315
1316 static struct clk_branch mdss_ahb_clk = {
1317 .halt_reg = 0x2308,
1318 .clkr = {
1319 .enable_reg = 0x2308,
1320 .enable_mask = BIT(0),
1321 .hw.init = &(struct clk_init_data){
1322 .name = "mdss_ahb_clk",
1323 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1324 .num_parents = 1,
1325 .ops = &clk_branch2_ops,
1326 .flags = CLK_SET_RATE_PARENT,
1327 },
1328 },
1329 };
1330
1331 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
1332 .halt_reg = 0x230c,
1333 .clkr = {
1334 .enable_reg = 0x230c,
1335 .enable_mask = BIT(0),
1336 .hw.init = &(struct clk_init_data){
1337 .name = "mdss_hdmi_dp_ahb_clk",
1338 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1339 .num_parents = 1,
1340 .ops = &clk_branch2_ops,
1341 .flags = CLK_SET_RATE_PARENT,
1342 },
1343 },
1344 };
1345
1346 static struct clk_branch mdss_axi_clk = {
1347 .halt_reg = 0x2310,
1348 .clkr = {
1349 .enable_reg = 0x2310,
1350 .enable_mask = BIT(0),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "mdss_axi_clk",
1353 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1354 .num_parents = 1,
1355 .ops = &clk_branch2_ops,
1356 },
1357 },
1358 };
1359
1360 static struct clk_branch mdss_pclk0_clk = {
1361 .halt_reg = 0x2314,
1362 .clkr = {
1363 .enable_reg = 0x2314,
1364 .enable_mask = BIT(0),
1365 .hw.init = &(struct clk_init_data){
1366 .name = "mdss_pclk0_clk",
1367 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1368 .num_parents = 1,
1369 .ops = &clk_branch2_ops,
1370 .flags = CLK_SET_RATE_PARENT,
1371 },
1372 },
1373 };
1374
1375 static struct clk_branch mdss_pclk1_clk = {
1376 .halt_reg = 0x2318,
1377 .clkr = {
1378 .enable_reg = 0x2318,
1379 .enable_mask = BIT(0),
1380 .hw.init = &(struct clk_init_data){
1381 .name = "mdss_pclk1_clk",
1382 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1383 .num_parents = 1,
1384 .ops = &clk_branch2_ops,
1385 .flags = CLK_SET_RATE_PARENT,
1386 },
1387 },
1388 };
1389
1390 static struct clk_branch mdss_mdp_clk = {
1391 .halt_reg = 0x231c,
1392 .clkr = {
1393 .enable_reg = 0x231c,
1394 .enable_mask = BIT(0),
1395 .hw.init = &(struct clk_init_data){
1396 .name = "mdss_mdp_clk",
1397 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1398 .num_parents = 1,
1399 .ops = &clk_branch2_ops,
1400 .flags = CLK_SET_RATE_PARENT,
1401 },
1402 },
1403 };
1404
1405 static struct clk_branch mdss_mdp_lut_clk = {
1406 .halt_reg = 0x2320,
1407 .clkr = {
1408 .enable_reg = 0x2320,
1409 .enable_mask = BIT(0),
1410 .hw.init = &(struct clk_init_data){
1411 .name = "mdss_mdp_lut_clk",
1412 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1413 .num_parents = 1,
1414 .ops = &clk_branch2_ops,
1415 .flags = CLK_SET_RATE_PARENT,
1416 },
1417 },
1418 };
1419
1420 static struct clk_branch mdss_extpclk_clk = {
1421 .halt_reg = 0x2324,
1422 .clkr = {
1423 .enable_reg = 0x2324,
1424 .enable_mask = BIT(0),
1425 .hw.init = &(struct clk_init_data){
1426 .name = "mdss_extpclk_clk",
1427 .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1428 .num_parents = 1,
1429 .ops = &clk_branch2_ops,
1430 .flags = CLK_SET_RATE_PARENT,
1431 },
1432 },
1433 };
1434
1435 static struct clk_branch mdss_vsync_clk = {
1436 .halt_reg = 0x2328,
1437 .clkr = {
1438 .enable_reg = 0x2328,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "mdss_vsync_clk",
1442 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1443 .num_parents = 1,
1444 .ops = &clk_branch2_ops,
1445 .flags = CLK_SET_RATE_PARENT,
1446 },
1447 },
1448 };
1449
1450 static struct clk_branch mdss_hdmi_clk = {
1451 .halt_reg = 0x2338,
1452 .clkr = {
1453 .enable_reg = 0x2338,
1454 .enable_mask = BIT(0),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "mdss_hdmi_clk",
1457 .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1458 .num_parents = 1,
1459 .ops = &clk_branch2_ops,
1460 .flags = CLK_SET_RATE_PARENT,
1461 },
1462 },
1463 };
1464
1465 static struct clk_branch mdss_byte0_clk = {
1466 .halt_reg = 0x233c,
1467 .clkr = {
1468 .enable_reg = 0x233c,
1469 .enable_mask = BIT(0),
1470 .hw.init = &(struct clk_init_data){
1471 .name = "mdss_byte0_clk",
1472 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1473 .num_parents = 1,
1474 .ops = &clk_branch2_ops,
1475 .flags = CLK_SET_RATE_PARENT,
1476 },
1477 },
1478 };
1479
1480 static struct clk_branch mdss_byte1_clk = {
1481 .halt_reg = 0x2340,
1482 .clkr = {
1483 .enable_reg = 0x2340,
1484 .enable_mask = BIT(0),
1485 .hw.init = &(struct clk_init_data){
1486 .name = "mdss_byte1_clk",
1487 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1488 .num_parents = 1,
1489 .ops = &clk_branch2_ops,
1490 .flags = CLK_SET_RATE_PARENT,
1491 },
1492 },
1493 };
1494
1495 static struct clk_branch mdss_esc0_clk = {
1496 .halt_reg = 0x2344,
1497 .clkr = {
1498 .enable_reg = 0x2344,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "mdss_esc0_clk",
1502 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1503 .num_parents = 1,
1504 .ops = &clk_branch2_ops,
1505 .flags = CLK_SET_RATE_PARENT,
1506 },
1507 },
1508 };
1509
1510 static struct clk_branch mdss_esc1_clk = {
1511 .halt_reg = 0x2348,
1512 .clkr = {
1513 .enable_reg = 0x2348,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "mdss_esc1_clk",
1517 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1518 .num_parents = 1,
1519 .ops = &clk_branch2_ops,
1520 .flags = CLK_SET_RATE_PARENT,
1521 },
1522 },
1523 };
1524
1525 static struct clk_branch mdss_rot_clk = {
1526 .halt_reg = 0x2350,
1527 .clkr = {
1528 .enable_reg = 0x2350,
1529 .enable_mask = BIT(0),
1530 .hw.init = &(struct clk_init_data){
1531 .name = "mdss_rot_clk",
1532 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
1533 .num_parents = 1,
1534 .ops = &clk_branch2_ops,
1535 .flags = CLK_SET_RATE_PARENT,
1536 },
1537 },
1538 };
1539
1540 static struct clk_branch mdss_dp_link_clk = {
1541 .halt_reg = 0x2354,
1542 .clkr = {
1543 .enable_reg = 0x2354,
1544 .enable_mask = BIT(0),
1545 .hw.init = &(struct clk_init_data){
1546 .name = "mdss_dp_link_clk",
1547 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1548 .num_parents = 1,
1549 .ops = &clk_branch2_ops,
1550 .flags = CLK_SET_RATE_PARENT,
1551 },
1552 },
1553 };
1554
1555 static struct clk_branch mdss_dp_link_intf_clk = {
1556 .halt_reg = 0x2358,
1557 .clkr = {
1558 .enable_reg = 0x2358,
1559 .enable_mask = BIT(0),
1560 .hw.init = &(struct clk_init_data){
1561 .name = "mdss_dp_link_intf_clk",
1562 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1563 .num_parents = 1,
1564 .ops = &clk_branch2_ops,
1565 .flags = CLK_SET_RATE_PARENT,
1566 },
1567 },
1568 };
1569
1570 static struct clk_branch mdss_dp_crypto_clk = {
1571 .halt_reg = 0x235c,
1572 .clkr = {
1573 .enable_reg = 0x235c,
1574 .enable_mask = BIT(0),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "mdss_dp_crypto_clk",
1577 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
1578 .num_parents = 1,
1579 .ops = &clk_branch2_ops,
1580 .flags = CLK_SET_RATE_PARENT,
1581 },
1582 },
1583 };
1584
1585 static struct clk_branch mdss_dp_pixel_clk = {
1586 .halt_reg = 0x2360,
1587 .clkr = {
1588 .enable_reg = 0x2360,
1589 .enable_mask = BIT(0),
1590 .hw.init = &(struct clk_init_data){
1591 .name = "mdss_dp_pixel_clk",
1592 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
1593 .num_parents = 1,
1594 .ops = &clk_branch2_ops,
1595 .flags = CLK_SET_RATE_PARENT,
1596 },
1597 },
1598 };
1599
1600 static struct clk_branch mdss_dp_aux_clk = {
1601 .halt_reg = 0x2364,
1602 .clkr = {
1603 .enable_reg = 0x2364,
1604 .enable_mask = BIT(0),
1605 .hw.init = &(struct clk_init_data){
1606 .name = "mdss_dp_aux_clk",
1607 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
1608 .num_parents = 1,
1609 .ops = &clk_branch2_ops,
1610 .flags = CLK_SET_RATE_PARENT,
1611 },
1612 },
1613 };
1614
1615 static struct clk_branch mdss_byte0_intf_clk = {
1616 .halt_reg = 0x2374,
1617 .clkr = {
1618 .enable_reg = 0x2374,
1619 .enable_mask = BIT(0),
1620 .hw.init = &(struct clk_init_data){
1621 .name = "mdss_byte0_intf_clk",
1622 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1623 .num_parents = 1,
1624 .ops = &clk_branch2_ops,
1625 .flags = CLK_SET_RATE_PARENT,
1626 },
1627 },
1628 };
1629
1630 static struct clk_branch mdss_byte1_intf_clk = {
1631 .halt_reg = 0x2378,
1632 .clkr = {
1633 .enable_reg = 0x2378,
1634 .enable_mask = BIT(0),
1635 .hw.init = &(struct clk_init_data){
1636 .name = "mdss_byte1_intf_clk",
1637 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1638 .num_parents = 1,
1639 .ops = &clk_branch2_ops,
1640 .flags = CLK_SET_RATE_PARENT,
1641 },
1642 },
1643 };
1644
1645 static struct clk_branch camss_csi0phytimer_clk = {
1646 .halt_reg = 0x3024,
1647 .clkr = {
1648 .enable_reg = 0x3024,
1649 .enable_mask = BIT(0),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "camss_csi0phytimer_clk",
1652 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1653 .num_parents = 1,
1654 .ops = &clk_branch2_ops,
1655 .flags = CLK_SET_RATE_PARENT,
1656 },
1657 },
1658 };
1659
1660 static struct clk_branch camss_csi1phytimer_clk = {
1661 .halt_reg = 0x3054,
1662 .clkr = {
1663 .enable_reg = 0x3054,
1664 .enable_mask = BIT(0),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "camss_csi1phytimer_clk",
1667 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1668 .num_parents = 1,
1669 .ops = &clk_branch2_ops,
1670 .flags = CLK_SET_RATE_PARENT,
1671 },
1672 },
1673 };
1674
1675 static struct clk_branch camss_csi2phytimer_clk = {
1676 .halt_reg = 0x3084,
1677 .clkr = {
1678 .enable_reg = 0x3084,
1679 .enable_mask = BIT(0),
1680 .hw.init = &(struct clk_init_data){
1681 .name = "camss_csi2phytimer_clk",
1682 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1683 .num_parents = 1,
1684 .ops = &clk_branch2_ops,
1685 .flags = CLK_SET_RATE_PARENT,
1686 },
1687 },
1688 };
1689
1690 static struct clk_branch camss_csi0_clk = {
1691 .halt_reg = 0x30b4,
1692 .clkr = {
1693 .enable_reg = 0x30b4,
1694 .enable_mask = BIT(0),
1695 .hw.init = &(struct clk_init_data){
1696 .name = "camss_csi0_clk",
1697 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1698 .num_parents = 1,
1699 .ops = &clk_branch2_ops,
1700 .flags = CLK_SET_RATE_PARENT,
1701 },
1702 },
1703 };
1704
1705 static struct clk_branch camss_csi0_ahb_clk = {
1706 .halt_reg = 0x30bc,
1707 .clkr = {
1708 .enable_reg = 0x30bc,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "camss_csi0_ahb_clk",
1712 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1713 .num_parents = 1,
1714 .ops = &clk_branch2_ops,
1715 .flags = CLK_SET_RATE_PARENT,
1716 },
1717 },
1718 };
1719
1720 static struct clk_branch camss_csi0rdi_clk = {
1721 .halt_reg = 0x30d4,
1722 .clkr = {
1723 .enable_reg = 0x30d4,
1724 .enable_mask = BIT(0),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "camss_csi0rdi_clk",
1727 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1728 .num_parents = 1,
1729 .ops = &clk_branch2_ops,
1730 .flags = CLK_SET_RATE_PARENT,
1731 },
1732 },
1733 };
1734
1735 static struct clk_branch camss_csi0pix_clk = {
1736 .halt_reg = 0x30e4,
1737 .clkr = {
1738 .enable_reg = 0x30e4,
1739 .enable_mask = BIT(0),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "camss_csi0pix_clk",
1742 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1743 .num_parents = 1,
1744 .ops = &clk_branch2_ops,
1745 .flags = CLK_SET_RATE_PARENT,
1746 },
1747 },
1748 };
1749
1750 static struct clk_branch camss_csi1_clk = {
1751 .halt_reg = 0x3124,
1752 .clkr = {
1753 .enable_reg = 0x3124,
1754 .enable_mask = BIT(0),
1755 .hw.init = &(struct clk_init_data){
1756 .name = "camss_csi1_clk",
1757 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1758 .num_parents = 1,
1759 .ops = &clk_branch2_ops,
1760 .flags = CLK_SET_RATE_PARENT,
1761 },
1762 },
1763 };
1764
1765 static struct clk_branch camss_csi1_ahb_clk = {
1766 .halt_reg = 0x3128,
1767 .clkr = {
1768 .enable_reg = 0x3128,
1769 .enable_mask = BIT(0),
1770 .hw.init = &(struct clk_init_data){
1771 .name = "camss_csi1_ahb_clk",
1772 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1773 .num_parents = 1,
1774 .ops = &clk_branch2_ops,
1775 .flags = CLK_SET_RATE_PARENT,
1776 },
1777 },
1778 };
1779
1780 static struct clk_branch camss_csi1rdi_clk = {
1781 .halt_reg = 0x3144,
1782 .clkr = {
1783 .enable_reg = 0x3144,
1784 .enable_mask = BIT(0),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "camss_csi1rdi_clk",
1787 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1788 .num_parents = 1,
1789 .ops = &clk_branch2_ops,
1790 .flags = CLK_SET_RATE_PARENT,
1791 },
1792 },
1793 };
1794
1795 static struct clk_branch camss_csi1pix_clk = {
1796 .halt_reg = 0x3154,
1797 .clkr = {
1798 .enable_reg = 0x3154,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "camss_csi1pix_clk",
1802 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1803 .num_parents = 1,
1804 .ops = &clk_branch2_ops,
1805 .flags = CLK_SET_RATE_PARENT,
1806 },
1807 },
1808 };
1809
1810 static struct clk_branch camss_csi2_clk = {
1811 .halt_reg = 0x3184,
1812 .clkr = {
1813 .enable_reg = 0x3184,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "camss_csi2_clk",
1817 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1818 .num_parents = 1,
1819 .ops = &clk_branch2_ops,
1820 .flags = CLK_SET_RATE_PARENT,
1821 },
1822 },
1823 };
1824
1825 static struct clk_branch camss_csi2_ahb_clk = {
1826 .halt_reg = 0x3188,
1827 .clkr = {
1828 .enable_reg = 0x3188,
1829 .enable_mask = BIT(0),
1830 .hw.init = &(struct clk_init_data){
1831 .name = "camss_csi2_ahb_clk",
1832 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1833 .num_parents = 1,
1834 .ops = &clk_branch2_ops,
1835 .flags = CLK_SET_RATE_PARENT,
1836 },
1837 },
1838 };
1839
1840 static struct clk_branch camss_csi2rdi_clk = {
1841 .halt_reg = 0x31a4,
1842 .clkr = {
1843 .enable_reg = 0x31a4,
1844 .enable_mask = BIT(0),
1845 .hw.init = &(struct clk_init_data){
1846 .name = "camss_csi2rdi_clk",
1847 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1848 .num_parents = 1,
1849 .ops = &clk_branch2_ops,
1850 .flags = CLK_SET_RATE_PARENT,
1851 },
1852 },
1853 };
1854
1855 static struct clk_branch camss_csi2pix_clk = {
1856 .halt_reg = 0x31b4,
1857 .clkr = {
1858 .enable_reg = 0x31b4,
1859 .enable_mask = BIT(0),
1860 .hw.init = &(struct clk_init_data){
1861 .name = "camss_csi2pix_clk",
1862 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1863 .num_parents = 1,
1864 .ops = &clk_branch2_ops,
1865 .flags = CLK_SET_RATE_PARENT,
1866 },
1867 },
1868 };
1869
1870 static struct clk_branch camss_csi3_clk = {
1871 .halt_reg = 0x31e4,
1872 .clkr = {
1873 .enable_reg = 0x31e4,
1874 .enable_mask = BIT(0),
1875 .hw.init = &(struct clk_init_data){
1876 .name = "camss_csi3_clk",
1877 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1878 .num_parents = 1,
1879 .ops = &clk_branch2_ops,
1880 .flags = CLK_SET_RATE_PARENT,
1881 },
1882 },
1883 };
1884
1885 static struct clk_branch camss_csi3_ahb_clk = {
1886 .halt_reg = 0x31e8,
1887 .clkr = {
1888 .enable_reg = 0x31e8,
1889 .enable_mask = BIT(0),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "camss_csi3_ahb_clk",
1892 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1893 .num_parents = 1,
1894 .ops = &clk_branch2_ops,
1895 .flags = CLK_SET_RATE_PARENT,
1896 },
1897 },
1898 };
1899
1900 static struct clk_branch camss_csi3rdi_clk = {
1901 .halt_reg = 0x3204,
1902 .clkr = {
1903 .enable_reg = 0x3204,
1904 .enable_mask = BIT(0),
1905 .hw.init = &(struct clk_init_data){
1906 .name = "camss_csi3rdi_clk",
1907 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1908 .num_parents = 1,
1909 .ops = &clk_branch2_ops,
1910 .flags = CLK_SET_RATE_PARENT,
1911 },
1912 },
1913 };
1914
1915 static struct clk_branch camss_csi3pix_clk = {
1916 .halt_reg = 0x3214,
1917 .clkr = {
1918 .enable_reg = 0x3214,
1919 .enable_mask = BIT(0),
1920 .hw.init = &(struct clk_init_data){
1921 .name = "camss_csi3pix_clk",
1922 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1923 .num_parents = 1,
1924 .ops = &clk_branch2_ops,
1925 .flags = CLK_SET_RATE_PARENT,
1926 },
1927 },
1928 };
1929
1930 static struct clk_branch camss_ispif_ahb_clk = {
1931 .halt_reg = 0x3224,
1932 .clkr = {
1933 .enable_reg = 0x3224,
1934 .enable_mask = BIT(0),
1935 .hw.init = &(struct clk_init_data){
1936 .name = "camss_ispif_ahb_clk",
1937 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1938 .num_parents = 1,
1939 .ops = &clk_branch2_ops,
1940 .flags = CLK_SET_RATE_PARENT,
1941 },
1942 },
1943 };
1944
1945 static struct clk_branch camss_cci_clk = {
1946 .halt_reg = 0x3344,
1947 .clkr = {
1948 .enable_reg = 0x3344,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data){
1951 .name = "camss_cci_clk",
1952 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1953 .num_parents = 1,
1954 .ops = &clk_branch2_ops,
1955 .flags = CLK_SET_RATE_PARENT,
1956 },
1957 },
1958 };
1959
1960 static struct clk_branch camss_cci_ahb_clk = {
1961 .halt_reg = 0x3348,
1962 .clkr = {
1963 .enable_reg = 0x3348,
1964 .enable_mask = BIT(0),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "camss_cci_ahb_clk",
1967 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1968 .num_parents = 1,
1969 .ops = &clk_branch2_ops,
1970 .flags = CLK_SET_RATE_PARENT,
1971 },
1972 },
1973 };
1974
1975 static struct clk_branch camss_mclk0_clk = {
1976 .halt_reg = 0x3384,
1977 .clkr = {
1978 .enable_reg = 0x3384,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "camss_mclk0_clk",
1982 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1983 .num_parents = 1,
1984 .ops = &clk_branch2_ops,
1985 .flags = CLK_SET_RATE_PARENT,
1986 },
1987 },
1988 };
1989
1990 static struct clk_branch camss_mclk1_clk = {
1991 .halt_reg = 0x33b4,
1992 .clkr = {
1993 .enable_reg = 0x33b4,
1994 .enable_mask = BIT(0),
1995 .hw.init = &(struct clk_init_data){
1996 .name = "camss_mclk1_clk",
1997 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1998 .num_parents = 1,
1999 .ops = &clk_branch2_ops,
2000 .flags = CLK_SET_RATE_PARENT,
2001 },
2002 },
2003 };
2004
2005 static struct clk_branch camss_mclk2_clk = {
2006 .halt_reg = 0x33e4,
2007 .clkr = {
2008 .enable_reg = 0x33e4,
2009 .enable_mask = BIT(0),
2010 .hw.init = &(struct clk_init_data){
2011 .name = "camss_mclk2_clk",
2012 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
2013 .num_parents = 1,
2014 .ops = &clk_branch2_ops,
2015 .flags = CLK_SET_RATE_PARENT,
2016 },
2017 },
2018 };
2019
2020 static struct clk_branch camss_mclk3_clk = {
2021 .halt_reg = 0x3414,
2022 .clkr = {
2023 .enable_reg = 0x3414,
2024 .enable_mask = BIT(0),
2025 .hw.init = &(struct clk_init_data){
2026 .name = "camss_mclk3_clk",
2027 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
2028 .num_parents = 1,
2029 .ops = &clk_branch2_ops,
2030 .flags = CLK_SET_RATE_PARENT,
2031 },
2032 },
2033 };
2034
2035 static struct clk_branch camss_top_ahb_clk = {
2036 .halt_reg = 0x3484,
2037 .clkr = {
2038 .enable_reg = 0x3484,
2039 .enable_mask = BIT(0),
2040 .hw.init = &(struct clk_init_data){
2041 .name = "camss_top_ahb_clk",
2042 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2043 .num_parents = 1,
2044 .ops = &clk_branch2_ops,
2045 .flags = CLK_SET_RATE_PARENT,
2046 },
2047 },
2048 };
2049
2050 static struct clk_branch camss_ahb_clk = {
2051 .halt_reg = 0x348c,
2052 .clkr = {
2053 .enable_reg = 0x348c,
2054 .enable_mask = BIT(0),
2055 .hw.init = &(struct clk_init_data){
2056 .name = "camss_ahb_clk",
2057 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2058 .num_parents = 1,
2059 .ops = &clk_branch2_ops,
2060 .flags = CLK_SET_RATE_PARENT,
2061 },
2062 },
2063 };
2064
2065 static struct clk_branch camss_micro_ahb_clk = {
2066 .halt_reg = 0x3494,
2067 .clkr = {
2068 .enable_reg = 0x3494,
2069 .enable_mask = BIT(0),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "camss_micro_ahb_clk",
2072 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2073 .num_parents = 1,
2074 .ops = &clk_branch2_ops,
2075 .flags = CLK_SET_RATE_PARENT,
2076 },
2077 },
2078 };
2079
2080 static struct clk_branch camss_jpeg0_clk = {
2081 .halt_reg = 0x35a8,
2082 .clkr = {
2083 .enable_reg = 0x35a8,
2084 .enable_mask = BIT(0),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "camss_jpeg0_clk",
2087 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
2088 .num_parents = 1,
2089 .ops = &clk_branch2_ops,
2090 .flags = CLK_SET_RATE_PARENT,
2091 },
2092 },
2093 };
2094
2095 static struct clk_branch camss_jpeg_ahb_clk = {
2096 .halt_reg = 0x35b4,
2097 .clkr = {
2098 .enable_reg = 0x35b4,
2099 .enable_mask = BIT(0),
2100 .hw.init = &(struct clk_init_data){
2101 .name = "camss_jpeg_ahb_clk",
2102 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2103 .num_parents = 1,
2104 .ops = &clk_branch2_ops,
2105 .flags = CLK_SET_RATE_PARENT,
2106 },
2107 },
2108 };
2109
2110 static struct clk_branch camss_jpeg_axi_clk = {
2111 .halt_reg = 0x35b8,
2112 .clkr = {
2113 .enable_reg = 0x35b8,
2114 .enable_mask = BIT(0),
2115 .hw.init = &(struct clk_init_data){
2116 .name = "camss_jpeg_axi_clk",
2117 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2118 .num_parents = 1,
2119 .ops = &clk_branch2_ops,
2120 },
2121 },
2122 };
2123
2124 static struct clk_branch camss_vfe0_ahb_clk = {
2125 .halt_reg = 0x3668,
2126 .clkr = {
2127 .enable_reg = 0x3668,
2128 .enable_mask = BIT(0),
2129 .hw.init = &(struct clk_init_data){
2130 .name = "camss_vfe0_ahb_clk",
2131 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2132 .num_parents = 1,
2133 .ops = &clk_branch2_ops,
2134 .flags = CLK_SET_RATE_PARENT,
2135 },
2136 },
2137 };
2138
2139 static struct clk_branch camss_vfe1_ahb_clk = {
2140 .halt_reg = 0x3678,
2141 .clkr = {
2142 .enable_reg = 0x3678,
2143 .enable_mask = BIT(0),
2144 .hw.init = &(struct clk_init_data){
2145 .name = "camss_vfe1_ahb_clk",
2146 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2147 .num_parents = 1,
2148 .ops = &clk_branch2_ops,
2149 .flags = CLK_SET_RATE_PARENT,
2150 },
2151 },
2152 };
2153
2154 static struct clk_branch camss_vfe0_clk = {
2155 .halt_reg = 0x36a8,
2156 .clkr = {
2157 .enable_reg = 0x36a8,
2158 .enable_mask = BIT(0),
2159 .hw.init = &(struct clk_init_data){
2160 .name = "camss_vfe0_clk",
2161 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2162 .num_parents = 1,
2163 .ops = &clk_branch2_ops,
2164 .flags = CLK_SET_RATE_PARENT,
2165 },
2166 },
2167 };
2168
2169 static struct clk_branch camss_vfe1_clk = {
2170 .halt_reg = 0x36ac,
2171 .clkr = {
2172 .enable_reg = 0x36ac,
2173 .enable_mask = BIT(0),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "camss_vfe1_clk",
2176 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2177 .num_parents = 1,
2178 .ops = &clk_branch2_ops,
2179 .flags = CLK_SET_RATE_PARENT,
2180 },
2181 },
2182 };
2183
2184 static struct clk_branch camss_cpp_clk = {
2185 .halt_reg = 0x36b0,
2186 .clkr = {
2187 .enable_reg = 0x36b0,
2188 .enable_mask = BIT(0),
2189 .hw.init = &(struct clk_init_data){
2190 .name = "camss_cpp_clk",
2191 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
2192 .num_parents = 1,
2193 .ops = &clk_branch2_ops,
2194 .flags = CLK_SET_RATE_PARENT,
2195 },
2196 },
2197 };
2198
2199 static struct clk_branch camss_cpp_ahb_clk = {
2200 .halt_reg = 0x36b4,
2201 .clkr = {
2202 .enable_reg = 0x36b4,
2203 .enable_mask = BIT(0),
2204 .hw.init = &(struct clk_init_data){
2205 .name = "camss_cpp_ahb_clk",
2206 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2207 .num_parents = 1,
2208 .ops = &clk_branch2_ops,
2209 .flags = CLK_SET_RATE_PARENT,
2210 },
2211 },
2212 };
2213
2214 static struct clk_branch camss_vfe_vbif_ahb_clk = {
2215 .halt_reg = 0x36b8,
2216 .clkr = {
2217 .enable_reg = 0x36b8,
2218 .enable_mask = BIT(0),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "camss_vfe_vbif_ahb_clk",
2221 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2222 .num_parents = 1,
2223 .ops = &clk_branch2_ops,
2224 .flags = CLK_SET_RATE_PARENT,
2225 },
2226 },
2227 };
2228
2229 static struct clk_branch camss_vfe_vbif_axi_clk = {
2230 .halt_reg = 0x36bc,
2231 .clkr = {
2232 .enable_reg = 0x36bc,
2233 .enable_mask = BIT(0),
2234 .hw.init = &(struct clk_init_data){
2235 .name = "camss_vfe_vbif_axi_clk",
2236 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2237 .num_parents = 1,
2238 .ops = &clk_branch2_ops,
2239 },
2240 },
2241 };
2242
2243 static struct clk_branch camss_cpp_axi_clk = {
2244 .halt_reg = 0x36c4,
2245 .clkr = {
2246 .enable_reg = 0x36c4,
2247 .enable_mask = BIT(0),
2248 .hw.init = &(struct clk_init_data){
2249 .name = "camss_cpp_axi_clk",
2250 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2251 .num_parents = 1,
2252 .ops = &clk_branch2_ops,
2253 },
2254 },
2255 };
2256
2257 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2258 .halt_reg = 0x36c8,
2259 .clkr = {
2260 .enable_reg = 0x36c8,
2261 .enable_mask = BIT(0),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "camss_cpp_vbif_ahb_clk",
2264 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2265 .num_parents = 1,
2266 .ops = &clk_branch2_ops,
2267 .flags = CLK_SET_RATE_PARENT,
2268 },
2269 },
2270 };
2271
2272 static struct clk_branch camss_csi_vfe0_clk = {
2273 .halt_reg = 0x3704,
2274 .clkr = {
2275 .enable_reg = 0x3704,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "camss_csi_vfe0_clk",
2279 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2280 .num_parents = 1,
2281 .ops = &clk_branch2_ops,
2282 .flags = CLK_SET_RATE_PARENT,
2283 },
2284 },
2285 };
2286
2287 static struct clk_branch camss_csi_vfe1_clk = {
2288 .halt_reg = 0x3714,
2289 .clkr = {
2290 .enable_reg = 0x3714,
2291 .enable_mask = BIT(0),
2292 .hw.init = &(struct clk_init_data){
2293 .name = "camss_csi_vfe1_clk",
2294 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2295 .num_parents = 1,
2296 .ops = &clk_branch2_ops,
2297 .flags = CLK_SET_RATE_PARENT,
2298 },
2299 },
2300 };
2301
2302 static struct clk_branch camss_vfe0_stream_clk = {
2303 .halt_reg = 0x3720,
2304 .clkr = {
2305 .enable_reg = 0x3720,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "camss_vfe0_stream_clk",
2309 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2310 .num_parents = 1,
2311 .ops = &clk_branch2_ops,
2312 .flags = CLK_SET_RATE_PARENT,
2313 },
2314 },
2315 };
2316
2317 static struct clk_branch camss_vfe1_stream_clk = {
2318 .halt_reg = 0x3724,
2319 .clkr = {
2320 .enable_reg = 0x3724,
2321 .enable_mask = BIT(0),
2322 .hw.init = &(struct clk_init_data){
2323 .name = "camss_vfe1_stream_clk",
2324 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2325 .num_parents = 1,
2326 .ops = &clk_branch2_ops,
2327 .flags = CLK_SET_RATE_PARENT,
2328 },
2329 },
2330 };
2331
2332 static struct clk_branch camss_cphy_csid0_clk = {
2333 .halt_reg = 0x3730,
2334 .clkr = {
2335 .enable_reg = 0x3730,
2336 .enable_mask = BIT(0),
2337 .hw.init = &(struct clk_init_data){
2338 .name = "camss_cphy_csid0_clk",
2339 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2340 .num_parents = 1,
2341 .ops = &clk_branch2_ops,
2342 .flags = CLK_SET_RATE_PARENT,
2343 },
2344 },
2345 };
2346
2347 static struct clk_branch camss_cphy_csid1_clk = {
2348 .halt_reg = 0x3734,
2349 .clkr = {
2350 .enable_reg = 0x3734,
2351 .enable_mask = BIT(0),
2352 .hw.init = &(struct clk_init_data){
2353 .name = "camss_cphy_csid1_clk",
2354 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2355 .num_parents = 1,
2356 .ops = &clk_branch2_ops,
2357 .flags = CLK_SET_RATE_PARENT,
2358 },
2359 },
2360 };
2361
2362 static struct clk_branch camss_cphy_csid2_clk = {
2363 .halt_reg = 0x3738,
2364 .clkr = {
2365 .enable_reg = 0x3738,
2366 .enable_mask = BIT(0),
2367 .hw.init = &(struct clk_init_data){
2368 .name = "camss_cphy_csid2_clk",
2369 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2370 .num_parents = 1,
2371 .ops = &clk_branch2_ops,
2372 .flags = CLK_SET_RATE_PARENT,
2373 },
2374 },
2375 };
2376
2377 static struct clk_branch camss_cphy_csid3_clk = {
2378 .halt_reg = 0x373c,
2379 .clkr = {
2380 .enable_reg = 0x373c,
2381 .enable_mask = BIT(0),
2382 .hw.init = &(struct clk_init_data){
2383 .name = "camss_cphy_csid3_clk",
2384 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2385 .num_parents = 1,
2386 .ops = &clk_branch2_ops,
2387 .flags = CLK_SET_RATE_PARENT,
2388 },
2389 },
2390 };
2391
2392 static struct clk_branch camss_csiphy0_clk = {
2393 .halt_reg = 0x3740,
2394 .clkr = {
2395 .enable_reg = 0x3740,
2396 .enable_mask = BIT(0),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "camss_csiphy0_clk",
2399 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2400 .num_parents = 1,
2401 .ops = &clk_branch2_ops,
2402 .flags = CLK_SET_RATE_PARENT,
2403 },
2404 },
2405 };
2406
2407 static struct clk_branch camss_csiphy1_clk = {
2408 .halt_reg = 0x3744,
2409 .clkr = {
2410 .enable_reg = 0x3744,
2411 .enable_mask = BIT(0),
2412 .hw.init = &(struct clk_init_data){
2413 .name = "camss_csiphy1_clk",
2414 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2415 .num_parents = 1,
2416 .ops = &clk_branch2_ops,
2417 .flags = CLK_SET_RATE_PARENT,
2418 },
2419 },
2420 };
2421
2422 static struct clk_branch camss_csiphy2_clk = {
2423 .halt_reg = 0x3748,
2424 .clkr = {
2425 .enable_reg = 0x3748,
2426 .enable_mask = BIT(0),
2427 .hw.init = &(struct clk_init_data){
2428 .name = "camss_csiphy2_clk",
2429 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2430 .num_parents = 1,
2431 .ops = &clk_branch2_ops,
2432 .flags = CLK_SET_RATE_PARENT,
2433 },
2434 },
2435 };
2436
2437 static struct clk_branch fd_core_clk = {
2438 .halt_reg = 0x3b68,
2439 .clkr = {
2440 .enable_reg = 0x3b68,
2441 .enable_mask = BIT(0),
2442 .hw.init = &(struct clk_init_data){
2443 .name = "fd_core_clk",
2444 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2445 .num_parents = 1,
2446 .ops = &clk_branch2_ops,
2447 .flags = CLK_SET_RATE_PARENT,
2448 },
2449 },
2450 };
2451
2452 static struct clk_branch fd_core_uar_clk = {
2453 .halt_reg = 0x3b6c,
2454 .clkr = {
2455 .enable_reg = 0x3b6c,
2456 .enable_mask = BIT(0),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "fd_core_uar_clk",
2459 .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2460 .num_parents = 1,
2461 .ops = &clk_branch2_ops,
2462 .flags = CLK_SET_RATE_PARENT,
2463 },
2464 },
2465 };
2466
2467 static struct clk_branch fd_ahb_clk = {
2468 .halt_reg = 0x3b74,
2469 .clkr = {
2470 .enable_reg = 0x3b74,
2471 .enable_mask = BIT(0),
2472 .hw.init = &(struct clk_init_data){
2473 .name = "fd_ahb_clk",
2474 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2475 .num_parents = 1,
2476 .ops = &clk_branch2_ops,
2477 .flags = CLK_SET_RATE_PARENT,
2478 },
2479 },
2480 };
2481
2482 static struct clk_branch mnoc_ahb_clk = {
2483 .halt_reg = 0x5024,
2484 .clkr = {
2485 .enable_reg = 0x5024,
2486 .enable_mask = BIT(0),
2487 .hw.init = &(struct clk_init_data){
2488 .name = "mnoc_ahb_clk",
2489 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2490 .num_parents = 1,
2491 .ops = &clk_branch2_ops,
2492 .flags = CLK_SET_RATE_PARENT,
2493 },
2494 },
2495 };
2496
2497 static struct clk_branch bimc_smmu_ahb_clk = {
2498 .halt_reg = 0xe004,
2499 .clkr = {
2500 .enable_reg = 0xe004,
2501 .enable_mask = BIT(0),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "bimc_smmu_ahb_clk",
2504 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2505 .num_parents = 1,
2506 .ops = &clk_branch2_ops,
2507 .flags = CLK_SET_RATE_PARENT,
2508 },
2509 },
2510 };
2511
2512 static struct clk_branch bimc_smmu_axi_clk = {
2513 .halt_reg = 0xe008,
2514 .clkr = {
2515 .enable_reg = 0xe008,
2516 .enable_mask = BIT(0),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "bimc_smmu_axi_clk",
2519 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2520 .num_parents = 1,
2521 .ops = &clk_branch2_ops,
2522 },
2523 },
2524 };
2525
2526 static struct clk_branch mnoc_maxi_clk = {
2527 .halt_reg = 0xf004,
2528 .clkr = {
2529 .enable_reg = 0xf004,
2530 .enable_mask = BIT(0),
2531 .hw.init = &(struct clk_init_data){
2532 .name = "mnoc_maxi_clk",
2533 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2534 .num_parents = 1,
2535 .ops = &clk_branch2_ops,
2536 .flags = CLK_SET_RATE_PARENT,
2537 },
2538 },
2539 };
2540
2541 static struct clk_branch vmem_maxi_clk = {
2542 .halt_reg = 0xf064,
2543 .clkr = {
2544 .enable_reg = 0xf064,
2545 .enable_mask = BIT(0),
2546 .hw.init = &(struct clk_init_data){
2547 .name = "vmem_maxi_clk",
2548 .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2549 .num_parents = 1,
2550 .ops = &clk_branch2_ops,
2551 .flags = CLK_SET_RATE_PARENT,
2552 },
2553 },
2554 };
2555
2556 static struct clk_branch vmem_ahb_clk = {
2557 .halt_reg = 0xf068,
2558 .clkr = {
2559 .enable_reg = 0xf068,
2560 .enable_mask = BIT(0),
2561 .hw.init = &(struct clk_init_data){
2562 .name = "vmem_ahb_clk",
2563 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2564 .num_parents = 1,
2565 .ops = &clk_branch2_ops,
2566 .flags = CLK_SET_RATE_PARENT,
2567 },
2568 },
2569 };
2570
2571 static struct clk_hw *mmcc_msm8998_hws[] = {
2572 &gpll0_div.hw,
2573 };
2574
2575 static struct gdsc video_top_gdsc = {
2576 .gdscr = 0x1024,
2577 .pd = {
2578 .name = "video_top",
2579 },
2580 .pwrsts = PWRSTS_OFF_ON,
2581 };
2582
2583 static struct gdsc video_subcore0_gdsc = {
2584 .gdscr = 0x1040,
2585 .pd = {
2586 .name = "video_subcore0",
2587 },
2588 .parent = &video_top_gdsc.pd,
2589 .pwrsts = PWRSTS_OFF_ON,
2590 };
2591
2592 static struct gdsc video_subcore1_gdsc = {
2593 .gdscr = 0x1044,
2594 .pd = {
2595 .name = "video_subcore1",
2596 },
2597 .parent = &video_top_gdsc.pd,
2598 .pwrsts = PWRSTS_OFF_ON,
2599 };
2600
2601 static struct gdsc mdss_gdsc = {
2602 .gdscr = 0x2304,
2603 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2604 .cxc_count = 4,
2605 .pd = {
2606 .name = "mdss",
2607 },
2608 .pwrsts = PWRSTS_OFF_ON,
2609 };
2610
2611 static struct gdsc camss_top_gdsc = {
2612 .gdscr = 0x34a0,
2613 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2614 0x35a8, 0x3868 },
2615 .cxc_count = 7,
2616 .pd = {
2617 .name = "camss_top",
2618 },
2619 .pwrsts = PWRSTS_OFF_ON,
2620 };
2621
2622 static struct gdsc camss_vfe0_gdsc = {
2623 .gdscr = 0x3664,
2624 .pd = {
2625 .name = "camss_vfe0",
2626 },
2627 .parent = &camss_top_gdsc.pd,
2628 .pwrsts = PWRSTS_OFF_ON,
2629 };
2630
2631 static struct gdsc camss_vfe1_gdsc = {
2632 .gdscr = 0x3674,
2633 .pd = {
2634 .name = "camss_vfe1_gdsc",
2635 },
2636 .parent = &camss_top_gdsc.pd,
2637 .pwrsts = PWRSTS_OFF_ON,
2638 };
2639
2640 static struct gdsc camss_cpp_gdsc = {
2641 .gdscr = 0x36d4,
2642 .pd = {
2643 .name = "camss_cpp",
2644 },
2645 .parent = &camss_top_gdsc.pd,
2646 .pwrsts = PWRSTS_OFF_ON,
2647 };
2648
2649 static struct gdsc bimc_smmu_gdsc = {
2650 .gdscr = 0xe020,
2651 .gds_hw_ctrl = 0xe024,
2652 .pd = {
2653 .name = "bimc_smmu",
2654 },
2655 .pwrsts = PWRSTS_OFF_ON,
2656 .flags = HW_CTRL,
2657 };
2658
2659 static struct clk_regmap *mmcc_msm8998_clocks[] = {
2660 [MMPLL0] = &mmpll0.clkr,
2661 [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
2662 [MMPLL1] = &mmpll1.clkr,
2663 [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
2664 [MMPLL3] = &mmpll3.clkr,
2665 [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
2666 [MMPLL4] = &mmpll4.clkr,
2667 [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
2668 [MMPLL5] = &mmpll5.clkr,
2669 [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
2670 [MMPLL6] = &mmpll6.clkr,
2671 [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
2672 [MMPLL7] = &mmpll7.clkr,
2673 [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
2674 [MMPLL10] = &mmpll10.clkr,
2675 [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
2676 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2677 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2678 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2679 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2680 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2681 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2682 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2683 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2684 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2685 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2686 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2687 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2688 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2689 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2690 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2691 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2692 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2693 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2694 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2695 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2696 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2697 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2698 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2699 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2700 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2701 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2702 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2703 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2704 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2705 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2706 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2707 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2708 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2709 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2710 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2711 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2712 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2713 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2714 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2715 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2716 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2717 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2718 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2719 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
2720 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2721 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
2722 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2723 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2724 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2725 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2726 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2727 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2728 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2729 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2730 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2731 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2732 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2733 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2734 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2735 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2736 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2737 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2738 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2739 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2740 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2741 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2742 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2743 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2744 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2745 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2746 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2747 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2748 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2749 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2750 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2751 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2752 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2753 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2754 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2755 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2756 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2757 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2758 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2759 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2760 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2761 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2762 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2763 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2764 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2765 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2766 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2767 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2768 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2769 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2770 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2771 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2772 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2773 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2774 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2775 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2776 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2777 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2778 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2779 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2780 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2781 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2782 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2783 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2784 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2785 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2786 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2787 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2788 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2789 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2790 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2791 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2792 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2793 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2794 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2795 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2796 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2797 [FD_CORE_CLK] = &fd_core_clk.clkr,
2798 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2799 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2800 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2801 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2802 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2803 [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
2804 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
2805 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
2806 };
2807
2808 static struct gdsc *mmcc_msm8998_gdscs[] = {
2809 [VIDEO_TOP_GDSC] = &video_top_gdsc,
2810 [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
2811 [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
2812 [MDSS_GDSC] = &mdss_gdsc,
2813 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2814 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2815 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2816 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2817 [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
2818 };
2819
2820 static const struct qcom_reset_map mmcc_msm8998_resets[] = {
2821 [SPDM_BCR] = { 0x200 },
2822 [SPDM_RM_BCR] = { 0x300 },
2823 [MISC_BCR] = { 0x320 },
2824 [VIDEO_TOP_BCR] = { 0x1020 },
2825 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2826 [MDSS_BCR] = { 0x2300 },
2827 [THROTTLE_MDSS_BCR] = { 0x2460 },
2828 [CAMSS_PHY0_BCR] = { 0x3020 },
2829 [CAMSS_PHY1_BCR] = { 0x3050 },
2830 [CAMSS_PHY2_BCR] = { 0x3080 },
2831 [CAMSS_CSI0_BCR] = { 0x30b0 },
2832 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2833 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2834 [CAMSS_CSI1_BCR] = { 0x3120 },
2835 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2836 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2837 [CAMSS_CSI2_BCR] = { 0x3180 },
2838 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2839 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2840 [CAMSS_CSI3_BCR] = { 0x31e0 },
2841 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2842 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2843 [CAMSS_ISPIF_BCR] = { 0x3220 },
2844 [CAMSS_CCI_BCR] = { 0x3340 },
2845 [CAMSS_TOP_BCR] = { 0x3480 },
2846 [CAMSS_AHB_BCR] = { 0x3488 },
2847 [CAMSS_MICRO_BCR] = { 0x3490 },
2848 [CAMSS_JPEG_BCR] = { 0x35a0 },
2849 [CAMSS_VFE0_BCR] = { 0x3660 },
2850 [CAMSS_VFE1_BCR] = { 0x3670 },
2851 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2852 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2853 [CAMSS_CPP_BCR] = { 0x36d0 },
2854 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2855 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2856 [CAMSS_FD_BCR] = { 0x3b60 },
2857 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2858 [MNOCAHB_BCR] = { 0x5020 },
2859 [MNOCAXI_BCR] = { 0xd020 },
2860 [BMIC_SMMU_BCR] = { 0xe000 },
2861 [MNOC_MAXI_BCR] = { 0xf000 },
2862 [VMEM_BCR] = { 0xf060 },
2863 [BTO_BCR] = { 0x10004 },
2864 };
2865
2866 static const struct regmap_config mmcc_msm8998_regmap_config = {
2867 .reg_bits = 32,
2868 .reg_stride = 4,
2869 .val_bits = 32,
2870 .max_register = 0x10004,
2871 .fast_io = true,
2872 };
2873
2874 static const struct qcom_cc_desc mmcc_msm8998_desc = {
2875 .config = &mmcc_msm8998_regmap_config,
2876 .clks = mmcc_msm8998_clocks,
2877 .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
2878 .resets = mmcc_msm8998_resets,
2879 .num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
2880 .gdscs = mmcc_msm8998_gdscs,
2881 .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2882 .clk_hws = mmcc_msm8998_hws,
2883 .num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),
2884 };
2885
2886 static const struct of_device_id mmcc_msm8998_match_table[] = {
2887 { .compatible = "qcom,mmcc-msm8998" },
2888 { }
2889 };
2890 MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
2891
2892 static int mmcc_msm8998_probe(struct platform_device *pdev)
2893 {
2894 struct regmap *regmap;
2895
2896 regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
2897 if (IS_ERR(regmap))
2898 return PTR_ERR(regmap);
2899
2900 return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
2901 }
2902
2903 static struct platform_driver mmcc_msm8998_driver = {
2904 .probe = mmcc_msm8998_probe,
2905 .driver = {
2906 .name = "mmcc-msm8998",
2907 .of_match_table = mmcc_msm8998_match_table,
2908 },
2909 };
2910 module_platform_driver(mmcc_msm8998_driver);
2911
2912 MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
2913 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support