1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015 Maxime Ripard
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
11 #include <linux/of_address.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
15 #define SUN4I_A10_PLL3_GATE_BIT 31
16 #define SUN4I_A10_PLL3_DIV_WIDTH 7
17 #define SUN4I_A10_PLL3_DIV_SHIFT 0
19 static DEFINE_SPINLOCK(sun4i_a10_pll3_lock
);
21 static void __init
sun4i_a10_pll3_setup(struct device_node
*node
)
23 const char *clk_name
= node
->name
, *parent
;
24 struct clk_multiplier
*mult
;
25 struct clk_gate
*gate
;
31 of_property_read_string(node
, "clock-output-names", &clk_name
);
32 parent
= of_clk_get_parent_name(node
, 0);
34 reg
= of_io_request_and_map(node
, 0, of_node_full_name(node
));
36 pr_err("%s: Could not map the clock registers\n", clk_name
);
40 gate
= kzalloc(sizeof(*gate
), GFP_KERNEL
);
45 gate
->bit_idx
= SUN4I_A10_PLL3_GATE_BIT
;
46 gate
->lock
= &sun4i_a10_pll3_lock
;
48 mult
= kzalloc(sizeof(*mult
), GFP_KERNEL
);
53 mult
->shift
= SUN4I_A10_PLL3_DIV_SHIFT
;
54 mult
->width
= SUN4I_A10_PLL3_DIV_WIDTH
;
55 mult
->lock
= &sun4i_a10_pll3_lock
;
57 clk
= clk_register_composite(NULL
, clk_name
,
60 &mult
->hw
, &clk_multiplier_ops
,
61 &gate
->hw
, &clk_gate_ops
,
64 pr_err("%s: Couldn't register the clock\n", clk_name
);
68 ret
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
70 pr_err("%s: Couldn't register DT provider\n",
72 goto err_clk_unregister
;
78 clk_unregister_composite(clk
);
85 of_address_to_resource(node
, 0, &res
);
86 release_mem_region(res
.start
, resource_size(&res
));
89 CLK_OF_DECLARE(sun4i_a10_pll3
, "allwinner,sun4i-a10-pll3-clk",
90 sun4i_a10_pll3_setup
);