1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
7 * Aleksandr Frid <afrid@nvidia.com>
8 * Paul Walmsley <pwalmsley@nvidia.com>
10 * This library is for the DVCO and DFLL IP blocks on the Tegra124
11 * SoC. These IP blocks together are also known at NVIDIA as
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
13 * collectively as the "DFLL."
15 * The DFLL is a root clocksource which tolerates some amount of
16 * supply voltage noise. Tegra124 uses it to clock the fast CPU
17 * complex when the target CPU speed is above a particular rate. The
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
21 * target frequency, the DFLL minimizes supply voltage while
22 * delivering an average frequency equal to the target.
24 * Devices clocked by the DFLL must be able to tolerate frequency
25 * variation. In the case of the CPU, it's important to note that the
26 * CPU cycle time will vary. This has implications for
27 * performance-measurement code and any code that relies on the CPU
28 * cycle time to delay for a certain length of time.
31 #include <linux/clk.h>
32 #include <linux/clk-provider.h>
33 #include <linux/debugfs.h>
34 #include <linux/device.h>
35 #include <linux/err.h>
36 #include <linux/i2c.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/pm_opp.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/regmap.h>
45 #include <linux/regulator/consumer.h>
46 #include <linux/reset.h>
47 #include <linux/seq_file.h>
53 * DFLL control registers - access via dfll_{readl,writel}
56 /* DFLL_CTRL: DFLL control register */
57 #define DFLL_CTRL 0x00
58 #define DFLL_CTRL_MODE_MASK 0x03
60 /* DFLL_CONFIG: DFLL sample rate control */
61 #define DFLL_CONFIG 0x04
62 #define DFLL_CONFIG_DIV_MASK 0xff
63 #define DFLL_CONFIG_DIV_PRESCALE 32
65 /* DFLL_PARAMS: tuning coefficients for closed loop integrator */
66 #define DFLL_PARAMS 0x08
67 #define DFLL_PARAMS_CG_SCALE (0x1 << 24)
68 #define DFLL_PARAMS_FORCE_MODE_SHIFT 22
69 #define DFLL_PARAMS_FORCE_MODE_MASK (0x3 << DFLL_PARAMS_FORCE_MODE_SHIFT)
70 #define DFLL_PARAMS_CF_PARAM_SHIFT 16
71 #define DFLL_PARAMS_CF_PARAM_MASK (0x3f << DFLL_PARAMS_CF_PARAM_SHIFT)
72 #define DFLL_PARAMS_CI_PARAM_SHIFT 8
73 #define DFLL_PARAMS_CI_PARAM_MASK (0x7 << DFLL_PARAMS_CI_PARAM_SHIFT)
74 #define DFLL_PARAMS_CG_PARAM_SHIFT 0
75 #define DFLL_PARAMS_CG_PARAM_MASK (0xff << DFLL_PARAMS_CG_PARAM_SHIFT)
77 /* DFLL_TUNE0: delay line configuration register 0 */
78 #define DFLL_TUNE0 0x0c
80 /* DFLL_TUNE1: delay line configuration register 1 */
81 #define DFLL_TUNE1 0x10
83 /* DFLL_FREQ_REQ: target DFLL frequency control */
84 #define DFLL_FREQ_REQ 0x14
85 #define DFLL_FREQ_REQ_FORCE_ENABLE (0x1 << 28)
86 #define DFLL_FREQ_REQ_FORCE_SHIFT 16
87 #define DFLL_FREQ_REQ_FORCE_MASK (0xfff << DFLL_FREQ_REQ_FORCE_SHIFT)
88 #define FORCE_MAX 2047
89 #define FORCE_MIN -2048
90 #define DFLL_FREQ_REQ_SCALE_SHIFT 8
91 #define DFLL_FREQ_REQ_SCALE_MASK (0xff << DFLL_FREQ_REQ_SCALE_SHIFT)
92 #define DFLL_FREQ_REQ_SCALE_MAX 256
93 #define DFLL_FREQ_REQ_FREQ_VALID (0x1 << 7)
94 #define DFLL_FREQ_REQ_MULT_SHIFT 0
95 #define DFLL_FREQ_REG_MULT_MASK (0x7f << DFLL_FREQ_REQ_MULT_SHIFT)
98 /* DFLL_DROOP_CTRL: droop prevention control */
99 #define DFLL_DROOP_CTRL 0x1c
101 /* DFLL_OUTPUT_CFG: closed loop mode control registers */
102 /* NOTE: access via dfll_i2c_{readl,writel} */
103 #define DFLL_OUTPUT_CFG 0x20
104 #define DFLL_OUTPUT_CFG_I2C_ENABLE (0x1 << 30)
105 #define OUT_MASK 0x3f
106 #define DFLL_OUTPUT_CFG_SAFE_SHIFT 24
107 #define DFLL_OUTPUT_CFG_SAFE_MASK \
108 (OUT_MASK << DFLL_OUTPUT_CFG_SAFE_SHIFT)
109 #define DFLL_OUTPUT_CFG_MAX_SHIFT 16
110 #define DFLL_OUTPUT_CFG_MAX_MASK \
111 (OUT_MASK << DFLL_OUTPUT_CFG_MAX_SHIFT)
112 #define DFLL_OUTPUT_CFG_MIN_SHIFT 8
113 #define DFLL_OUTPUT_CFG_MIN_MASK \
114 (OUT_MASK << DFLL_OUTPUT_CFG_MIN_SHIFT)
115 #define DFLL_OUTPUT_CFG_PWM_DELTA (0x1 << 7)
116 #define DFLL_OUTPUT_CFG_PWM_ENABLE (0x1 << 6)
117 #define DFLL_OUTPUT_CFG_PWM_DIV_SHIFT 0
118 #define DFLL_OUTPUT_CFG_PWM_DIV_MASK \
119 (OUT_MASK << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
121 /* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */
122 #define DFLL_OUTPUT_FORCE 0x24
123 #define DFLL_OUTPUT_FORCE_ENABLE (0x1 << 6)
124 #define DFLL_OUTPUT_FORCE_VALUE_SHIFT 0
125 #define DFLL_OUTPUT_FORCE_VALUE_MASK \
126 (OUT_MASK << DFLL_OUTPUT_FORCE_VALUE_SHIFT)
128 /* DFLL_MONITOR_CTRL: internal monitor data source control */
129 #define DFLL_MONITOR_CTRL 0x28
130 #define DFLL_MONITOR_CTRL_FREQ 6
132 /* DFLL_MONITOR_DATA: internal monitor data output */
133 #define DFLL_MONITOR_DATA 0x2c
134 #define DFLL_MONITOR_DATA_NEW_MASK (0x1 << 16)
135 #define DFLL_MONITOR_DATA_VAL_SHIFT 0
136 #define DFLL_MONITOR_DATA_VAL_MASK (0xFFFF << DFLL_MONITOR_DATA_VAL_SHIFT)
139 * I2C output control registers - access via dfll_i2c_{readl,writel}
142 /* DFLL_I2C_CFG: I2C controller configuration register */
143 #define DFLL_I2C_CFG 0x40
144 #define DFLL_I2C_CFG_ARB_ENABLE (0x1 << 20)
145 #define DFLL_I2C_CFG_HS_CODE_SHIFT 16
146 #define DFLL_I2C_CFG_HS_CODE_MASK (0x7 << DFLL_I2C_CFG_HS_CODE_SHIFT)
147 #define DFLL_I2C_CFG_PACKET_ENABLE (0x1 << 15)
148 #define DFLL_I2C_CFG_SIZE_SHIFT 12
149 #define DFLL_I2C_CFG_SIZE_MASK (0x7 << DFLL_I2C_CFG_SIZE_SHIFT)
150 #define DFLL_I2C_CFG_SLAVE_ADDR_10 (0x1 << 10)
151 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT 1
152 #define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT 0
154 /* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */
155 #define DFLL_I2C_VDD_REG_ADDR 0x44
157 /* DFLL_I2C_STS: I2C controller status */
158 #define DFLL_I2C_STS 0x48
159 #define DFLL_I2C_STS_I2C_LAST_SHIFT 1
160 #define DFLL_I2C_STS_I2C_REQ_PENDING 0x1
162 /* DFLL_INTR_STS: DFLL interrupt status register */
163 #define DFLL_INTR_STS 0x5c
165 /* DFLL_INTR_EN: DFLL interrupt enable register */
166 #define DFLL_INTR_EN 0x60
167 #define DFLL_INTR_MIN_MASK 0x1
168 #define DFLL_INTR_MAX_MASK 0x2
171 * Integrated I2C controller registers - relative to td->i2c_controller_base
174 /* DFLL_I2C_CLK_DIVISOR: I2C controller clock divisor */
175 #define DFLL_I2C_CLK_DIVISOR 0x6c
176 #define DFLL_I2C_CLK_DIVISOR_MASK 0xffff
177 #define DFLL_I2C_CLK_DIVISOR_FS_SHIFT 16
178 #define DFLL_I2C_CLK_DIVISOR_HS_SHIFT 0
179 #define DFLL_I2C_CLK_DIVISOR_PREDIV 8
180 #define DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV 12
186 /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */
187 #define MAX_DFLL_VOLTAGES 33
190 * REF_CLK_CYC_PER_DVCO_SAMPLE: the number of ref_clk cycles that the hardware
191 * integrates the DVCO counter over - used for debug rate monitoring and
194 #define REF_CLK_CYC_PER_DVCO_SAMPLE 4
197 * REF_CLOCK_RATE: the DFLL reference clock rate currently supported by this
200 #define REF_CLOCK_RATE 51000000UL
202 #define DVCO_RATE_TO_MULT(rate, ref_rate) ((rate) / ((ref_rate) / 2))
203 #define MULT_TO_DVCO_RATE(mult, ref_rate) ((mult) * ((ref_rate) / 2))
206 * enum dfll_ctrl_mode - DFLL hardware operating mode
207 * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield)
208 * @DFLL_DISABLED: DFLL not generating an output clock
209 * @DFLL_OPEN_LOOP: DVCO running, but DFLL not adjusting voltage
210 * @DFLL_CLOSED_LOOP: DVCO running, and DFLL adjusting voltage to match
213 * The integer corresponding to the last two states, minus one, is
214 * written to the DFLL hardware to change operating modes.
216 enum dfll_ctrl_mode
{
217 DFLL_UNINITIALIZED
= 0,
220 DFLL_CLOSED_LOOP
= 3,
224 * enum dfll_tune_range - voltage range that the driver believes it's in
225 * @DFLL_TUNE_UNINITIALIZED: DFLL tuning not yet programmed
226 * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode)
228 * Some DFLL tuning parameters may need to change depending on the
229 * DVCO's voltage; these states represent the ranges that the driver
230 * supports. These are software states; these values are never
231 * written into registers.
233 enum dfll_tune_range
{
234 DFLL_TUNE_UNINITIALIZED
= 0,
239 enum tegra_dfll_pmu_if
{
240 TEGRA_DFLL_PMU_I2C
= 0,
241 TEGRA_DFLL_PMU_PWM
= 1,
245 * struct dfll_rate_req - target DFLL rate request data
246 * @rate: target frequency, after the postscaling
247 * @dvco_target_rate: target frequency, after the postscaling
248 * @lut_index: LUT index at which voltage the dvco_target_rate will be reached
249 * @mult_bits: value to program to the MULT bits of the DFLL_FREQ_REQ register
250 * @scale_bits: value to program to the SCALE bits of the DFLL_FREQ_REQ register
252 struct dfll_rate_req
{
254 unsigned long dvco_target_rate
;
262 struct tegra_dfll_soc_data
*soc
;
265 void __iomem
*i2c_base
;
266 void __iomem
*i2c_controller_base
;
267 void __iomem
*lut_base
;
269 struct regulator
*vdd_reg
;
273 struct clk
*dfll_clk
;
274 struct reset_control
*dvco_rst
;
275 unsigned long ref_rate
;
276 unsigned long i2c_clk_rate
;
277 unsigned long dvco_rate_min
;
279 enum dfll_ctrl_mode mode
;
280 enum dfll_tune_range tune_range
;
281 struct dentry
*debugfs_dir
;
282 struct clk_hw dfll_clk_hw
;
283 const char *output_clock_name
;
284 struct dfll_rate_req last_req
;
285 unsigned long last_unrounded_rate
;
287 /* Parameters from DT */
296 /* I2C interface parameters */
301 /* lut array entries are regulator framework selectors or PWM values*/
302 unsigned lut
[MAX_DFLL_VOLTAGES
];
303 unsigned long lut_uv
[MAX_DFLL_VOLTAGES
];
305 u8 lut_bottom
, lut_min
, lut_max
, lut_safe
;
308 enum tegra_dfll_pmu_if pmu_if
;
309 unsigned long pwm_rate
;
310 struct pinctrl
*pwm_pin
;
311 struct pinctrl_state
*pwm_enable_state
;
312 struct pinctrl_state
*pwm_disable_state
;
316 #define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)
318 /* mode_name: map numeric DFLL modes to names for friendly console messages */
319 static const char * const mode_name
[] = {
320 [DFLL_UNINITIALIZED
] = "uninitialized",
321 [DFLL_DISABLED
] = "disabled",
322 [DFLL_OPEN_LOOP
] = "open_loop",
323 [DFLL_CLOSED_LOOP
] = "closed_loop",
330 static inline u32
dfll_readl(struct tegra_dfll
*td
, u32 offs
)
332 return __raw_readl(td
->base
+ offs
);
335 static inline void dfll_writel(struct tegra_dfll
*td
, u32 val
, u32 offs
)
337 WARN_ON(offs
>= DFLL_I2C_CFG
);
338 __raw_writel(val
, td
->base
+ offs
);
341 static inline void dfll_wmb(struct tegra_dfll
*td
)
343 dfll_readl(td
, DFLL_CTRL
);
346 /* I2C output control registers - for addresses above DFLL_I2C_CFG */
348 static inline u32
dfll_i2c_readl(struct tegra_dfll
*td
, u32 offs
)
350 return __raw_readl(td
->i2c_base
+ offs
);
353 static inline void dfll_i2c_writel(struct tegra_dfll
*td
, u32 val
, u32 offs
)
355 __raw_writel(val
, td
->i2c_base
+ offs
);
358 static inline void dfll_i2c_wmb(struct tegra_dfll
*td
)
360 dfll_i2c_readl(td
, DFLL_I2C_CFG
);
364 * dfll_is_running - is the DFLL currently generating a clock?
367 * If the DFLL is currently generating an output clock signal, return
368 * true; otherwise return false.
370 static bool dfll_is_running(struct tegra_dfll
*td
)
372 return td
->mode
>= DFLL_OPEN_LOOP
;
376 * Runtime PM suspend/resume callbacks
380 * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL
381 * @dev: DFLL device *
383 * Enable all clocks needed by the DFLL. Assumes that clk_prepare()
384 * has already been called on all the clocks.
386 * XXX Should also handle context restore when returning from off.
388 int tegra_dfll_runtime_resume(struct device
*dev
)
390 struct tegra_dfll
*td
= dev_get_drvdata(dev
);
393 ret
= clk_enable(td
->ref_clk
);
395 dev_err(dev
, "could not enable ref clock: %d\n", ret
);
399 ret
= clk_enable(td
->soc_clk
);
401 dev_err(dev
, "could not enable register clock: %d\n", ret
);
402 clk_disable(td
->ref_clk
);
406 ret
= clk_enable(td
->i2c_clk
);
408 dev_err(dev
, "could not enable i2c clock: %d\n", ret
);
409 clk_disable(td
->soc_clk
);
410 clk_disable(td
->ref_clk
);
416 EXPORT_SYMBOL(tegra_dfll_runtime_resume
);
419 * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL
420 * @dev: DFLL device *
422 * Disable all clocks needed by the DFLL. Assumes that other code
423 * will later call clk_unprepare().
425 int tegra_dfll_runtime_suspend(struct device
*dev
)
427 struct tegra_dfll
*td
= dev_get_drvdata(dev
);
429 clk_disable(td
->ref_clk
);
430 clk_disable(td
->soc_clk
);
431 clk_disable(td
->i2c_clk
);
435 EXPORT_SYMBOL(tegra_dfll_runtime_suspend
);
438 * DFLL tuning operations (per-voltage-range tuning settings)
442 * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage
445 * Tune the DFLL oscillator parameters and the CPU clock shaper for
446 * the low-voltage range. These settings are valid for any voltage,
447 * but may not be optimal.
449 static void dfll_tune_low(struct tegra_dfll
*td
)
451 td
->tune_range
= DFLL_TUNE_LOW
;
453 dfll_writel(td
, td
->soc
->cvb
->cpu_dfll_data
.tune0_low
, DFLL_TUNE0
);
454 dfll_writel(td
, td
->soc
->cvb
->cpu_dfll_data
.tune1
, DFLL_TUNE1
);
457 if (td
->soc
->set_clock_trimmers_low
)
458 td
->soc
->set_clock_trimmers_low();
462 * Output clock scaler helpers
466 * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate
467 * @scale_bits: clock scaler value (bits in the DFLL_FREQ_REQ_SCALE field)
468 * @dvco_rate: the DVCO rate
470 * Apply the same scaling formula that the DFLL hardware uses to scale
473 static unsigned long dfll_scale_dvco_rate(int scale_bits
,
474 unsigned long dvco_rate
)
476 return (u64
)dvco_rate
* (scale_bits
+ 1) / DFLL_FREQ_REQ_SCALE_MAX
;
480 * DFLL mode switching
484 * dfll_set_mode - change the DFLL control mode
486 * @mode: DFLL control mode (see enum dfll_ctrl_mode)
488 * Change the DFLL's operating mode between disabled, open-loop mode,
489 * and closed-loop mode, or vice versa.
491 static void dfll_set_mode(struct tegra_dfll
*td
,
492 enum dfll_ctrl_mode mode
)
495 dfll_writel(td
, mode
- 1, DFLL_CTRL
);
503 static unsigned long get_dvco_rate_below(struct tegra_dfll
*td
, u8 out_min
)
505 struct dev_pm_opp
*opp
;
506 unsigned long rate
, prev_rate
;
507 unsigned long uv
, min_uv
;
509 min_uv
= td
->lut_uv
[out_min
];
510 for (rate
= 0, prev_rate
= 0; ; rate
++) {
511 opp
= dev_pm_opp_find_freq_ceil(td
->soc
->dev
, &rate
);
515 uv
= dev_pm_opp_get_voltage(opp
);
518 if (uv
&& uv
> min_uv
)
528 * DFLL-to-I2C controller interface
532 * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests
534 * @enable: whether to enable or disable the I2C voltage requests
536 * Set the master enable control for I2C control value updates. If disabled,
537 * then I2C control messages are inhibited, regardless of the DFLL mode.
539 static int dfll_i2c_set_output_enabled(struct tegra_dfll
*td
, bool enable
)
543 val
= dfll_i2c_readl(td
, DFLL_OUTPUT_CFG
);
546 val
|= DFLL_OUTPUT_CFG_I2C_ENABLE
;
548 val
&= ~DFLL_OUTPUT_CFG_I2C_ENABLE
;
550 dfll_i2c_writel(td
, val
, DFLL_OUTPUT_CFG
);
558 * DFLL-to-PWM controller interface
562 * dfll_pwm_set_output_enabled - enable/disable PWM voltage requests
564 * @enable: whether to enable or disable the PWM voltage requests
566 * Set the master enable control for PWM control value updates. If disabled,
567 * then the PWM signal is not driven. Also configure the PWM output pad
568 * to the appropriate state.
570 static int dfll_pwm_set_output_enabled(struct tegra_dfll
*td
, bool enable
)
576 ret
= pinctrl_select_state(td
->pwm_pin
, td
->pwm_enable_state
);
578 dev_err(td
->dev
, "setting enable state failed\n");
581 val
= dfll_readl(td
, DFLL_OUTPUT_CFG
);
582 val
&= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK
;
583 div
= DIV_ROUND_UP(td
->ref_rate
, td
->pwm_rate
);
584 val
|= (div
<< DFLL_OUTPUT_CFG_PWM_DIV_SHIFT
)
585 & DFLL_OUTPUT_CFG_PWM_DIV_MASK
;
586 dfll_writel(td
, val
, DFLL_OUTPUT_CFG
);
589 val
|= DFLL_OUTPUT_CFG_PWM_ENABLE
;
590 dfll_writel(td
, val
, DFLL_OUTPUT_CFG
);
593 ret
= pinctrl_select_state(td
->pwm_pin
, td
->pwm_disable_state
);
595 dev_warn(td
->dev
, "setting disable state failed\n");
597 val
= dfll_readl(td
, DFLL_OUTPUT_CFG
);
598 val
&= ~DFLL_OUTPUT_CFG_PWM_ENABLE
;
599 dfll_writel(td
, val
, DFLL_OUTPUT_CFG
);
607 * dfll_set_force_output_value - set fixed value for force output
609 * @out_val: value to force output
611 * Set the fixed value for force output, DFLL will output this value when
612 * force output is enabled.
614 static u32
dfll_set_force_output_value(struct tegra_dfll
*td
, u8 out_val
)
616 u32 val
= dfll_readl(td
, DFLL_OUTPUT_FORCE
);
618 val
= (val
& DFLL_OUTPUT_FORCE_ENABLE
) | (out_val
& OUT_MASK
);
619 dfll_writel(td
, val
, DFLL_OUTPUT_FORCE
);
622 return dfll_readl(td
, DFLL_OUTPUT_FORCE
);
626 * dfll_set_force_output_enabled - enable/disable force output
628 * @enable: whether to enable or disable the force output
630 * Set the enable control for fouce output with fixed value.
632 static void dfll_set_force_output_enabled(struct tegra_dfll
*td
, bool enable
)
634 u32 val
= dfll_readl(td
, DFLL_OUTPUT_FORCE
);
637 val
|= DFLL_OUTPUT_FORCE_ENABLE
;
639 val
&= ~DFLL_OUTPUT_FORCE_ENABLE
;
641 dfll_writel(td
, val
, DFLL_OUTPUT_FORCE
);
646 * dfll_force_output - force output a fixed value
648 * @out_sel: value to force output
650 * Set the fixed value for force output, DFLL will output this value.
652 static int dfll_force_output(struct tegra_dfll
*td
, unsigned int out_sel
)
656 if (out_sel
> OUT_MASK
)
659 val
= dfll_set_force_output_value(td
, out_sel
);
660 if ((td
->mode
< DFLL_CLOSED_LOOP
) &&
661 !(val
& DFLL_OUTPUT_FORCE_ENABLE
)) {
662 dfll_set_force_output_enabled(td
, true);
669 * dfll_load_lut - load the voltage lookup table
670 * @td: struct tegra_dfll *
672 * Load the voltage-to-PMIC register value lookup table into the DFLL
673 * IP block memory. Look-up tables can be loaded at any time.
675 static void dfll_load_i2c_lut(struct tegra_dfll
*td
)
680 for (i
= 0; i
< MAX_DFLL_VOLTAGES
; i
++) {
682 lut_index
= td
->lut_min
;
683 else if (i
> td
->lut_max
)
684 lut_index
= td
->lut_max
;
688 val
= regulator_list_hardware_vsel(td
->vdd_reg
,
690 __raw_writel(val
, td
->lut_base
+ i
* 4);
697 * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface
700 * During DFLL driver initialization, program the DFLL-I2C interface
701 * with the PMU slave address, vdd register offset, and transfer mode.
702 * This data is used by the DFLL to automatically construct I2C
703 * voltage-set commands, which are then passed to the DFLL's internal
706 static void dfll_init_i2c_if(struct tegra_dfll
*td
)
710 if (td
->i2c_slave_addr
> 0x7f) {
711 val
= td
->i2c_slave_addr
<< DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT
;
712 val
|= DFLL_I2C_CFG_SLAVE_ADDR_10
;
714 val
= td
->i2c_slave_addr
<< DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT
;
716 val
|= DFLL_I2C_CFG_SIZE_MASK
;
717 val
|= DFLL_I2C_CFG_ARB_ENABLE
;
718 dfll_i2c_writel(td
, val
, DFLL_I2C_CFG
);
720 dfll_i2c_writel(td
, td
->i2c_reg
, DFLL_I2C_VDD_REG_ADDR
);
722 val
= DIV_ROUND_UP(td
->i2c_clk_rate
, td
->i2c_fs_rate
* 8);
723 BUG_ON(!val
|| (val
> DFLL_I2C_CLK_DIVISOR_MASK
));
724 val
= (val
- 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT
;
726 /* default hs divisor just in case */
727 val
|= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT
;
728 __raw_writel(val
, td
->i2c_controller_base
+ DFLL_I2C_CLK_DIVISOR
);
733 * dfll_init_out_if - prepare DFLL-to-PMIC interface
736 * During DFLL driver initialization or resume from context loss,
737 * disable the I2C command output to the PMIC, set safe voltage and
738 * output limits, and disable and clear limit interrupts.
740 static void dfll_init_out_if(struct tegra_dfll
*td
)
744 td
->lut_min
= td
->lut_bottom
;
745 td
->lut_max
= td
->lut_size
- 1;
746 td
->lut_safe
= td
->lut_min
+ (td
->lut_min
< td
->lut_max
? 1 : 0);
748 /* clear DFLL_OUTPUT_CFG before setting new value */
749 dfll_writel(td
, 0, DFLL_OUTPUT_CFG
);
752 val
= (td
->lut_safe
<< DFLL_OUTPUT_CFG_SAFE_SHIFT
) |
753 (td
->lut_max
<< DFLL_OUTPUT_CFG_MAX_SHIFT
) |
754 (td
->lut_min
<< DFLL_OUTPUT_CFG_MIN_SHIFT
);
755 dfll_writel(td
, val
, DFLL_OUTPUT_CFG
);
758 dfll_writel(td
, 0, DFLL_OUTPUT_FORCE
);
759 dfll_i2c_writel(td
, 0, DFLL_INTR_EN
);
760 dfll_i2c_writel(td
, DFLL_INTR_MAX_MASK
| DFLL_INTR_MIN_MASK
,
763 if (td
->pmu_if
== TEGRA_DFLL_PMU_PWM
) {
764 u32 vinit
= td
->reg_init_uV
;
765 int vstep
= td
->soc
->alignment
.step_uv
;
766 unsigned long vmin
= td
->lut_uv
[0];
768 /* set initial voltage */
769 if ((vinit
>= vmin
) && vstep
) {
772 vsel
= DIV_ROUND_UP((vinit
- vmin
), vstep
);
773 dfll_force_output(td
, vsel
);
776 dfll_load_i2c_lut(td
);
777 dfll_init_i2c_if(td
);
782 * Set/get the DFLL's targeted output clock rate
786 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
790 * Determines the index of a I2C LUT entry for a voltage that approximately
791 * produces the given DFLL clock rate. This is used when forcing a value
792 * to the integrator during rate changes. Returns -ENOENT if a suitable
793 * LUT index is not found.
795 static int find_lut_index_for_rate(struct tegra_dfll
*td
, unsigned long rate
)
797 struct dev_pm_opp
*opp
;
800 opp
= dev_pm_opp_find_freq_ceil(td
->soc
->dev
, &rate
);
804 align_step
= dev_pm_opp_get_voltage(opp
) / td
->soc
->alignment
.step_uv
;
807 for (i
= td
->lut_bottom
; i
< td
->lut_size
; i
++) {
808 if ((td
->lut_uv
[i
] / td
->soc
->alignment
.step_uv
) >= align_step
)
816 * dfll_calculate_rate_request - calculate DFLL parameters for a given rate
818 * @req: DFLL-rate-request structure
819 * @rate: the desired DFLL rate
821 * Populate the DFLL-rate-request record @req fields with the scale_bits
822 * and mult_bits fields, based on the target input rate. Returns 0 upon
823 * success, or -EINVAL if the requested rate in req->rate is too high
824 * or low for the DFLL to generate.
826 static int dfll_calculate_rate_request(struct tegra_dfll
*td
,
827 struct dfll_rate_req
*req
,
833 * If requested rate is below the minimum DVCO rate, active the scaler.
834 * In the future the DVCO minimum voltage should be selected based on
835 * chip temperature and the actual minimum rate should be calibrated
838 req
->scale_bits
= DFLL_FREQ_REQ_SCALE_MAX
- 1;
839 if (rate
< td
->dvco_rate_min
) {
842 scale
= DIV_ROUND_CLOSEST(rate
/ 1000 * DFLL_FREQ_REQ_SCALE_MAX
,
843 td
->dvco_rate_min
/ 1000);
845 dev_err(td
->dev
, "%s: Rate %lu is too low\n",
849 req
->scale_bits
= scale
- 1;
850 rate
= td
->dvco_rate_min
;
853 /* Convert requested rate into frequency request and scale settings */
854 val
= DVCO_RATE_TO_MULT(rate
, td
->ref_rate
);
855 if (val
> FREQ_MAX
) {
856 dev_err(td
->dev
, "%s: Rate %lu is above dfll range\n",
860 req
->mult_bits
= val
;
861 req
->dvco_target_rate
= MULT_TO_DVCO_RATE(req
->mult_bits
, td
->ref_rate
);
862 req
->rate
= dfll_scale_dvco_rate(req
->scale_bits
,
863 req
->dvco_target_rate
);
864 req
->lut_index
= find_lut_index_for_rate(td
, req
->dvco_target_rate
);
865 if (req
->lut_index
< 0)
866 return req
->lut_index
;
872 * dfll_set_frequency_request - start the frequency change operation
874 * @req: rate request structure
876 * Tell the DFLL to try to change its output frequency to the
877 * frequency represented by @req. DFLL must be in closed-loop mode.
879 static void dfll_set_frequency_request(struct tegra_dfll
*td
,
880 struct dfll_rate_req
*req
)
884 int coef
= 128; /* FIXME: td->cg_scale? */;
886 force_val
= (req
->lut_index
- td
->lut_safe
) * coef
/ td
->cg
;
887 force_val
= clamp(force_val
, FORCE_MIN
, FORCE_MAX
);
889 val
|= req
->mult_bits
<< DFLL_FREQ_REQ_MULT_SHIFT
;
890 val
|= req
->scale_bits
<< DFLL_FREQ_REQ_SCALE_SHIFT
;
891 val
|= ((u32
)force_val
<< DFLL_FREQ_REQ_FORCE_SHIFT
) &
892 DFLL_FREQ_REQ_FORCE_MASK
;
893 val
|= DFLL_FREQ_REQ_FREQ_VALID
| DFLL_FREQ_REQ_FORCE_ENABLE
;
895 dfll_writel(td
, val
, DFLL_FREQ_REQ
);
900 * tegra_dfll_request_rate - set the next rate for the DFLL to tune to
902 * @rate: clock rate to target
904 * Convert the requested clock rate @rate into the DFLL control logic
905 * settings. In closed-loop mode, update new settings immediately to
906 * adjust DFLL output rate accordingly. Otherwise, just save them
907 * until the next switch to closed loop. Returns 0 upon success,
908 * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL
909 * if @rate is outside the DFLL's tunable range.
911 static int dfll_request_rate(struct tegra_dfll
*td
, unsigned long rate
)
914 struct dfll_rate_req req
;
916 if (td
->mode
== DFLL_UNINITIALIZED
) {
917 dev_err(td
->dev
, "%s: Cannot set DFLL rate in %s mode\n",
918 __func__
, mode_name
[td
->mode
]);
922 ret
= dfll_calculate_rate_request(td
, &req
, rate
);
926 td
->last_unrounded_rate
= rate
;
929 if (td
->mode
== DFLL_CLOSED_LOOP
)
930 dfll_set_frequency_request(td
, &td
->last_req
);
936 * DFLL enable/disable & open-loop <-> closed-loop transitions
940 * dfll_disable - switch from open-loop mode to disabled mode
943 * Switch from OPEN_LOOP state to DISABLED state. Returns 0 upon success
944 * or -EPERM if the DFLL is not currently in open-loop mode.
946 static int dfll_disable(struct tegra_dfll
*td
)
948 if (td
->mode
!= DFLL_OPEN_LOOP
) {
949 dev_err(td
->dev
, "cannot disable DFLL in %s mode\n",
950 mode_name
[td
->mode
]);
954 dfll_set_mode(td
, DFLL_DISABLED
);
955 pm_runtime_put_sync(td
->dev
);
961 * dfll_enable - switch a disabled DFLL to open-loop mode
964 * Switch from DISABLED state to OPEN_LOOP state. Returns 0 upon success
965 * or -EPERM if the DFLL is not currently disabled.
967 static int dfll_enable(struct tegra_dfll
*td
)
969 if (td
->mode
!= DFLL_DISABLED
) {
970 dev_err(td
->dev
, "cannot enable DFLL in %s mode\n",
971 mode_name
[td
->mode
]);
975 pm_runtime_get_sync(td
->dev
);
976 dfll_set_mode(td
, DFLL_OPEN_LOOP
);
982 * dfll_set_open_loop_config - prepare to switch to open-loop mode
985 * Prepare to switch the DFLL to open-loop mode. This switches the
986 * DFLL to the low-voltage tuning range, ensures that I2C output
987 * forcing is disabled, and disables the output clock rate scaler.
988 * The DFLL's low-voltage tuning range parameters must be
989 * characterized to keep the downstream device stable at any DVCO
990 * input voltage. No return value.
992 static void dfll_set_open_loop_config(struct tegra_dfll
*td
)
996 /* always tune low (safe) in open loop */
997 if (td
->tune_range
!= DFLL_TUNE_LOW
)
1000 val
= dfll_readl(td
, DFLL_FREQ_REQ
);
1001 val
|= DFLL_FREQ_REQ_SCALE_MASK
;
1002 val
&= ~DFLL_FREQ_REQ_FORCE_ENABLE
;
1003 dfll_writel(td
, val
, DFLL_FREQ_REQ
);
1008 * tegra_dfll_lock - switch from open-loop to closed-loop mode
1009 * @td: DFLL instance
1011 * Switch from OPEN_LOOP state to CLOSED_LOOP state. Returns 0 upon success,
1012 * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the
1013 * DFLL is not currently in open-loop mode.
1015 static int dfll_lock(struct tegra_dfll
*td
)
1017 struct dfll_rate_req
*req
= &td
->last_req
;
1020 case DFLL_CLOSED_LOOP
:
1023 case DFLL_OPEN_LOOP
:
1024 if (req
->rate
== 0) {
1025 dev_err(td
->dev
, "%s: Cannot lock DFLL at rate 0\n",
1030 if (td
->pmu_if
== TEGRA_DFLL_PMU_PWM
)
1031 dfll_pwm_set_output_enabled(td
, true);
1033 dfll_i2c_set_output_enabled(td
, true);
1035 dfll_set_mode(td
, DFLL_CLOSED_LOOP
);
1036 dfll_set_frequency_request(td
, req
);
1037 dfll_set_force_output_enabled(td
, false);
1041 BUG_ON(td
->mode
> DFLL_CLOSED_LOOP
);
1042 dev_err(td
->dev
, "%s: Cannot lock DFLL in %s mode\n",
1043 __func__
, mode_name
[td
->mode
]);
1049 * tegra_dfll_unlock - switch from closed-loop to open-loop mode
1050 * @td: DFLL instance
1052 * Switch from CLOSED_LOOP state to OPEN_LOOP state. Returns 0 upon success,
1053 * or -EPERM if the DFLL is not currently in open-loop mode.
1055 static int dfll_unlock(struct tegra_dfll
*td
)
1058 case DFLL_CLOSED_LOOP
:
1059 dfll_set_open_loop_config(td
);
1060 dfll_set_mode(td
, DFLL_OPEN_LOOP
);
1061 if (td
->pmu_if
== TEGRA_DFLL_PMU_PWM
)
1062 dfll_pwm_set_output_enabled(td
, false);
1064 dfll_i2c_set_output_enabled(td
, false);
1067 case DFLL_OPEN_LOOP
:
1071 BUG_ON(td
->mode
> DFLL_CLOSED_LOOP
);
1072 dev_err(td
->dev
, "%s: Cannot unlock DFLL in %s mode\n",
1073 __func__
, mode_name
[td
->mode
]);
1079 * Clock framework integration
1081 * When the DFLL is being controlled by the CCF, always enter closed loop
1082 * mode when the clk is enabled. This requires that a DFLL rate request
1083 * has been set beforehand, which implies that a clk_set_rate() call is
1084 * always required before a clk_enable().
1087 static int dfll_clk_is_enabled(struct clk_hw
*hw
)
1089 struct tegra_dfll
*td
= clk_hw_to_dfll(hw
);
1091 return dfll_is_running(td
);
1094 static int dfll_clk_enable(struct clk_hw
*hw
)
1096 struct tegra_dfll
*td
= clk_hw_to_dfll(hw
);
1099 ret
= dfll_enable(td
);
1103 ret
= dfll_lock(td
);
1110 static void dfll_clk_disable(struct clk_hw
*hw
)
1112 struct tegra_dfll
*td
= clk_hw_to_dfll(hw
);
1115 ret
= dfll_unlock(td
);
1120 static unsigned long dfll_clk_recalc_rate(struct clk_hw
*hw
,
1121 unsigned long parent_rate
)
1123 struct tegra_dfll
*td
= clk_hw_to_dfll(hw
);
1125 return td
->last_unrounded_rate
;
1128 /* Must use determine_rate since it allows for rates exceeding 2^31-1 */
1129 static int dfll_clk_determine_rate(struct clk_hw
*hw
,
1130 struct clk_rate_request
*clk_req
)
1132 struct tegra_dfll
*td
= clk_hw_to_dfll(hw
);
1133 struct dfll_rate_req req
;
1136 ret
= dfll_calculate_rate_request(td
, &req
, clk_req
->rate
);
1141 * Don't set the rounded rate, since it doesn't really matter as
1142 * the output rate will be voltage controlled anyway, and cpufreq
1143 * freaks out if any rounding happens.
1149 static int dfll_clk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
1150 unsigned long parent_rate
)
1152 struct tegra_dfll
*td
= clk_hw_to_dfll(hw
);
1154 return dfll_request_rate(td
, rate
);
1157 static const struct clk_ops dfll_clk_ops
= {
1158 .is_enabled
= dfll_clk_is_enabled
,
1159 .enable
= dfll_clk_enable
,
1160 .disable
= dfll_clk_disable
,
1161 .recalc_rate
= dfll_clk_recalc_rate
,
1162 .determine_rate
= dfll_clk_determine_rate
,
1163 .set_rate
= dfll_clk_set_rate
,
1166 static struct clk_init_data dfll_clk_init_data
= {
1167 .ops
= &dfll_clk_ops
,
1172 * dfll_register_clk - register the DFLL output clock with the clock framework
1173 * @td: DFLL instance
1175 * Register the DFLL's output clock with the Linux clock framework and register
1176 * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL
1177 * or -ENOMEM upon failure.
1179 static int dfll_register_clk(struct tegra_dfll
*td
)
1183 dfll_clk_init_data
.name
= td
->output_clock_name
;
1184 td
->dfll_clk_hw
.init
= &dfll_clk_init_data
;
1186 td
->dfll_clk
= clk_register(td
->dev
, &td
->dfll_clk_hw
);
1187 if (IS_ERR(td
->dfll_clk
)) {
1188 dev_err(td
->dev
, "DFLL clock registration error\n");
1192 ret
= of_clk_add_provider(td
->dev
->of_node
, of_clk_src_simple_get
,
1195 dev_err(td
->dev
, "of_clk_add_provider() failed\n");
1197 clk_unregister(td
->dfll_clk
);
1205 * dfll_unregister_clk - unregister the DFLL output clock
1206 * @td: DFLL instance
1208 * Unregister the DFLL's output clock from the Linux clock framework
1209 * and from clkdev. No return value.
1211 static void dfll_unregister_clk(struct tegra_dfll
*td
)
1213 of_clk_del_provider(td
->dev
->of_node
);
1214 clk_unregister(td
->dfll_clk
);
1215 td
->dfll_clk
= NULL
;
1222 #ifdef CONFIG_DEBUG_FS
1228 * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
1229 * @monitor_data: value read from the DFLL_MONITOR_DATA_VAL bitfield
1230 * @ref_rate: DFLL reference clock rate
1232 * Convert @monitor_data from DFLL_MONITOR_DATA_VAL units into cycles
1233 * per second. Returns the converted value.
1235 static u64
dfll_calc_monitored_rate(u32 monitor_data
,
1236 unsigned long ref_rate
)
1238 return monitor_data
* (ref_rate
/ REF_CLK_CYC_PER_DVCO_SAMPLE
);
1242 * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
1243 * @td: DFLL instance
1245 * If the DFLL is enabled, return the last rate reported by the DFLL's
1246 * internal monitoring hardware. This works in both open-loop and
1247 * closed-loop mode, and takes the output scaler setting into account.
1248 * Assumes that the monitor was programmed to monitor frequency before
1249 * the sample period started. If the driver believes that the DFLL is
1250 * currently uninitialized or disabled, it will return 0, since
1251 * otherwise the DFLL monitor data register will return the last
1252 * measured rate from when the DFLL was active.
1254 static u64
dfll_read_monitor_rate(struct tegra_dfll
*td
)
1257 u64 pre_scaler_rate
, post_scaler_rate
;
1259 if (!dfll_is_running(td
))
1262 v
= dfll_readl(td
, DFLL_MONITOR_DATA
);
1263 v
= (v
& DFLL_MONITOR_DATA_VAL_MASK
) >> DFLL_MONITOR_DATA_VAL_SHIFT
;
1264 pre_scaler_rate
= dfll_calc_monitored_rate(v
, td
->ref_rate
);
1266 s
= dfll_readl(td
, DFLL_FREQ_REQ
);
1267 s
= (s
& DFLL_FREQ_REQ_SCALE_MASK
) >> DFLL_FREQ_REQ_SCALE_SHIFT
;
1268 post_scaler_rate
= dfll_scale_dvco_rate(s
, pre_scaler_rate
);
1270 return post_scaler_rate
;
1273 static int attr_enable_get(void *data
, u64
*val
)
1275 struct tegra_dfll
*td
= data
;
1277 *val
= dfll_is_running(td
);
1281 static int attr_enable_set(void *data
, u64 val
)
1283 struct tegra_dfll
*td
= data
;
1285 return val
? dfll_enable(td
) : dfll_disable(td
);
1287 DEFINE_DEBUGFS_ATTRIBUTE(enable_fops
, attr_enable_get
, attr_enable_set
,
1290 static int attr_lock_get(void *data
, u64
*val
)
1292 struct tegra_dfll
*td
= data
;
1294 *val
= (td
->mode
== DFLL_CLOSED_LOOP
);
1298 static int attr_lock_set(void *data
, u64 val
)
1300 struct tegra_dfll
*td
= data
;
1302 return val
? dfll_lock(td
) : dfll_unlock(td
);
1304 DEFINE_DEBUGFS_ATTRIBUTE(lock_fops
, attr_lock_get
, attr_lock_set
, "%llu\n");
1306 static int attr_rate_get(void *data
, u64
*val
)
1308 struct tegra_dfll
*td
= data
;
1310 *val
= dfll_read_monitor_rate(td
);
1315 static int attr_rate_set(void *data
, u64 val
)
1317 struct tegra_dfll
*td
= data
;
1319 return dfll_request_rate(td
, val
);
1321 DEFINE_DEBUGFS_ATTRIBUTE(rate_fops
, attr_rate_get
, attr_rate_set
, "%llu\n");
1323 static int attr_registers_show(struct seq_file
*s
, void *data
)
1326 struct tegra_dfll
*td
= s
->private;
1328 seq_puts(s
, "CONTROL REGISTERS:\n");
1329 for (offs
= 0; offs
<= DFLL_MONITOR_DATA
; offs
+= 4) {
1330 if (offs
== DFLL_OUTPUT_CFG
)
1331 val
= dfll_i2c_readl(td
, offs
);
1333 val
= dfll_readl(td
, offs
);
1334 seq_printf(s
, "[0x%02x] = 0x%08x\n", offs
, val
);
1337 seq_puts(s
, "\nI2C and INTR REGISTERS:\n");
1338 for (offs
= DFLL_I2C_CFG
; offs
<= DFLL_I2C_STS
; offs
+= 4)
1339 seq_printf(s
, "[0x%02x] = 0x%08x\n", offs
,
1340 dfll_i2c_readl(td
, offs
));
1341 for (offs
= DFLL_INTR_STS
; offs
<= DFLL_INTR_EN
; offs
+= 4)
1342 seq_printf(s
, "[0x%02x] = 0x%08x\n", offs
,
1343 dfll_i2c_readl(td
, offs
));
1345 if (td
->pmu_if
== TEGRA_DFLL_PMU_I2C
) {
1346 seq_puts(s
, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n");
1347 offs
= DFLL_I2C_CLK_DIVISOR
;
1348 seq_printf(s
, "[0x%02x] = 0x%08x\n", offs
,
1349 __raw_readl(td
->i2c_controller_base
+ offs
));
1351 seq_puts(s
, "\nLUT:\n");
1352 for (offs
= 0; offs
< 4 * MAX_DFLL_VOLTAGES
; offs
+= 4)
1353 seq_printf(s
, "[0x%02x] = 0x%08x\n", offs
,
1354 __raw_readl(td
->lut_base
+ offs
));
1360 DEFINE_SHOW_ATTRIBUTE(attr_registers
);
1362 static void dfll_debug_init(struct tegra_dfll
*td
)
1364 struct dentry
*root
;
1366 if (!td
|| (td
->mode
== DFLL_UNINITIALIZED
))
1369 root
= debugfs_create_dir("tegra_dfll_fcpu", NULL
);
1370 td
->debugfs_dir
= root
;
1372 debugfs_create_file_unsafe("enable", 0644, root
, td
,
1374 debugfs_create_file_unsafe("lock", 0444, root
, td
, &lock_fops
);
1375 debugfs_create_file_unsafe("rate", 0444, root
, td
, &rate_fops
);
1376 debugfs_create_file("registers", 0444, root
, td
, &attr_registers_fops
);
1380 static void inline dfll_debug_init(struct tegra_dfll
*td
) { }
1381 #endif /* CONFIG_DEBUG_FS */
1384 * DFLL initialization
1388 * dfll_set_default_params - program non-output related DFLL parameters
1389 * @td: DFLL instance
1391 * During DFLL driver initialization or resume from context loss,
1392 * program parameters for the closed loop integrator, DVCO tuning,
1393 * voltage droop control and monitor control.
1395 static void dfll_set_default_params(struct tegra_dfll
*td
)
1399 val
= DIV_ROUND_UP(td
->ref_rate
, td
->sample_rate
* 32);
1400 BUG_ON(val
> DFLL_CONFIG_DIV_MASK
);
1401 dfll_writel(td
, val
, DFLL_CONFIG
);
1403 val
= (td
->force_mode
<< DFLL_PARAMS_FORCE_MODE_SHIFT
) |
1404 (td
->cf
<< DFLL_PARAMS_CF_PARAM_SHIFT
) |
1405 (td
->ci
<< DFLL_PARAMS_CI_PARAM_SHIFT
) |
1406 (td
->cg
<< DFLL_PARAMS_CG_PARAM_SHIFT
) |
1407 (td
->cg_scale
? DFLL_PARAMS_CG_SCALE
: 0);
1408 dfll_writel(td
, val
, DFLL_PARAMS
);
1411 dfll_writel(td
, td
->droop_ctrl
, DFLL_DROOP_CTRL
);
1412 dfll_writel(td
, DFLL_MONITOR_CTRL_FREQ
, DFLL_MONITOR_CTRL
);
1416 * dfll_init_clks - clk_get() the DFLL source clocks
1417 * @td: DFLL instance
1419 * Call clk_get() on the DFLL source clocks and save the pointers for later
1420 * use. Returns 0 upon success or error (see devm_clk_get) if one or more
1421 * of the clocks couldn't be looked up.
1423 static int dfll_init_clks(struct tegra_dfll
*td
)
1425 td
->ref_clk
= devm_clk_get(td
->dev
, "ref");
1426 if (IS_ERR(td
->ref_clk
)) {
1427 dev_err(td
->dev
, "missing ref clock\n");
1428 return PTR_ERR(td
->ref_clk
);
1431 td
->soc_clk
= devm_clk_get(td
->dev
, "soc");
1432 if (IS_ERR(td
->soc_clk
)) {
1433 dev_err(td
->dev
, "missing soc clock\n");
1434 return PTR_ERR(td
->soc_clk
);
1437 td
->i2c_clk
= devm_clk_get(td
->dev
, "i2c");
1438 if (IS_ERR(td
->i2c_clk
)) {
1439 dev_err(td
->dev
, "missing i2c clock\n");
1440 return PTR_ERR(td
->i2c_clk
);
1442 td
->i2c_clk_rate
= clk_get_rate(td
->i2c_clk
);
1448 * dfll_init - Prepare the DFLL IP block for use
1449 * @td: DFLL instance
1451 * Do everything necessary to prepare the DFLL IP block for use. The
1452 * DFLL will be left in DISABLED state. Called by dfll_probe().
1453 * Returns 0 upon success, or passes along the error from whatever
1454 * function returned it.
1456 static int dfll_init(struct tegra_dfll
*td
)
1460 td
->ref_rate
= clk_get_rate(td
->ref_clk
);
1461 if (td
->ref_rate
!= REF_CLOCK_RATE
) {
1462 dev_err(td
->dev
, "unexpected ref clk rate %lu, expecting %lu",
1463 td
->ref_rate
, REF_CLOCK_RATE
);
1467 reset_control_deassert(td
->dvco_rst
);
1469 ret
= clk_prepare(td
->ref_clk
);
1471 dev_err(td
->dev
, "failed to prepare ref_clk\n");
1475 ret
= clk_prepare(td
->soc_clk
);
1477 dev_err(td
->dev
, "failed to prepare soc_clk\n");
1481 ret
= clk_prepare(td
->i2c_clk
);
1483 dev_err(td
->dev
, "failed to prepare i2c_clk\n");
1487 td
->last_unrounded_rate
= 0;
1489 pm_runtime_enable(td
->dev
);
1490 pm_runtime_get_sync(td
->dev
);
1492 dfll_set_mode(td
, DFLL_DISABLED
);
1493 dfll_set_default_params(td
);
1495 if (td
->soc
->init_clock_trimmers
)
1496 td
->soc
->init_clock_trimmers();
1498 dfll_set_open_loop_config(td
);
1500 dfll_init_out_if(td
);
1502 pm_runtime_put_sync(td
->dev
);
1507 clk_unprepare(td
->soc_clk
);
1509 clk_unprepare(td
->ref_clk
);
1511 reset_control_assert(td
->dvco_rst
);
1517 * tegra_dfll_suspend - check DFLL is disabled
1518 * @dev: DFLL instance
1520 * DFLL clock should be disabled by the CPUFreq driver. So, make
1521 * sure it is disabled and disable all clocks needed by the DFLL.
1523 int tegra_dfll_suspend(struct device
*dev
)
1525 struct tegra_dfll
*td
= dev_get_drvdata(dev
);
1527 if (dfll_is_running(td
)) {
1528 dev_err(td
->dev
, "DFLL still enabled while suspending\n");
1532 reset_control_assert(td
->dvco_rst
);
1536 EXPORT_SYMBOL(tegra_dfll_suspend
);
1539 * tegra_dfll_resume - reinitialize DFLL on resume
1540 * @dev: DFLL instance
1542 * DFLL is disabled and reset during suspend and resume.
1543 * So, reinitialize the DFLL IP block back for use.
1544 * DFLL clock is enabled later in closed loop mode by CPUFreq
1545 * driver before switching its clock source to DFLL output.
1547 int tegra_dfll_resume(struct device
*dev
)
1549 struct tegra_dfll
*td
= dev_get_drvdata(dev
);
1551 reset_control_deassert(td
->dvco_rst
);
1553 pm_runtime_get_sync(td
->dev
);
1555 dfll_set_mode(td
, DFLL_DISABLED
);
1556 dfll_set_default_params(td
);
1558 if (td
->soc
->init_clock_trimmers
)
1559 td
->soc
->init_clock_trimmers();
1561 dfll_set_open_loop_config(td
);
1563 dfll_init_out_if(td
);
1565 pm_runtime_put_sync(td
->dev
);
1569 EXPORT_SYMBOL(tegra_dfll_resume
);
1576 * Find a PMIC voltage register-to-voltage mapping for the given voltage.
1577 * An exact voltage match is required.
1579 static int find_vdd_map_entry_exact(struct tegra_dfll
*td
, int uV
)
1581 int i
, n_voltages
, reg_uV
,reg_volt_id
, align_step
;
1583 if (WARN_ON(td
->pmu_if
== TEGRA_DFLL_PMU_PWM
))
1586 align_step
= uV
/ td
->soc
->alignment
.step_uv
;
1587 n_voltages
= regulator_count_voltages(td
->vdd_reg
);
1588 for (i
= 0; i
< n_voltages
; i
++) {
1589 reg_uV
= regulator_list_voltage(td
->vdd_reg
, i
);
1593 reg_volt_id
= reg_uV
/ td
->soc
->alignment
.step_uv
;
1595 if (align_step
== reg_volt_id
)
1599 dev_err(td
->dev
, "no voltage map entry for %d uV\n", uV
);
1604 * Find a PMIC voltage register-to-voltage mapping for the given voltage,
1605 * rounding up to the closest supported voltage.
1607 static int find_vdd_map_entry_min(struct tegra_dfll
*td
, int uV
)
1609 int i
, n_voltages
, reg_uV
, reg_volt_id
, align_step
;
1611 if (WARN_ON(td
->pmu_if
== TEGRA_DFLL_PMU_PWM
))
1614 align_step
= uV
/ td
->soc
->alignment
.step_uv
;
1615 n_voltages
= regulator_count_voltages(td
->vdd_reg
);
1616 for (i
= 0; i
< n_voltages
; i
++) {
1617 reg_uV
= regulator_list_voltage(td
->vdd_reg
, i
);
1621 reg_volt_id
= reg_uV
/ td
->soc
->alignment
.step_uv
;
1623 if (align_step
<= reg_volt_id
)
1627 dev_err(td
->dev
, "no voltage map entry rounding to %d uV\n", uV
);
1632 * dfll_build_pwm_lut - build the PWM regulator lookup table
1633 * @td: DFLL instance
1634 * @v_max: Vmax from OPP table
1636 * Look-up table in h/w is ignored when PWM is used as DFLL interface to PMIC.
1637 * In this case closed loop output is controlling duty cycle directly. The s/w
1638 * look-up that maps PWM duty cycle to voltage is still built by this function.
1640 static int dfll_build_pwm_lut(struct tegra_dfll
*td
, unsigned long v_max
)
1643 unsigned long rate
, reg_volt
;
1644 u8 lut_bottom
= MAX_DFLL_VOLTAGES
;
1645 int v_min
= td
->soc
->cvb
->min_millivolts
* 1000;
1647 for (i
= 0; i
< MAX_DFLL_VOLTAGES
; i
++) {
1648 reg_volt
= td
->lut_uv
[i
];
1650 /* since opp voltage is exact mv */
1651 reg_volt
= (reg_volt
/ 1000) * 1000;
1652 if (reg_volt
> v_max
)
1656 if ((lut_bottom
== MAX_DFLL_VOLTAGES
) && (reg_volt
>= v_min
))
1660 /* determine voltage boundaries */
1662 if ((lut_bottom
== MAX_DFLL_VOLTAGES
) ||
1663 (lut_bottom
+ 1 >= td
->lut_size
)) {
1664 dev_err(td
->dev
, "no voltage above DFLL minimum %d mV\n",
1665 td
->soc
->cvb
->min_millivolts
);
1668 td
->lut_bottom
= lut_bottom
;
1670 /* determine rate boundaries */
1671 rate
= get_dvco_rate_below(td
, td
->lut_bottom
);
1673 dev_err(td
->dev
, "no opp below DFLL minimum voltage %d mV\n",
1674 td
->soc
->cvb
->min_millivolts
);
1677 td
->dvco_rate_min
= rate
;
1683 * dfll_build_i2c_lut - build the I2C voltage register lookup table
1684 * @td: DFLL instance
1685 * @v_max: Vmax from OPP table
1687 * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with
1688 * PMIC voltage register values that span the entire DFLL operating range.
1689 * This function builds the look-up table based on the OPP table provided by
1690 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC
1691 * register-to-voltage mapping queried from the regulator framework.
1693 * On success, fills in td->lut and returns 0, or -err on failure.
1695 static int dfll_build_i2c_lut(struct tegra_dfll
*td
, unsigned long v_max
)
1697 unsigned long rate
, v
, v_opp
;
1699 int j
, selector
, lut
;
1701 v
= td
->soc
->cvb
->min_millivolts
* 1000;
1702 lut
= find_vdd_map_entry_exact(td
, v
);
1708 for (j
= 1, rate
= 0; ; rate
++) {
1709 struct dev_pm_opp
*opp
;
1711 opp
= dev_pm_opp_find_freq_ceil(td
->soc
->dev
, &rate
);
1714 v_opp
= dev_pm_opp_get_voltage(opp
);
1716 if (v_opp
<= td
->soc
->cvb
->min_millivolts
* 1000)
1717 td
->dvco_rate_min
= dev_pm_opp_get_freq(opp
);
1719 dev_pm_opp_put(opp
);
1722 v
+= max(1UL, (v_max
- v
) / (MAX_DFLL_VOLTAGES
- j
));
1726 selector
= find_vdd_map_entry_min(td
, v
);
1729 if (selector
!= td
->lut
[j
- 1])
1730 td
->lut
[j
++] = selector
;
1733 v
= (j
== MAX_DFLL_VOLTAGES
- 1) ? v_max
: v_opp
;
1734 selector
= find_vdd_map_entry_exact(td
, v
);
1737 if (selector
!= td
->lut
[j
- 1])
1738 td
->lut
[j
++] = selector
;
1745 if (!td
->dvco_rate_min
)
1746 dev_err(td
->dev
, "no opp above DFLL minimum voltage %d mV\n",
1747 td
->soc
->cvb
->min_millivolts
);
1750 for (j
= 0; j
< td
->lut_size
; j
++)
1752 regulator_list_voltage(td
->vdd_reg
,
1760 static int dfll_build_lut(struct tegra_dfll
*td
)
1762 unsigned long rate
, v_max
;
1763 struct dev_pm_opp
*opp
;
1766 opp
= dev_pm_opp_find_freq_floor(td
->soc
->dev
, &rate
);
1768 dev_err(td
->dev
, "couldn't get vmax opp, empty opp table?\n");
1771 v_max
= dev_pm_opp_get_voltage(opp
);
1772 dev_pm_opp_put(opp
);
1774 if (td
->pmu_if
== TEGRA_DFLL_PMU_PWM
)
1775 return dfll_build_pwm_lut(td
, v_max
);
1777 return dfll_build_i2c_lut(td
, v_max
);
1781 * read_dt_param - helper function for reading required parameters from the DT
1782 * @td: DFLL instance
1783 * @param: DT property name
1784 * @dest: output pointer for the value read
1786 * Read a required numeric parameter from the DFLL device node, or complain
1787 * if the property doesn't exist. Returns a boolean indicating success for
1788 * easy chaining of multiple calls to this function.
1790 static bool read_dt_param(struct tegra_dfll
*td
, const char *param
, u32
*dest
)
1792 int err
= of_property_read_u32(td
->dev
->of_node
, param
, dest
);
1795 dev_err(td
->dev
, "failed to read DT parameter %s: %d\n",
1804 * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem
1805 * @td: DFLL instance
1807 * Read all the parameters required for operation in I2C mode. The parameters
1808 * can originate from the device tree or the regulator subsystem.
1809 * Returns 0 on success or -err on failure.
1811 static int dfll_fetch_i2c_params(struct tegra_dfll
*td
)
1813 struct regmap
*regmap
;
1814 struct device
*i2c_dev
;
1815 struct i2c_client
*i2c_client
;
1816 int vsel_reg
, vsel_mask
;
1819 if (!read_dt_param(td
, "nvidia,i2c-fs-rate", &td
->i2c_fs_rate
))
1822 regmap
= regulator_get_regmap(td
->vdd_reg
);
1823 i2c_dev
= regmap_get_device(regmap
);
1824 i2c_client
= to_i2c_client(i2c_dev
);
1826 td
->i2c_slave_addr
= i2c_client
->addr
;
1828 ret
= regulator_get_hardware_vsel_register(td
->vdd_reg
,
1833 "regulator unsuitable for DFLL I2C operation\n");
1836 td
->i2c_reg
= vsel_reg
;
1841 static int dfll_fetch_pwm_params(struct tegra_dfll
*td
)
1846 if (!td
->soc
->alignment
.step_uv
|| !td
->soc
->alignment
.offset_uv
) {
1848 "Missing step or alignment info for PWM regulator");
1851 for (i
= 0; i
< MAX_DFLL_VOLTAGES
; i
++)
1852 td
->lut_uv
[i
] = td
->soc
->alignment
.offset_uv
+
1853 i
* td
->soc
->alignment
.step_uv
;
1855 ret
= read_dt_param(td
, "nvidia,pwm-tristate-microvolts",
1858 dev_err(td
->dev
, "couldn't get initialized voltage\n");
1862 ret
= read_dt_param(td
, "nvidia,pwm-period-nanoseconds", &pwm_period
);
1864 dev_err(td
->dev
, "couldn't get PWM period\n");
1867 td
->pwm_rate
= (NSEC_PER_SEC
/ pwm_period
) * (MAX_DFLL_VOLTAGES
- 1);
1869 td
->pwm_pin
= devm_pinctrl_get(td
->dev
);
1870 if (IS_ERR(td
->pwm_pin
)) {
1871 dev_err(td
->dev
, "DT: missing pinctrl device\n");
1872 return PTR_ERR(td
->pwm_pin
);
1875 td
->pwm_enable_state
= pinctrl_lookup_state(td
->pwm_pin
,
1877 if (IS_ERR(td
->pwm_enable_state
)) {
1878 dev_err(td
->dev
, "DT: missing pwm enabled state\n");
1879 return PTR_ERR(td
->pwm_enable_state
);
1882 td
->pwm_disable_state
= pinctrl_lookup_state(td
->pwm_pin
,
1883 "dvfs_pwm_disable");
1884 if (IS_ERR(td
->pwm_disable_state
)) {
1885 dev_err(td
->dev
, "DT: missing pwm disabled state\n");
1886 return PTR_ERR(td
->pwm_disable_state
);
1893 * dfll_fetch_common_params - read DFLL parameters from the device tree
1894 * @td: DFLL instance
1896 * Read all the DT parameters that are common to both I2C and PWM operation.
1897 * Returns 0 on success or -EINVAL on any failure.
1899 static int dfll_fetch_common_params(struct tegra_dfll
*td
)
1903 ok
&= read_dt_param(td
, "nvidia,droop-ctrl", &td
->droop_ctrl
);
1904 ok
&= read_dt_param(td
, "nvidia,sample-rate", &td
->sample_rate
);
1905 ok
&= read_dt_param(td
, "nvidia,force-mode", &td
->force_mode
);
1906 ok
&= read_dt_param(td
, "nvidia,cf", &td
->cf
);
1907 ok
&= read_dt_param(td
, "nvidia,ci", &td
->ci
);
1908 ok
&= read_dt_param(td
, "nvidia,cg", &td
->cg
);
1909 td
->cg_scale
= of_property_read_bool(td
->dev
->of_node
,
1912 if (of_property_read_string(td
->dev
->of_node
, "clock-output-names",
1913 &td
->output_clock_name
)) {
1914 dev_err(td
->dev
, "missing clock-output-names property\n");
1918 return ok
? 0 : -EINVAL
;
1922 * API exported to per-SoC platform drivers
1926 * tegra_dfll_register - probe a Tegra DFLL device
1927 * @pdev: DFLL platform_device *
1928 * @soc: Per-SoC integration and characterization data for this DFLL instance
1930 * Probe and initialize a DFLL device instance. Intended to be called
1931 * by a SoC-specific shim driver that passes in per-SoC integration
1932 * and configuration data via @soc. Returns 0 on success or -err on failure.
1934 int tegra_dfll_register(struct platform_device
*pdev
,
1935 struct tegra_dfll_soc_data
*soc
)
1937 struct resource
*mem
;
1938 struct tegra_dfll
*td
;
1942 dev_err(&pdev
->dev
, "no tegra_dfll_soc_data provided\n");
1946 td
= devm_kzalloc(&pdev
->dev
, sizeof(*td
), GFP_KERNEL
);
1949 td
->dev
= &pdev
->dev
;
1950 platform_set_drvdata(pdev
, td
);
1954 td
->dvco_rst
= devm_reset_control_get(td
->dev
, "dvco");
1955 if (IS_ERR(td
->dvco_rst
)) {
1956 dev_err(td
->dev
, "couldn't get dvco reset\n");
1957 return PTR_ERR(td
->dvco_rst
);
1960 ret
= dfll_fetch_common_params(td
);
1962 dev_err(td
->dev
, "couldn't parse device tree parameters\n");
1966 if (of_property_read_bool(td
->dev
->of_node
, "nvidia,pwm-to-pmic")) {
1967 td
->pmu_if
= TEGRA_DFLL_PMU_PWM
;
1968 ret
= dfll_fetch_pwm_params(td
);
1970 td
->vdd_reg
= devm_regulator_get(td
->dev
, "vdd-cpu");
1971 if (IS_ERR(td
->vdd_reg
)) {
1972 dev_err(td
->dev
, "couldn't get vdd_cpu regulator\n");
1973 return PTR_ERR(td
->vdd_reg
);
1975 td
->pmu_if
= TEGRA_DFLL_PMU_I2C
;
1976 ret
= dfll_fetch_i2c_params(td
);
1981 ret
= dfll_build_lut(td
);
1983 dev_err(td
->dev
, "couldn't build LUT\n");
1987 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1989 dev_err(td
->dev
, "no control register resource\n");
1993 td
->base
= devm_ioremap(td
->dev
, mem
->start
, resource_size(mem
));
1995 dev_err(td
->dev
, "couldn't ioremap DFLL control registers\n");
1999 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2001 dev_err(td
->dev
, "no i2c_base resource\n");
2005 td
->i2c_base
= devm_ioremap(td
->dev
, mem
->start
, resource_size(mem
));
2006 if (!td
->i2c_base
) {
2007 dev_err(td
->dev
, "couldn't ioremap i2c_base resource\n");
2011 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
2013 dev_err(td
->dev
, "no i2c_controller_base resource\n");
2017 td
->i2c_controller_base
= devm_ioremap(td
->dev
, mem
->start
,
2018 resource_size(mem
));
2019 if (!td
->i2c_controller_base
) {
2021 "couldn't ioremap i2c_controller_base resource\n");
2025 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 3);
2027 dev_err(td
->dev
, "no lut_base resource\n");
2031 td
->lut_base
= devm_ioremap(td
->dev
, mem
->start
, resource_size(mem
));
2032 if (!td
->lut_base
) {
2034 "couldn't ioremap lut_base resource\n");
2038 ret
= dfll_init_clks(td
);
2040 dev_err(&pdev
->dev
, "DFLL clock init error\n");
2044 /* Enable the clocks and set the device up */
2045 ret
= dfll_init(td
);
2049 ret
= dfll_register_clk(td
);
2051 dev_err(&pdev
->dev
, "DFLL clk registration failed\n");
2055 dfll_debug_init(td
);
2059 EXPORT_SYMBOL(tegra_dfll_register
);
2062 * tegra_dfll_unregister - release all of the DFLL driver resources for a device
2063 * @pdev: DFLL platform_device *
2065 * Unbind this driver from the DFLL hardware device represented by
2066 * @pdev. The DFLL must be disabled for this to succeed. Returns a
2067 * soc pointer upon success or -EBUSY if the DFLL is still active.
2069 struct tegra_dfll_soc_data
*tegra_dfll_unregister(struct platform_device
*pdev
)
2071 struct tegra_dfll
*td
= platform_get_drvdata(pdev
);
2073 /* Try to prevent removal while the DFLL is active */
2074 if (td
->mode
!= DFLL_DISABLED
) {
2076 "must disable DFLL before removing driver\n");
2077 return ERR_PTR(-EBUSY
);
2080 debugfs_remove_recursive(td
->debugfs_dir
);
2082 dfll_unregister_clk(td
);
2083 pm_runtime_disable(&pdev
->dev
);
2085 clk_unprepare(td
->ref_clk
);
2086 clk_unprepare(td
->soc_clk
);
2087 clk_unprepare(td
->i2c_clk
);
2089 reset_control_assert(td
->dvco_rst
);
2093 EXPORT_SYMBOL(tegra_dfll_unregister
);