drivers/clk/tegra/clk-dfll.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
   4  * Copyright (C) 2013-2019 NVIDIA Corporation.  All rights reserved.
   5  *
   6  * Aleksandr Frid <afrid@nvidia.com>
   7  * Paul Walmsley <pwalmsley@nvidia.com>
   8  */
   9
  10 #ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
  11 #define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/reset.h>
  15 #include <linux/types.h>
  16
  17 #include "cvb.h"
  18
  19 /**
  20  * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
  21  * @dev: struct device * that holds the OPP table for the DFLL
  22  * @max_freq: maximum frequency supported on this SoC
  23  * @cvb: CPU frequency table for this SoC
  24  * @alignment: parameters of the regulator step and offset
  25  * @init_clock_trimmers: callback to initialize clock trimmers
  26  * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
  27  * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
  28  */
  29 struct tegra_dfll_soc_data {
  30         struct device *dev;
  31         unsigned long max_freq;
  32         const struct cvb_table *cvb;
  33         struct rail_alignment alignment;
  34
  35         void (*init_clock_trimmers)(void);
  36         void (*set_clock_trimmers_high)(void);
  37         void (*set_clock_trimmers_low)(void);
  38 };
  39
  40 int tegra_dfll_register(struct platform_device *pdev,
  41                         struct tegra_dfll_soc_data *soc);
  42 struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
  43 int tegra_dfll_runtime_suspend(struct device *dev);
  44 int tegra_dfll_runtime_resume(struct device *dev);
  45 int tegra_dfll_suspend(struct device *dev);
  46 int tegra_dfll_resume(struct device *dev);
  47
  48 #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */