drivers/clocksource/timer-ti-dm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * linux/arch/arm/plat-omap/dmtimer.c
   4  *
   5  * OMAP Dual-Mode Timers
   6  *
   7  * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
   8  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   9  * Thara Gopinath <thara@ti.com>
  10  *
  11  * dmtimer adaptation to platform_driver.
  12  *
  13  * Copyright (C) 2005 Nokia Corporation
  14  * OMAP2 support by Juha Yrjola
  15  * API improvements and OMAP2 clock framework support by Timo Teras
  16  *
  17  * Copyright (C) 2009 Texas Instruments
  18  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/cpu_pm.h>
  24 #include <linux/module.h>
  25 #include <linux/io.h>
  26 #include <linux/device.h>
  27 #include <linux/err.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/platform_data/dmtimer-omap.h>
  33
  34 #include <clocksource/timer-ti-dm.h>
  35
  36 static u32 omap_reserved_systimers;
  37 static LIST_HEAD(omap_timer_list);
  38 static DEFINE_SPINLOCK(dm_timer_lock);
  39
  40 enum {
  41         REQUEST_ANY = 0,
  42         REQUEST_BY_ID,
  43         REQUEST_BY_CAP,
  44         REQUEST_BY_NODE,
  45 };
  46
  47 /**
  48  * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
  49  * @timer:      timer pointer over which read operation to perform
  50  * @reg:        lowest byte holds the register offset
  51  *
  52  * The posted mode bit is encoded in reg. Note that in posted mode write
  53  * pending bit must be checked. Otherwise a read of a non completed write
  54  * will produce an error.
  55  */
  56 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
  57 {
  58         WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
  59         return __omap_dm_timer_read(timer, reg, timer->posted);
  60 }
  61
  62 /**
  63  * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
  64  * @timer:      timer pointer over which write operation is to perform
  65  * @reg:        lowest byte holds the register offset
  66  * @value:      data to write into the register
  67  *
  68  * The posted mode bit is encoded in reg. Note that in posted mode the write
  69  * pending bit must be checked. Otherwise a write on a register which has a
  70  * pending write will be lost.
  71  */
  72 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
  73                                                 u32 value)
  74 {
  75         WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
  76         __omap_dm_timer_write(timer, reg, value, timer->posted);
  77 }
  78
  79 static void omap_timer_restore_context(struct omap_dm_timer *timer)
  80 {
  81         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
  82                                 timer->context.twer);
  83         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
  84                                 timer->context.tcrr);
  85         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
  86                                 timer->context.tldr);
  87         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
  88                                 timer->context.tmar);
  89         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
  90                                 timer->context.tsicr);
  91         writel_relaxed(timer->context.tier, timer->irq_ena);
  92         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
  93                                 timer->context.tclr);
  94 }
  95
  96 static void omap_timer_save_context(struct omap_dm_timer *timer)
  97 {
  98         timer->context.tclr =
  99                         omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 100         timer->context.twer =
 101                         omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG);
 102         timer->context.tldr =
 103                         omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG);
 104         timer->context.tmar =
 105                         omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG);
 106         timer->context.tier = readl_relaxed(timer->irq_ena);
 107         timer->context.tsicr =
 108                         omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG);
 109 }
 110
 111 static int omap_timer_context_notifier(struct notifier_block *nb,
 112                                        unsigned long cmd, void *v)
 113 {
 114         struct omap_dm_timer *timer;
 115
 116         timer = container_of(nb, struct omap_dm_timer, nb);
 117
 118         switch (cmd) {
 119         case CPU_CLUSTER_PM_ENTER:
 120                 if ((timer->capability & OMAP_TIMER_ALWON) ||
 121                     !atomic_read(&timer->enabled))
 122                         break;
 123                 omap_timer_save_context(timer);
 124                 break;
 125         case CPU_CLUSTER_PM_ENTER_FAILED:
 126         case CPU_CLUSTER_PM_EXIT:
 127                 if ((timer->capability & OMAP_TIMER_ALWON) ||
 128                     !atomic_read(&timer->enabled))
 129                         break;
 130                 omap_timer_restore_context(timer);
 131                 break;
 132         }
 133
 134         return NOTIFY_OK;
 135 }
 136
 137 static int omap_dm_timer_reset(struct omap_dm_timer *timer)
 138 {
 139         u32 l, timeout = 100000;
 140
 141         if (timer->revision != 1)
 142                 return -EINVAL;
 143
 144         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 145
 146         do {
 147                 l = __omap_dm_timer_read(timer,
 148                                          OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
 149         } while (!l && timeout--);
 150
 151         if (!timeout) {
 152                 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
 153                 return -ETIMEDOUT;
 154         }
 155
 156         /* Configure timer for smart-idle mode */
 157         l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
 158         l |= 0x2 << 0x3;
 159         __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
 160
 161         timer->posted = 0;
 162
 163         return 0;
 164 }
 165
 166 static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 167 {
 168         int ret;
 169         const char *parent_name;
 170         struct clk *parent;
 171         struct dmtimer_platform_data *pdata;
 172
 173         if (unlikely(!timer) || IS_ERR(timer->fclk))
 174                 return -EINVAL;
 175
 176         switch (source) {
 177         case OMAP_TIMER_SRC_SYS_CLK:
 178                 parent_name = "timer_sys_ck";
 179                 break;
 180         case OMAP_TIMER_SRC_32_KHZ:
 181                 parent_name = "timer_32k_ck";
 182                 break;
 183         case OMAP_TIMER_SRC_EXT_CLK:
 184                 parent_name = "timer_ext_ck";
 185                 break;
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         pdata = timer->pdev->dev.platform_data;
 191
 192         /*
 193          * FIXME: Used for OMAP1 devices only because they do not currently
 194          * use the clock framework to set the parent clock. To be removed
 195          * once OMAP1 migrated to using clock framework for dmtimers
 196          */
 197         if (pdata && pdata->set_timer_src)
 198                 return pdata->set_timer_src(timer->pdev, source);
 199
 200 #if defined(CONFIG_COMMON_CLK)
 201         /* Check if the clock has configurable parents */
 202         if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
 203                 return 0;
 204 #endif
 205
 206         parent = clk_get(&timer->pdev->dev, parent_name);
 207         if (IS_ERR(parent)) {
 208                 pr_err("%s: %s not found\n", __func__, parent_name);
 209                 return -EINVAL;
 210         }
 211
 212         ret = clk_set_parent(timer->fclk, parent);
 213         if (ret < 0)
 214                 pr_err("%s: failed to set %s as parent\n", __func__,
 215                         parent_name);
 216
 217         clk_put(parent);
 218
 219         return ret;
 220 }
 221
 222 static void omap_dm_timer_enable(struct omap_dm_timer *timer)
 223 {
 224         pm_runtime_get_sync(&timer->pdev->dev);
 225 }
 226
 227 static void omap_dm_timer_disable(struct omap_dm_timer *timer)
 228 {
 229         pm_runtime_put_sync(&timer->pdev->dev);
 230 }
 231
 232 static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 233 {
 234         int rc;
 235
 236         /*
 237          * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
 238          * do not call clk_get() for these devices.
 239          */
 240         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
 241                 timer->fclk = clk_get(&timer->pdev->dev, "fck");
 242                 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
 243                         dev_err(&timer->pdev->dev, ": No fclk handle.\n");
 244                         return -EINVAL;
 245                 }
 246         }
 247
 248         omap_dm_timer_enable(timer);
 249
 250         if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
 251                 rc = omap_dm_timer_reset(timer);
 252                 if (rc) {
 253                         omap_dm_timer_disable(timer);
 254                         return rc;
 255                 }
 256         }
 257
 258         __omap_dm_timer_enable_posted(timer);
 259         omap_dm_timer_disable(timer);
 260
 261         return 0;
 262 }
 263
 264 static inline u32 omap_dm_timer_reserved_systimer(int id)
 265 {
 266         return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
 267 }
 268
 269 int omap_dm_timer_reserve_systimer(int id)
 270 {
 271         if (omap_dm_timer_reserved_systimer(id))
 272                 return -ENODEV;
 273
 274         omap_reserved_systimers |= (1 << (id - 1));
 275
 276         return 0;
 277 }
 278
 279 static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
 280 {
 281         struct omap_dm_timer *timer = NULL, *t;
 282         struct device_node *np = NULL;
 283         unsigned long flags;
 284         u32 cap = 0;
 285         int id = 0;
 286
 287         switch (req_type) {
 288         case REQUEST_BY_ID:
 289                 id = *(int *)data;
 290                 break;
 291         case REQUEST_BY_CAP:
 292                 cap = *(u32 *)data;
 293                 break;
 294         case REQUEST_BY_NODE:
 295                 np = (struct device_node *)data;
 296                 break;
 297         default:
 298                 /* REQUEST_ANY */
 299                 break;
 300         }
 301
 302         spin_lock_irqsave(&dm_timer_lock, flags);
 303         list_for_each_entry(t, &omap_timer_list, node) {
 304                 if (t->reserved)
 305                         continue;
 306
 307                 switch (req_type) {
 308                 case REQUEST_BY_ID:
 309                         if (id == t->pdev->id) {
 310                                 timer = t;
 311                                 timer->reserved = 1;
 312                                 goto found;
 313                         }
 314                         break;
 315                 case REQUEST_BY_CAP:
 316                         if (cap == (t->capability & cap)) {
 317                                 /*
 318                                  * If timer is not NULL, we have already found
 319                                  * one timer. But it was not an exact match
 320                                  * because it had more capabilities than what
 321                                  * was required. Therefore, unreserve the last
 322                                  * timer found and see if this one is a better
 323                                  * match.
 324                                  */
 325                                 if (timer)
 326                                         timer->reserved = 0;
 327                                 timer = t;
 328                                 timer->reserved = 1;
 329
 330                                 /* Exit loop early if we find an exact match */
 331                                 if (t->capability == cap)
 332                                         goto found;
 333                         }
 334                         break;
 335                 case REQUEST_BY_NODE:
 336                         if (np == t->pdev->dev.of_node) {
 337                                 timer = t;
 338                                 timer->reserved = 1;
 339                                 goto found;
 340                         }
 341                         break;
 342                 default:
 343                         /* REQUEST_ANY */
 344                         timer = t;
 345                         timer->reserved = 1;
 346                         goto found;
 347                 }
 348         }
 349 found:
 350         spin_unlock_irqrestore(&dm_timer_lock, flags);
 351
 352         if (timer && omap_dm_timer_prepare(timer)) {
 353                 timer->reserved = 0;
 354                 timer = NULL;
 355         }
 356
 357         if (!timer)
 358                 pr_debug("%s: timer request failed!\n", __func__);
 359
 360         return timer;
 361 }
 362
 363 static struct omap_dm_timer *omap_dm_timer_request(void)
 364 {
 365         return _omap_dm_timer_request(REQUEST_ANY, NULL);
 366 }
 367
 368 static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 369 {
 370         /* Requesting timer by ID is not supported when device tree is used */
 371         if (of_have_populated_dt()) {
 372                 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
 373                         __func__);
 374                 return NULL;
 375         }
 376
 377         return _omap_dm_timer_request(REQUEST_BY_ID, &id);
 378 }
 379
 380 /**
 381  * omap_dm_timer_request_by_cap - Request a timer by capability
 382  * @cap:        Bit mask of capabilities to match
 383  *
 384  * Find a timer based upon capabilities bit mask. Callers of this function
 385  * should use the definitions found in the plat/dmtimer.h file under the
 386  * comment "timer capabilities used in hwmod database". Returns pointer to
 387  * timer handle on success and a NULL pointer on failure.
 388  */
 389 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
 390 {
 391         return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
 392 }
 393
 394 /**
 395  * omap_dm_timer_request_by_node - Request a timer by device-tree node
 396  * @np:         Pointer to device-tree timer node
 397  *
 398  * Request a timer based upon a device node pointer. Returns pointer to
 399  * timer handle on success and a NULL pointer on failure.
 400  */
 401 static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
 402 {
 403         if (!np)
 404                 return NULL;
 405
 406         return _omap_dm_timer_request(REQUEST_BY_NODE, np);
 407 }
 408
 409 static int omap_dm_timer_free(struct omap_dm_timer *timer)
 410 {
 411         if (unlikely(!timer))
 412                 return -EINVAL;
 413
 414         clk_put(timer->fclk);
 415
 416         WARN_ON(!timer->reserved);
 417         timer->reserved = 0;
 418         return 0;
 419 }
 420
 421 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 422 {
 423         if (timer)
 424                 return timer->irq;
 425         return -EINVAL;
 426 }
 427
 428 #if defined(CONFIG_ARCH_OMAP1)
 429 #include <mach/hardware.h>
 430
 431 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 432 {
 433         return NULL;
 434 }
 435
 436 /**
 437  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 438  * @inputmask: current value of idlect mask
 439  */
 440 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 441 {
 442         int i = 0;
 443         struct omap_dm_timer *timer = NULL;
 444         unsigned long flags;
 445
 446         /* If ARMXOR cannot be idled this function call is unnecessary */
 447         if (!(inputmask & (1 << 1)))
 448                 return inputmask;
 449
 450         /* If any active timer is using ARMXOR return modified mask */
 451         spin_lock_irqsave(&dm_timer_lock, flags);
 452         list_for_each_entry(timer, &omap_timer_list, node) {
 453                 u32 l;
 454
 455                 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 456                 if (l & OMAP_TIMER_CTRL_ST) {
 457                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 458                                 inputmask &= ~(1 << 1);
 459                         else
 460                                 inputmask &= ~(1 << 2);
 461                 }
 462                 i++;
 463         }
 464         spin_unlock_irqrestore(&dm_timer_lock, flags);
 465
 466         return inputmask;
 467 }
 468
 469 #else
 470
 471 static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 472 {
 473         if (timer && !IS_ERR(timer->fclk))
 474                 return timer->fclk;
 475         return NULL;
 476 }
 477
 478 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 479 {
 480         BUG();
 481
 482         return 0;
 483 }
 484
 485 #endif
 486
 487 int omap_dm_timer_trigger(struct omap_dm_timer *timer)
 488 {
 489         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 490                 pr_err("%s: timer not available or enabled.\n", __func__);
 491                 return -EINVAL;
 492         }
 493
 494         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 495         return 0;
 496 }
 497
 498 static int omap_dm_timer_start(struct omap_dm_timer *timer)
 499 {
 500         u32 l;
 501
 502         if (unlikely(!timer))
 503                 return -EINVAL;
 504
 505         omap_dm_timer_enable(timer);
 506
 507         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 508         if (!(l & OMAP_TIMER_CTRL_ST)) {
 509                 l |= OMAP_TIMER_CTRL_ST;
 510                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 511         }
 512
 513         return 0;
 514 }
 515
 516 static int omap_dm_timer_stop(struct omap_dm_timer *timer)
 517 {
 518         unsigned long rate = 0;
 519
 520         if (unlikely(!timer))
 521                 return -EINVAL;
 522
 523         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
 524                 rate = clk_get_rate(timer->fclk);
 525
 526         __omap_dm_timer_stop(timer, timer->posted, rate);
 527
 528         omap_dm_timer_disable(timer);
 529         return 0;
 530 }
 531
 532 static int omap_dm_timer_set_load(struct omap_dm_timer *timer,
 533                                   unsigned int load)
 534 {
 535         if (unlikely(!timer))
 536                 return -EINVAL;
 537
 538         omap_dm_timer_enable(timer);
 539         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 540
 541         omap_dm_timer_disable(timer);
 542         return 0;
 543 }
 544
 545 static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 546                                    unsigned int match)
 547 {
 548         u32 l;
 549
 550         if (unlikely(!timer))
 551                 return -EINVAL;
 552
 553         omap_dm_timer_enable(timer);
 554         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 555         if (enable)
 556                 l |= OMAP_TIMER_CTRL_CE;
 557         else
 558                 l &= ~OMAP_TIMER_CTRL_CE;
 559         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 560         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 561
 562         omap_dm_timer_disable(timer);
 563         return 0;
 564 }
 565
 566 static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 567                                  int toggle, int trigger, int autoreload)
 568 {
 569         u32 l;
 570
 571         if (unlikely(!timer))
 572                 return -EINVAL;
 573
 574         omap_dm_timer_enable(timer);
 575         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 576         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 577                OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR);
 578         if (def_on)
 579                 l |= OMAP_TIMER_CTRL_SCPWM;
 580         if (toggle)
 581                 l |= OMAP_TIMER_CTRL_PT;
 582         l |= trigger << 10;
 583         if (autoreload)
 584                 l |= OMAP_TIMER_CTRL_AR;
 585         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 586
 587         omap_dm_timer_disable(timer);
 588         return 0;
 589 }
 590
 591 static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer)
 592 {
 593         u32 l;
 594
 595         if (unlikely(!timer))
 596                 return -EINVAL;
 597
 598         omap_dm_timer_enable(timer);
 599         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 600         omap_dm_timer_disable(timer);
 601
 602         return l;
 603 }
 604
 605 static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
 606                                         int prescaler)
 607 {
 608         u32 l;
 609
 610         if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
 611                 return -EINVAL;
 612
 613         omap_dm_timer_enable(timer);
 614         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 615         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 616         if (prescaler >= 0) {
 617                 l |= OMAP_TIMER_CTRL_PRE;
 618                 l |= prescaler << 2;
 619         }
 620         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 621
 622         omap_dm_timer_disable(timer);
 623         return 0;
 624 }
 625
 626 static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 627                                         unsigned int value)
 628 {
 629         if (unlikely(!timer))
 630                 return -EINVAL;
 631
 632         omap_dm_timer_enable(timer);
 633         __omap_dm_timer_int_enable(timer, value);
 634
 635         omap_dm_timer_disable(timer);
 636         return 0;
 637 }
 638
 639 /**
 640  * omap_dm_timer_set_int_disable - disable timer interrupts
 641  * @timer:      pointer to timer handle
 642  * @mask:       bit mask of interrupts to be disabled
 643  *
 644  * Disables the specified timer interrupts for a timer.
 645  */
 646 static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
 647 {
 648         u32 l = mask;
 649
 650         if (unlikely(!timer))
 651                 return -EINVAL;
 652
 653         omap_dm_timer_enable(timer);
 654
 655         if (timer->revision == 1)
 656                 l = readl_relaxed(timer->irq_ena) & ~mask;
 657
 658         writel_relaxed(l, timer->irq_dis);
 659         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
 660         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
 661
 662         omap_dm_timer_disable(timer);
 663         return 0;
 664 }
 665
 666 static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 667 {
 668         unsigned int l;
 669
 670         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 671                 pr_err("%s: timer not available or enabled.\n", __func__);
 672                 return 0;
 673         }
 674
 675         l = readl_relaxed(timer->irq_stat);
 676
 677         return l;
 678 }
 679
 680 static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 681 {
 682         if (unlikely(!timer || !atomic_read(&timer->enabled)))
 683                 return -EINVAL;
 684
 685         __omap_dm_timer_write_status(timer, value);
 686
 687         return 0;
 688 }
 689
 690 static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 691 {
 692         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 693                 pr_err("%s: timer not iavailable or enabled.\n", __func__);
 694                 return 0;
 695         }
 696
 697         return __omap_dm_timer_read_counter(timer, timer->posted);
 698 }
 699
 700 static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 701 {
 702         if (unlikely(!timer || !atomic_read(&timer->enabled))) {
 703                 pr_err("%s: timer not available or enabled.\n", __func__);
 704                 return -EINVAL;
 705         }
 706
 707         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 708
 709         /* Save the context */
 710         timer->context.tcrr = value;
 711         return 0;
 712 }
 713
 714 int omap_dm_timers_active(void)
 715 {
 716         struct omap_dm_timer *timer;
 717
 718         list_for_each_entry(timer, &omap_timer_list, node) {
 719                 if (!timer->reserved)
 720                         continue;
 721
 722                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 723                     OMAP_TIMER_CTRL_ST) {
 724                         return 1;
 725                 }
 726         }
 727         return 0;
 728 }
 729
 730 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev)
 731 {
 732         struct omap_dm_timer *timer = dev_get_drvdata(dev);
 733
 734         atomic_set(&timer->enabled, 0);
 735
 736         if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base)
 737                 return 0;
 738
 739         omap_timer_save_context(timer);
 740
 741         return 0;
 742 }
 743
 744 static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev)
 745 {
 746         struct omap_dm_timer *timer = dev_get_drvdata(dev);
 747
 748         if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base)
 749                 omap_timer_restore_context(timer);
 750
 751         atomic_set(&timer->enabled, 1);
 752
 753         return 0;
 754 }
 755
 756 static const struct dev_pm_ops omap_dm_timer_pm_ops = {
 757         SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend,
 758                            omap_dm_timer_runtime_resume, NULL)
 759 };
 760
 761 static const struct of_device_id omap_timer_match[];
 762
 763 /**
 764  * omap_dm_timer_probe - probe function called for every registered device
 765  * @pdev:       pointer to current timer platform device
 766  *
 767  * Called by driver framework at the end of device registration for all
 768  * timer devices.
 769  */
 770 static int omap_dm_timer_probe(struct platform_device *pdev)
 771 {
 772         unsigned long flags;
 773         struct omap_dm_timer *timer;
 774         struct device *dev = &pdev->dev;
 775         const struct dmtimer_platform_data *pdata;
 776         int ret;
 777
 778         pdata = of_device_get_match_data(dev);
 779         if (!pdata)
 780                 pdata = dev_get_platdata(dev);
 781         else
 782                 dev->platform_data = (void *)pdata;
 783
 784         if (!pdata) {
 785                 dev_err(dev, "%s: no platform data.\n", __func__);
 786                 return -ENODEV;
 787         }
 788
 789         timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
 790         if (!timer)
 791                 return  -ENOMEM;
 792
 793         timer->irq = platform_get_irq(pdev, 0);
 794         if (timer->irq < 0)
 795                 return timer->irq;
 796
 797         timer->fclk = ERR_PTR(-ENODEV);
 798         timer->io_base = devm_platform_ioremap_resource(pdev, 0);
 799         if (IS_ERR(timer->io_base))
 800                 return PTR_ERR(timer->io_base);
 801
 802         platform_set_drvdata(pdev, timer);
 803
 804         if (dev->of_node) {
 805                 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
 806                         timer->capability |= OMAP_TIMER_ALWON;
 807                 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
 808                         timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
 809                 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
 810                         timer->capability |= OMAP_TIMER_HAS_PWM;
 811                 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
 812                         timer->capability |= OMAP_TIMER_SECURE;
 813         } else {
 814                 timer->id = pdev->id;
 815                 timer->capability = pdata->timer_capability;
 816                 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
 817         }
 818
 819         if (!(timer->capability & OMAP_TIMER_ALWON)) {
 820                 timer->nb.notifier_call = omap_timer_context_notifier;
 821                 cpu_pm_register_notifier(&timer->nb);
 822         }
 823
 824         if (pdata)
 825                 timer->errata = pdata->timer_errata;
 826
 827         timer->pdev = pdev;
 828
 829         pm_runtime_enable(dev);
 830
 831         if (!timer->reserved) {
 832                 ret = pm_runtime_get_sync(dev);
 833                 if (ret < 0) {
 834                         dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
 835                                 __func__);
 836                         goto err_get_sync;
 837                 }
 838                 __omap_dm_timer_init_regs(timer);
 839                 pm_runtime_put(dev);
 840         }
 841
 842         /* add the timer element to the list */
 843         spin_lock_irqsave(&dm_timer_lock, flags);
 844         list_add_tail(&timer->node, &omap_timer_list);
 845         spin_unlock_irqrestore(&dm_timer_lock, flags);
 846
 847         dev_dbg(dev, "Device Probed.\n");
 848
 849         return 0;
 850
 851 err_get_sync:
 852         pm_runtime_put_noidle(dev);
 853         pm_runtime_disable(dev);
 854         return ret;
 855 }
 856
 857 /**
 858  * omap_dm_timer_remove - cleanup a registered timer device
 859  * @pdev:       pointer to current timer platform device
 860  *
 861  * Called by driver framework whenever a timer device is unregistered.
 862  * In addition to freeing platform resources it also deletes the timer
 863  * entry from the local list.
 864  */
 865 static int omap_dm_timer_remove(struct platform_device *pdev)
 866 {
 867         struct omap_dm_timer *timer;
 868         unsigned long flags;
 869         int ret = -EINVAL;
 870
 871         spin_lock_irqsave(&dm_timer_lock, flags);
 872         list_for_each_entry(timer, &omap_timer_list, node)
 873                 if (!strcmp(dev_name(&timer->pdev->dev),
 874                             dev_name(&pdev->dev))) {
 875                         if (!(timer->capability & OMAP_TIMER_ALWON))
 876                                 cpu_pm_unregister_notifier(&timer->nb);
 877                         list_del(&timer->node);
 878                         ret = 0;
 879                         break;
 880                 }
 881         spin_unlock_irqrestore(&dm_timer_lock, flags);
 882
 883         pm_runtime_disable(&pdev->dev);
 884
 885         return ret;
 886 }
 887
 888 static const struct omap_dm_timer_ops dmtimer_ops = {
 889         .request_by_node = omap_dm_timer_request_by_node,
 890         .request_specific = omap_dm_timer_request_specific,
 891         .request = omap_dm_timer_request,
 892         .set_source = omap_dm_timer_set_source,
 893         .get_irq = omap_dm_timer_get_irq,
 894         .set_int_enable = omap_dm_timer_set_int_enable,
 895         .set_int_disable = omap_dm_timer_set_int_disable,
 896         .free = omap_dm_timer_free,
 897         .enable = omap_dm_timer_enable,
 898         .disable = omap_dm_timer_disable,
 899         .get_fclk = omap_dm_timer_get_fclk,
 900         .start = omap_dm_timer_start,
 901         .stop = omap_dm_timer_stop,
 902         .set_load = omap_dm_timer_set_load,
 903         .set_match = omap_dm_timer_set_match,
 904         .set_pwm = omap_dm_timer_set_pwm,
 905         .get_pwm_status = omap_dm_timer_get_pwm_status,
 906         .set_prescaler = omap_dm_timer_set_prescaler,
 907         .read_counter = omap_dm_timer_read_counter,
 908         .write_counter = omap_dm_timer_write_counter,
 909         .read_status = omap_dm_timer_read_status,
 910         .write_status = omap_dm_timer_write_status,
 911 };
 912
 913 static const struct dmtimer_platform_data omap3plus_pdata = {
 914         .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
 915         .timer_ops = &dmtimer_ops,
 916 };
 917
 918 static const struct of_device_id omap_timer_match[] = {
 919         {
 920                 .compatible = "ti,omap2420-timer",
 921         },
 922         {
 923                 .compatible = "ti,omap3430-timer",
 924                 .data = &omap3plus_pdata,
 925         },
 926         {
 927                 .compatible = "ti,omap4430-timer",
 928                 .data = &omap3plus_pdata,
 929         },
 930         {
 931                 .compatible = "ti,omap5430-timer",
 932                 .data = &omap3plus_pdata,
 933         },
 934         {
 935                 .compatible = "ti,am335x-timer",
 936                 .data = &omap3plus_pdata,
 937         },
 938         {
 939                 .compatible = "ti,am335x-timer-1ms",
 940                 .data = &omap3plus_pdata,
 941         },
 942         {
 943                 .compatible = "ti,dm816-timer",
 944                 .data = &omap3plus_pdata,
 945         },
 946         {},
 947 };
 948 MODULE_DEVICE_TABLE(of, omap_timer_match);
 949
 950 static struct platform_driver omap_dm_timer_driver = {
 951         .probe  = omap_dm_timer_probe,
 952         .remove = omap_dm_timer_remove,
 953         .driver = {
 954                 .name   = "omap_timer",
 955                 .of_match_table = of_match_ptr(omap_timer_match),
 956                 .pm = &omap_dm_timer_pm_ops,
 957         },
 958 };
 959
 960 module_platform_driver(omap_dm_timer_driver);
 961
 962 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
 963 MODULE_LICENSE("GPL");
 964 MODULE_AUTHOR("Texas Instruments Inc");