1 // SPDX-License-Identifier: GPL-2.0
3 * Counter driver for the ACCES 104-QUAD-8
4 * Copyright (C) 2016 William Breathitt Gray
6 * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
8 #include <linux/bitops.h>
9 #include <linux/counter.h>
10 #include <linux/device.h>
11 #include <linux/errno.h>
12 #include <linux/iio/iio.h>
13 #include <linux/iio/types.h>
15 #include <linux/ioport.h>
16 #include <linux/isa.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/types.h>
22 #define QUAD8_EXTENT 32
24 static unsigned int base
[max_num_isa_dev(QUAD8_EXTENT
)];
25 static unsigned int num_quad8
;
26 module_param_array(base
, uint
, &num_quad8
, 0);
27 MODULE_PARM_DESC(base
, "ACCES 104-QUAD-8 base addresses");
29 #define QUAD8_NUM_COUNTERS 8
32 * struct quad8_iio - IIO device private data structure
33 * @counter: instance of the counter_device
34 * @fck_prescaler: array of filter clock prescaler configurations
35 * @preset: array of preset values
36 * @count_mode: array of count mode configurations
37 * @quadrature_mode: array of quadrature mode configurations
38 * @quadrature_scale: array of quadrature mode scale configurations
39 * @ab_enable: array of A and B inputs enable configurations
40 * @preset_enable: array of set_to_preset_on_index attribute configurations
41 * @synchronous_mode: array of index function synchronous mode configurations
42 * @index_polarity: array of index function polarity configurations
43 * @cable_fault_enable: differential encoder cable status enable configurations
44 * @base: base port address of the IIO device
48 struct counter_device counter
;
49 unsigned int fck_prescaler
[QUAD8_NUM_COUNTERS
];
50 unsigned int preset
[QUAD8_NUM_COUNTERS
];
51 unsigned int count_mode
[QUAD8_NUM_COUNTERS
];
52 unsigned int quadrature_mode
[QUAD8_NUM_COUNTERS
];
53 unsigned int quadrature_scale
[QUAD8_NUM_COUNTERS
];
54 unsigned int ab_enable
[QUAD8_NUM_COUNTERS
];
55 unsigned int preset_enable
[QUAD8_NUM_COUNTERS
];
56 unsigned int synchronous_mode
[QUAD8_NUM_COUNTERS
];
57 unsigned int index_polarity
[QUAD8_NUM_COUNTERS
];
58 unsigned int cable_fault_enable
;
62 #define QUAD8_REG_CHAN_OP 0x11
63 #define QUAD8_REG_INDEX_INPUT_LEVELS 0x16
64 #define QUAD8_DIFF_ENCODER_CABLE_STATUS 0x17
65 /* Borrow Toggle flip-flop */
66 #define QUAD8_FLAG_BT BIT(0)
67 /* Carry Toggle flip-flop */
68 #define QUAD8_FLAG_CT BIT(1)
70 #define QUAD8_FLAG_E BIT(4)
72 #define QUAD8_FLAG_UD BIT(5)
73 /* Reset and Load Signal Decoders */
74 #define QUAD8_CTR_RLD 0x00
75 /* Counter Mode Register */
76 #define QUAD8_CTR_CMR 0x20
77 /* Input / Output Control Register */
78 #define QUAD8_CTR_IOR 0x40
79 /* Index Control Register */
80 #define QUAD8_CTR_IDR 0x60
81 /* Reset Byte Pointer (three byte data pointer) */
82 #define QUAD8_RLD_RESET_BP 0x01
84 #define QUAD8_RLD_RESET_CNTR 0x02
85 /* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
86 #define QUAD8_RLD_RESET_FLAGS 0x04
87 /* Reset Error flag */
88 #define QUAD8_RLD_RESET_E 0x06
89 /* Preset Register to Counter */
90 #define QUAD8_RLD_PRESET_CNTR 0x08
91 /* Transfer Counter to Output Latch */
92 #define QUAD8_RLD_CNTR_OUT 0x10
93 /* Transfer Preset Register LSB to FCK Prescaler */
94 #define QUAD8_RLD_PRESET_PSC 0x18
95 #define QUAD8_CHAN_OP_ENABLE_COUNTERS 0x00
96 #define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
97 #define QUAD8_CMR_QUADRATURE_X1 0x08
98 #define QUAD8_CMR_QUADRATURE_X2 0x10
99 #define QUAD8_CMR_QUADRATURE_X4 0x18
102 static int quad8_read_raw(struct iio_dev
*indio_dev
,
103 struct iio_chan_spec
const *chan
, int *val
, int *val2
, long mask
)
105 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
106 const int base_offset
= priv
->base
+ 2 * chan
->channel
;
113 case IIO_CHAN_INFO_RAW
:
114 if (chan
->type
== IIO_INDEX
) {
115 *val
= !!(inb(priv
->base
+ QUAD8_REG_INDEX_INPUT_LEVELS
)
116 & BIT(chan
->channel
));
120 flags
= inb(base_offset
+ 1);
121 borrow
= flags
& QUAD8_FLAG_BT
;
122 carry
= !!(flags
& QUAD8_FLAG_CT
);
124 /* Borrow XOR Carry effectively doubles count range */
125 *val
= (borrow
^ carry
) << 24;
127 mutex_lock(&priv
->lock
);
129 /* Reset Byte Pointer; transfer Counter to Output Latch */
130 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
| QUAD8_RLD_CNTR_OUT
,
133 for (i
= 0; i
< 3; i
++)
134 *val
|= (unsigned int)inb(base_offset
) << (8 * i
);
136 mutex_unlock(&priv
->lock
);
139 case IIO_CHAN_INFO_ENABLE
:
140 *val
= priv
->ab_enable
[chan
->channel
];
142 case IIO_CHAN_INFO_SCALE
:
144 *val2
= priv
->quadrature_scale
[chan
->channel
];
145 return IIO_VAL_FRACTIONAL_LOG2
;
151 static int quad8_write_raw(struct iio_dev
*indio_dev
,
152 struct iio_chan_spec
const *chan
, int val
, int val2
, long mask
)
154 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
155 const int base_offset
= priv
->base
+ 2 * chan
->channel
;
157 unsigned int ior_cfg
;
160 case IIO_CHAN_INFO_RAW
:
161 if (chan
->type
== IIO_INDEX
)
164 /* Only 24-bit values are supported */
165 if ((unsigned int)val
> 0xFFFFFF)
168 mutex_lock(&priv
->lock
);
170 /* Reset Byte Pointer */
171 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
173 /* Counter can only be set via Preset Register */
174 for (i
= 0; i
< 3; i
++)
175 outb(val
>> (8 * i
), base_offset
);
177 /* Transfer Preset Register to Counter */
178 outb(QUAD8_CTR_RLD
| QUAD8_RLD_PRESET_CNTR
, base_offset
+ 1);
180 /* Reset Byte Pointer */
181 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
183 /* Set Preset Register back to original value */
184 val
= priv
->preset
[chan
->channel
];
185 for (i
= 0; i
< 3; i
++)
186 outb(val
>> (8 * i
), base_offset
);
188 /* Reset Borrow, Carry, Compare, and Sign flags */
189 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_FLAGS
, base_offset
+ 1);
190 /* Reset Error flag */
191 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_E
, base_offset
+ 1);
193 mutex_unlock(&priv
->lock
);
196 case IIO_CHAN_INFO_ENABLE
:
197 /* only boolean values accepted */
198 if (val
< 0 || val
> 1)
201 mutex_lock(&priv
->lock
);
203 priv
->ab_enable
[chan
->channel
] = val
;
205 ior_cfg
= val
| priv
->preset_enable
[chan
->channel
] << 1;
207 /* Load I/O control configuration */
208 outb(QUAD8_CTR_IOR
| ior_cfg
, base_offset
+ 1);
210 mutex_unlock(&priv
->lock
);
213 case IIO_CHAN_INFO_SCALE
:
214 mutex_lock(&priv
->lock
);
216 /* Quadrature scaling only available in quadrature mode */
217 if (!priv
->quadrature_mode
[chan
->channel
] &&
218 (val2
|| val
!= 1)) {
219 mutex_unlock(&priv
->lock
);
223 /* Only three gain states (1, 0.5, 0.25) */
224 if (val
== 1 && !val2
)
225 priv
->quadrature_scale
[chan
->channel
] = 0;
229 priv
->quadrature_scale
[chan
->channel
] = 1;
232 priv
->quadrature_scale
[chan
->channel
] = 2;
235 mutex_unlock(&priv
->lock
);
239 mutex_unlock(&priv
->lock
);
243 mutex_unlock(&priv
->lock
);
250 static const struct iio_info quad8_info
= {
251 .read_raw
= quad8_read_raw
,
252 .write_raw
= quad8_write_raw
255 static ssize_t
quad8_read_preset(struct iio_dev
*indio_dev
, uintptr_t private,
256 const struct iio_chan_spec
*chan
, char *buf
)
258 const struct quad8_iio
*const priv
= iio_priv(indio_dev
);
260 return snprintf(buf
, PAGE_SIZE
, "%u\n", priv
->preset
[chan
->channel
]);
263 static ssize_t
quad8_write_preset(struct iio_dev
*indio_dev
, uintptr_t private,
264 const struct iio_chan_spec
*chan
, const char *buf
, size_t len
)
266 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
267 const int base_offset
= priv
->base
+ 2 * chan
->channel
;
272 ret
= kstrtouint(buf
, 0, &preset
);
276 /* Only 24-bit values are supported */
277 if (preset
> 0xFFFFFF)
280 mutex_lock(&priv
->lock
);
282 priv
->preset
[chan
->channel
] = preset
;
284 /* Reset Byte Pointer */
285 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
287 /* Set Preset Register */
288 for (i
= 0; i
< 3; i
++)
289 outb(preset
>> (8 * i
), base_offset
);
291 mutex_unlock(&priv
->lock
);
296 static ssize_t
quad8_read_set_to_preset_on_index(struct iio_dev
*indio_dev
,
297 uintptr_t private, const struct iio_chan_spec
*chan
, char *buf
)
299 const struct quad8_iio
*const priv
= iio_priv(indio_dev
);
301 return snprintf(buf
, PAGE_SIZE
, "%u\n",
302 !priv
->preset_enable
[chan
->channel
]);
305 static ssize_t
quad8_write_set_to_preset_on_index(struct iio_dev
*indio_dev
,
306 uintptr_t private, const struct iio_chan_spec
*chan
, const char *buf
,
309 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
310 const int base_offset
= priv
->base
+ 2 * chan
->channel
+ 1;
313 unsigned int ior_cfg
;
315 ret
= kstrtobool(buf
, &preset_enable
);
319 /* Preset enable is active low in Input/Output Control register */
320 preset_enable
= !preset_enable
;
322 mutex_lock(&priv
->lock
);
324 priv
->preset_enable
[chan
->channel
] = preset_enable
;
326 ior_cfg
= priv
->ab_enable
[chan
->channel
] |
327 (unsigned int)preset_enable
<< 1;
329 /* Load I/O control configuration to Input / Output Control Register */
330 outb(QUAD8_CTR_IOR
| ior_cfg
, base_offset
);
332 mutex_unlock(&priv
->lock
);
337 static const char *const quad8_noise_error_states
[] = {
338 "No excessive noise is present at the count inputs",
339 "Excessive noise is present at the count inputs"
342 static int quad8_get_noise_error(struct iio_dev
*indio_dev
,
343 const struct iio_chan_spec
*chan
)
345 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
346 const int base_offset
= priv
->base
+ 2 * chan
->channel
+ 1;
348 return !!(inb(base_offset
) & QUAD8_FLAG_E
);
351 static const struct iio_enum quad8_noise_error_enum
= {
352 .items
= quad8_noise_error_states
,
353 .num_items
= ARRAY_SIZE(quad8_noise_error_states
),
354 .get
= quad8_get_noise_error
357 static const char *const quad8_count_direction_states
[] = {
362 static int quad8_get_count_direction(struct iio_dev
*indio_dev
,
363 const struct iio_chan_spec
*chan
)
365 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
366 const int base_offset
= priv
->base
+ 2 * chan
->channel
+ 1;
368 return !!(inb(base_offset
) & QUAD8_FLAG_UD
);
371 static const struct iio_enum quad8_count_direction_enum
= {
372 .items
= quad8_count_direction_states
,
373 .num_items
= ARRAY_SIZE(quad8_count_direction_states
),
374 .get
= quad8_get_count_direction
377 static const char *const quad8_count_modes
[] = {
384 static int quad8_set_count_mode(struct iio_dev
*indio_dev
,
385 const struct iio_chan_spec
*chan
, unsigned int cnt_mode
)
387 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
388 unsigned int mode_cfg
= cnt_mode
<< 1;
389 const int base_offset
= priv
->base
+ 2 * chan
->channel
+ 1;
391 mutex_lock(&priv
->lock
);
393 priv
->count_mode
[chan
->channel
] = cnt_mode
;
395 /* Add quadrature mode configuration */
396 if (priv
->quadrature_mode
[chan
->channel
])
397 mode_cfg
|= (priv
->quadrature_scale
[chan
->channel
] + 1) << 3;
399 /* Load mode configuration to Counter Mode Register */
400 outb(QUAD8_CTR_CMR
| mode_cfg
, base_offset
);
402 mutex_unlock(&priv
->lock
);
407 static int quad8_get_count_mode(struct iio_dev
*indio_dev
,
408 const struct iio_chan_spec
*chan
)
410 const struct quad8_iio
*const priv
= iio_priv(indio_dev
);
412 return priv
->count_mode
[chan
->channel
];
415 static const struct iio_enum quad8_count_mode_enum
= {
416 .items
= quad8_count_modes
,
417 .num_items
= ARRAY_SIZE(quad8_count_modes
),
418 .set
= quad8_set_count_mode
,
419 .get
= quad8_get_count_mode
422 static const char *const quad8_synchronous_modes
[] = {
427 static int quad8_set_synchronous_mode(struct iio_dev
*indio_dev
,
428 const struct iio_chan_spec
*chan
, unsigned int synchronous_mode
)
430 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
431 const int base_offset
= priv
->base
+ 2 * chan
->channel
+ 1;
432 unsigned int idr_cfg
= synchronous_mode
;
434 mutex_lock(&priv
->lock
);
436 idr_cfg
|= priv
->index_polarity
[chan
->channel
] << 1;
438 /* Index function must be non-synchronous in non-quadrature mode */
439 if (synchronous_mode
&& !priv
->quadrature_mode
[chan
->channel
]) {
440 mutex_unlock(&priv
->lock
);
444 priv
->synchronous_mode
[chan
->channel
] = synchronous_mode
;
446 /* Load Index Control configuration to Index Control Register */
447 outb(QUAD8_CTR_IDR
| idr_cfg
, base_offset
);
449 mutex_unlock(&priv
->lock
);
454 static int quad8_get_synchronous_mode(struct iio_dev
*indio_dev
,
455 const struct iio_chan_spec
*chan
)
457 const struct quad8_iio
*const priv
= iio_priv(indio_dev
);
459 return priv
->synchronous_mode
[chan
->channel
];
462 static const struct iio_enum quad8_synchronous_mode_enum
= {
463 .items
= quad8_synchronous_modes
,
464 .num_items
= ARRAY_SIZE(quad8_synchronous_modes
),
465 .set
= quad8_set_synchronous_mode
,
466 .get
= quad8_get_synchronous_mode
469 static const char *const quad8_quadrature_modes
[] = {
474 static int quad8_set_quadrature_mode(struct iio_dev
*indio_dev
,
475 const struct iio_chan_spec
*chan
, unsigned int quadrature_mode
)
477 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
478 const int base_offset
= priv
->base
+ 2 * chan
->channel
+ 1;
479 unsigned int mode_cfg
;
481 mutex_lock(&priv
->lock
);
483 mode_cfg
= priv
->count_mode
[chan
->channel
] << 1;
486 mode_cfg
|= (priv
->quadrature_scale
[chan
->channel
] + 1) << 3;
488 /* Quadrature scaling only available in quadrature mode */
489 priv
->quadrature_scale
[chan
->channel
] = 0;
491 /* Synchronous function not supported in non-quadrature mode */
492 if (priv
->synchronous_mode
[chan
->channel
])
493 quad8_set_synchronous_mode(indio_dev
, chan
, 0);
496 priv
->quadrature_mode
[chan
->channel
] = quadrature_mode
;
498 /* Load mode configuration to Counter Mode Register */
499 outb(QUAD8_CTR_CMR
| mode_cfg
, base_offset
);
501 mutex_unlock(&priv
->lock
);
506 static int quad8_get_quadrature_mode(struct iio_dev
*indio_dev
,
507 const struct iio_chan_spec
*chan
)
509 const struct quad8_iio
*const priv
= iio_priv(indio_dev
);
511 return priv
->quadrature_mode
[chan
->channel
];
514 static const struct iio_enum quad8_quadrature_mode_enum
= {
515 .items
= quad8_quadrature_modes
,
516 .num_items
= ARRAY_SIZE(quad8_quadrature_modes
),
517 .set
= quad8_set_quadrature_mode
,
518 .get
= quad8_get_quadrature_mode
521 static const char *const quad8_index_polarity_modes
[] = {
526 static int quad8_set_index_polarity(struct iio_dev
*indio_dev
,
527 const struct iio_chan_spec
*chan
, unsigned int index_polarity
)
529 struct quad8_iio
*const priv
= iio_priv(indio_dev
);
530 const int base_offset
= priv
->base
+ 2 * chan
->channel
+ 1;
531 unsigned int idr_cfg
= index_polarity
<< 1;
533 mutex_lock(&priv
->lock
);
535 idr_cfg
|= priv
->synchronous_mode
[chan
->channel
];
537 priv
->index_polarity
[chan
->channel
] = index_polarity
;
539 /* Load Index Control configuration to Index Control Register */
540 outb(QUAD8_CTR_IDR
| idr_cfg
, base_offset
);
542 mutex_unlock(&priv
->lock
);
547 static int quad8_get_index_polarity(struct iio_dev
*indio_dev
,
548 const struct iio_chan_spec
*chan
)
550 const struct quad8_iio
*const priv
= iio_priv(indio_dev
);
552 return priv
->index_polarity
[chan
->channel
];
555 static const struct iio_enum quad8_index_polarity_enum
= {
556 .items
= quad8_index_polarity_modes
,
557 .num_items
= ARRAY_SIZE(quad8_index_polarity_modes
),
558 .set
= quad8_set_index_polarity
,
559 .get
= quad8_get_index_polarity
562 static const struct iio_chan_spec_ext_info quad8_count_ext_info
[] = {
565 .shared
= IIO_SEPARATE
,
566 .read
= quad8_read_preset
,
567 .write
= quad8_write_preset
570 .name
= "set_to_preset_on_index",
571 .shared
= IIO_SEPARATE
,
572 .read
= quad8_read_set_to_preset_on_index
,
573 .write
= quad8_write_set_to_preset_on_index
575 IIO_ENUM("noise_error", IIO_SEPARATE
, &quad8_noise_error_enum
),
576 IIO_ENUM_AVAILABLE("noise_error", &quad8_noise_error_enum
),
577 IIO_ENUM("count_direction", IIO_SEPARATE
, &quad8_count_direction_enum
),
578 IIO_ENUM_AVAILABLE("count_direction", &quad8_count_direction_enum
),
579 IIO_ENUM("count_mode", IIO_SEPARATE
, &quad8_count_mode_enum
),
580 IIO_ENUM_AVAILABLE("count_mode", &quad8_count_mode_enum
),
581 IIO_ENUM("quadrature_mode", IIO_SEPARATE
, &quad8_quadrature_mode_enum
),
582 IIO_ENUM_AVAILABLE("quadrature_mode", &quad8_quadrature_mode_enum
),
586 static const struct iio_chan_spec_ext_info quad8_index_ext_info
[] = {
587 IIO_ENUM("synchronous_mode", IIO_SEPARATE
,
588 &quad8_synchronous_mode_enum
),
589 IIO_ENUM_AVAILABLE("synchronous_mode", &quad8_synchronous_mode_enum
),
590 IIO_ENUM("index_polarity", IIO_SEPARATE
, &quad8_index_polarity_enum
),
591 IIO_ENUM_AVAILABLE("index_polarity", &quad8_index_polarity_enum
),
595 #define QUAD8_COUNT_CHAN(_chan) { \
597 .channel = (_chan), \
598 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
599 BIT(IIO_CHAN_INFO_ENABLE) | BIT(IIO_CHAN_INFO_SCALE), \
600 .ext_info = quad8_count_ext_info, \
604 #define QUAD8_INDEX_CHAN(_chan) { \
606 .channel = (_chan), \
607 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
608 .ext_info = quad8_index_ext_info, \
612 static const struct iio_chan_spec quad8_channels
[] = {
613 QUAD8_COUNT_CHAN(0), QUAD8_INDEX_CHAN(0),
614 QUAD8_COUNT_CHAN(1), QUAD8_INDEX_CHAN(1),
615 QUAD8_COUNT_CHAN(2), QUAD8_INDEX_CHAN(2),
616 QUAD8_COUNT_CHAN(3), QUAD8_INDEX_CHAN(3),
617 QUAD8_COUNT_CHAN(4), QUAD8_INDEX_CHAN(4),
618 QUAD8_COUNT_CHAN(5), QUAD8_INDEX_CHAN(5),
619 QUAD8_COUNT_CHAN(6), QUAD8_INDEX_CHAN(6),
620 QUAD8_COUNT_CHAN(7), QUAD8_INDEX_CHAN(7)
623 static int quad8_signal_read(struct counter_device
*counter
,
624 struct counter_signal
*signal
, enum counter_signal_value
*val
)
626 const struct quad8_iio
*const priv
= counter
->priv
;
629 /* Only Index signal levels can be read */
633 state
= inb(priv
->base
+ QUAD8_REG_INDEX_INPUT_LEVELS
)
634 & BIT(signal
->id
- 16);
636 *val
= (state
) ? COUNTER_SIGNAL_HIGH
: COUNTER_SIGNAL_LOW
;
641 static int quad8_count_read(struct counter_device
*counter
,
642 struct counter_count
*count
, unsigned long *val
)
644 struct quad8_iio
*const priv
= counter
->priv
;
645 const int base_offset
= priv
->base
+ 2 * count
->id
;
651 flags
= inb(base_offset
+ 1);
652 borrow
= flags
& QUAD8_FLAG_BT
;
653 carry
= !!(flags
& QUAD8_FLAG_CT
);
655 /* Borrow XOR Carry effectively doubles count range */
656 *val
= (unsigned long)(borrow
^ carry
) << 24;
658 mutex_lock(&priv
->lock
);
660 /* Reset Byte Pointer; transfer Counter to Output Latch */
661 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
| QUAD8_RLD_CNTR_OUT
,
664 for (i
= 0; i
< 3; i
++)
665 *val
|= (unsigned long)inb(base_offset
) << (8 * i
);
667 mutex_unlock(&priv
->lock
);
672 static int quad8_count_write(struct counter_device
*counter
,
673 struct counter_count
*count
, unsigned long val
)
675 struct quad8_iio
*const priv
= counter
->priv
;
676 const int base_offset
= priv
->base
+ 2 * count
->id
;
679 /* Only 24-bit values are supported */
683 mutex_lock(&priv
->lock
);
685 /* Reset Byte Pointer */
686 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
688 /* Counter can only be set via Preset Register */
689 for (i
= 0; i
< 3; i
++)
690 outb(val
>> (8 * i
), base_offset
);
692 /* Transfer Preset Register to Counter */
693 outb(QUAD8_CTR_RLD
| QUAD8_RLD_PRESET_CNTR
, base_offset
+ 1);
695 /* Reset Byte Pointer */
696 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
698 /* Set Preset Register back to original value */
699 val
= priv
->preset
[count
->id
];
700 for (i
= 0; i
< 3; i
++)
701 outb(val
>> (8 * i
), base_offset
);
703 /* Reset Borrow, Carry, Compare, and Sign flags */
704 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_FLAGS
, base_offset
+ 1);
705 /* Reset Error flag */
706 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_E
, base_offset
+ 1);
708 mutex_unlock(&priv
->lock
);
713 enum quad8_count_function
{
714 QUAD8_COUNT_FUNCTION_PULSE_DIRECTION
= 0,
715 QUAD8_COUNT_FUNCTION_QUADRATURE_X1
,
716 QUAD8_COUNT_FUNCTION_QUADRATURE_X2
,
717 QUAD8_COUNT_FUNCTION_QUADRATURE_X4
720 static enum counter_count_function quad8_count_functions_list
[] = {
721 [QUAD8_COUNT_FUNCTION_PULSE_DIRECTION
] = COUNTER_COUNT_FUNCTION_PULSE_DIRECTION
,
722 [QUAD8_COUNT_FUNCTION_QUADRATURE_X1
] = COUNTER_COUNT_FUNCTION_QUADRATURE_X1_A
,
723 [QUAD8_COUNT_FUNCTION_QUADRATURE_X2
] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A
,
724 [QUAD8_COUNT_FUNCTION_QUADRATURE_X4
] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4
727 static int quad8_function_get(struct counter_device
*counter
,
728 struct counter_count
*count
, size_t *function
)
730 struct quad8_iio
*const priv
= counter
->priv
;
731 const int id
= count
->id
;
733 mutex_lock(&priv
->lock
);
735 if (priv
->quadrature_mode
[id
])
736 switch (priv
->quadrature_scale
[id
]) {
738 *function
= QUAD8_COUNT_FUNCTION_QUADRATURE_X1
;
741 *function
= QUAD8_COUNT_FUNCTION_QUADRATURE_X2
;
744 *function
= QUAD8_COUNT_FUNCTION_QUADRATURE_X4
;
748 *function
= QUAD8_COUNT_FUNCTION_PULSE_DIRECTION
;
750 mutex_unlock(&priv
->lock
);
755 static int quad8_function_set(struct counter_device
*counter
,
756 struct counter_count
*count
, size_t function
)
758 struct quad8_iio
*const priv
= counter
->priv
;
759 const int id
= count
->id
;
760 unsigned int *const quadrature_mode
= priv
->quadrature_mode
+ id
;
761 unsigned int *const scale
= priv
->quadrature_scale
+ id
;
762 unsigned int *const synchronous_mode
= priv
->synchronous_mode
+ id
;
763 const int base_offset
= priv
->base
+ 2 * id
+ 1;
764 unsigned int mode_cfg
;
765 unsigned int idr_cfg
;
767 mutex_lock(&priv
->lock
);
769 mode_cfg
= priv
->count_mode
[id
] << 1;
770 idr_cfg
= priv
->index_polarity
[id
] << 1;
772 if (function
== QUAD8_COUNT_FUNCTION_PULSE_DIRECTION
) {
773 *quadrature_mode
= 0;
775 /* Quadrature scaling only available in quadrature mode */
778 /* Synchronous function not supported in non-quadrature mode */
779 if (*synchronous_mode
) {
780 *synchronous_mode
= 0;
781 /* Disable synchronous function mode */
782 outb(QUAD8_CTR_IDR
| idr_cfg
, base_offset
);
785 *quadrature_mode
= 1;
788 case QUAD8_COUNT_FUNCTION_QUADRATURE_X1
:
790 mode_cfg
|= QUAD8_CMR_QUADRATURE_X1
;
792 case QUAD8_COUNT_FUNCTION_QUADRATURE_X2
:
794 mode_cfg
|= QUAD8_CMR_QUADRATURE_X2
;
796 case QUAD8_COUNT_FUNCTION_QUADRATURE_X4
:
798 mode_cfg
|= QUAD8_CMR_QUADRATURE_X4
;
803 /* Load mode configuration to Counter Mode Register */
804 outb(QUAD8_CTR_CMR
| mode_cfg
, base_offset
);
806 mutex_unlock(&priv
->lock
);
811 static void quad8_direction_get(struct counter_device
*counter
,
812 struct counter_count
*count
, enum counter_count_direction
*direction
)
814 const struct quad8_iio
*const priv
= counter
->priv
;
815 unsigned int ud_flag
;
816 const unsigned int flag_addr
= priv
->base
+ 2 * count
->id
+ 1;
818 /* U/D flag: nonzero = up, zero = down */
819 ud_flag
= inb(flag_addr
) & QUAD8_FLAG_UD
;
821 *direction
= (ud_flag
) ? COUNTER_COUNT_DIRECTION_FORWARD
:
822 COUNTER_COUNT_DIRECTION_BACKWARD
;
825 enum quad8_synapse_action
{
826 QUAD8_SYNAPSE_ACTION_NONE
= 0,
827 QUAD8_SYNAPSE_ACTION_RISING_EDGE
,
828 QUAD8_SYNAPSE_ACTION_FALLING_EDGE
,
829 QUAD8_SYNAPSE_ACTION_BOTH_EDGES
832 static enum counter_synapse_action quad8_index_actions_list
[] = {
833 [QUAD8_SYNAPSE_ACTION_NONE
] = COUNTER_SYNAPSE_ACTION_NONE
,
834 [QUAD8_SYNAPSE_ACTION_RISING_EDGE
] = COUNTER_SYNAPSE_ACTION_RISING_EDGE
837 static enum counter_synapse_action quad8_synapse_actions_list
[] = {
838 [QUAD8_SYNAPSE_ACTION_NONE
] = COUNTER_SYNAPSE_ACTION_NONE
,
839 [QUAD8_SYNAPSE_ACTION_RISING_EDGE
] = COUNTER_SYNAPSE_ACTION_RISING_EDGE
,
840 [QUAD8_SYNAPSE_ACTION_FALLING_EDGE
] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE
,
841 [QUAD8_SYNAPSE_ACTION_BOTH_EDGES
] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES
844 static int quad8_action_get(struct counter_device
*counter
,
845 struct counter_count
*count
, struct counter_synapse
*synapse
,
848 struct quad8_iio
*const priv
= counter
->priv
;
851 const size_t signal_a_id
= count
->synapses
[0].signal
->id
;
852 enum counter_count_direction direction
;
854 /* Handle Index signals */
855 if (synapse
->signal
->id
>= 16) {
856 if (priv
->preset_enable
[count
->id
])
857 *action
= QUAD8_SYNAPSE_ACTION_RISING_EDGE
;
859 *action
= QUAD8_SYNAPSE_ACTION_NONE
;
864 err
= quad8_function_get(counter
, count
, &function
);
868 /* Default action mode */
869 *action
= QUAD8_SYNAPSE_ACTION_NONE
;
871 /* Determine action mode based on current count function mode */
873 case QUAD8_COUNT_FUNCTION_PULSE_DIRECTION
:
874 if (synapse
->signal
->id
== signal_a_id
)
875 *action
= QUAD8_SYNAPSE_ACTION_RISING_EDGE
;
877 case QUAD8_COUNT_FUNCTION_QUADRATURE_X1
:
878 if (synapse
->signal
->id
== signal_a_id
) {
879 quad8_direction_get(counter
, count
, &direction
);
881 if (direction
== COUNTER_COUNT_DIRECTION_FORWARD
)
882 *action
= QUAD8_SYNAPSE_ACTION_RISING_EDGE
;
884 *action
= QUAD8_SYNAPSE_ACTION_FALLING_EDGE
;
887 case QUAD8_COUNT_FUNCTION_QUADRATURE_X2
:
888 if (synapse
->signal
->id
== signal_a_id
)
889 *action
= QUAD8_SYNAPSE_ACTION_BOTH_EDGES
;
891 case QUAD8_COUNT_FUNCTION_QUADRATURE_X4
:
892 *action
= QUAD8_SYNAPSE_ACTION_BOTH_EDGES
;
899 static const struct counter_ops quad8_ops
= {
900 .signal_read
= quad8_signal_read
,
901 .count_read
= quad8_count_read
,
902 .count_write
= quad8_count_write
,
903 .function_get
= quad8_function_get
,
904 .function_set
= quad8_function_set
,
905 .action_get
= quad8_action_get
908 static int quad8_index_polarity_get(struct counter_device
*counter
,
909 struct counter_signal
*signal
, size_t *index_polarity
)
911 const struct quad8_iio
*const priv
= counter
->priv
;
912 const size_t channel_id
= signal
->id
- 16;
914 *index_polarity
= priv
->index_polarity
[channel_id
];
919 static int quad8_index_polarity_set(struct counter_device
*counter
,
920 struct counter_signal
*signal
, size_t index_polarity
)
922 struct quad8_iio
*const priv
= counter
->priv
;
923 const size_t channel_id
= signal
->id
- 16;
924 const int base_offset
= priv
->base
+ 2 * channel_id
+ 1;
925 unsigned int idr_cfg
= index_polarity
<< 1;
927 mutex_lock(&priv
->lock
);
929 idr_cfg
|= priv
->synchronous_mode
[channel_id
];
931 priv
->index_polarity
[channel_id
] = index_polarity
;
933 /* Load Index Control configuration to Index Control Register */
934 outb(QUAD8_CTR_IDR
| idr_cfg
, base_offset
);
936 mutex_unlock(&priv
->lock
);
941 static struct counter_signal_enum_ext quad8_index_pol_enum
= {
942 .items
= quad8_index_polarity_modes
,
943 .num_items
= ARRAY_SIZE(quad8_index_polarity_modes
),
944 .get
= quad8_index_polarity_get
,
945 .set
= quad8_index_polarity_set
948 static int quad8_synchronous_mode_get(struct counter_device
*counter
,
949 struct counter_signal
*signal
, size_t *synchronous_mode
)
951 const struct quad8_iio
*const priv
= counter
->priv
;
952 const size_t channel_id
= signal
->id
- 16;
954 *synchronous_mode
= priv
->synchronous_mode
[channel_id
];
959 static int quad8_synchronous_mode_set(struct counter_device
*counter
,
960 struct counter_signal
*signal
, size_t synchronous_mode
)
962 struct quad8_iio
*const priv
= counter
->priv
;
963 const size_t channel_id
= signal
->id
- 16;
964 const int base_offset
= priv
->base
+ 2 * channel_id
+ 1;
965 unsigned int idr_cfg
= synchronous_mode
;
967 mutex_lock(&priv
->lock
);
969 idr_cfg
|= priv
->index_polarity
[channel_id
] << 1;
971 /* Index function must be non-synchronous in non-quadrature mode */
972 if (synchronous_mode
&& !priv
->quadrature_mode
[channel_id
]) {
973 mutex_unlock(&priv
->lock
);
977 priv
->synchronous_mode
[channel_id
] = synchronous_mode
;
979 /* Load Index Control configuration to Index Control Register */
980 outb(QUAD8_CTR_IDR
| idr_cfg
, base_offset
);
982 mutex_unlock(&priv
->lock
);
987 static struct counter_signal_enum_ext quad8_syn_mode_enum
= {
988 .items
= quad8_synchronous_modes
,
989 .num_items
= ARRAY_SIZE(quad8_synchronous_modes
),
990 .get
= quad8_synchronous_mode_get
,
991 .set
= quad8_synchronous_mode_set
994 static ssize_t
quad8_count_floor_read(struct counter_device
*counter
,
995 struct counter_count
*count
, void *private, char *buf
)
997 /* Only a floor of 0 is supported */
998 return sprintf(buf
, "0\n");
1001 static int quad8_count_mode_get(struct counter_device
*counter
,
1002 struct counter_count
*count
, size_t *cnt_mode
)
1004 const struct quad8_iio
*const priv
= counter
->priv
;
1006 /* Map 104-QUAD-8 count mode to Generic Counter count mode */
1007 switch (priv
->count_mode
[count
->id
]) {
1009 *cnt_mode
= COUNTER_COUNT_MODE_NORMAL
;
1012 *cnt_mode
= COUNTER_COUNT_MODE_RANGE_LIMIT
;
1015 *cnt_mode
= COUNTER_COUNT_MODE_NON_RECYCLE
;
1018 *cnt_mode
= COUNTER_COUNT_MODE_MODULO_N
;
1025 static int quad8_count_mode_set(struct counter_device
*counter
,
1026 struct counter_count
*count
, size_t cnt_mode
)
1028 struct quad8_iio
*const priv
= counter
->priv
;
1029 unsigned int mode_cfg
;
1030 const int base_offset
= priv
->base
+ 2 * count
->id
+ 1;
1032 /* Map Generic Counter count mode to 104-QUAD-8 count mode */
1034 case COUNTER_COUNT_MODE_NORMAL
:
1037 case COUNTER_COUNT_MODE_RANGE_LIMIT
:
1040 case COUNTER_COUNT_MODE_NON_RECYCLE
:
1043 case COUNTER_COUNT_MODE_MODULO_N
:
1048 mutex_lock(&priv
->lock
);
1050 priv
->count_mode
[count
->id
] = cnt_mode
;
1052 /* Set count mode configuration value */
1053 mode_cfg
= cnt_mode
<< 1;
1055 /* Add quadrature mode configuration */
1056 if (priv
->quadrature_mode
[count
->id
])
1057 mode_cfg
|= (priv
->quadrature_scale
[count
->id
] + 1) << 3;
1059 /* Load mode configuration to Counter Mode Register */
1060 outb(QUAD8_CTR_CMR
| mode_cfg
, base_offset
);
1062 mutex_unlock(&priv
->lock
);
1067 static struct counter_count_enum_ext quad8_cnt_mode_enum
= {
1068 .items
= counter_count_mode_str
,
1069 .num_items
= ARRAY_SIZE(counter_count_mode_str
),
1070 .get
= quad8_count_mode_get
,
1071 .set
= quad8_count_mode_set
1074 static ssize_t
quad8_count_direction_read(struct counter_device
*counter
,
1075 struct counter_count
*count
, void *priv
, char *buf
)
1077 enum counter_count_direction dir
;
1079 quad8_direction_get(counter
, count
, &dir
);
1081 return sprintf(buf
, "%s\n", counter_count_direction_str
[dir
]);
1084 static ssize_t
quad8_count_enable_read(struct counter_device
*counter
,
1085 struct counter_count
*count
, void *private, char *buf
)
1087 const struct quad8_iio
*const priv
= counter
->priv
;
1089 return sprintf(buf
, "%u\n", priv
->ab_enable
[count
->id
]);
1092 static ssize_t
quad8_count_enable_write(struct counter_device
*counter
,
1093 struct counter_count
*count
, void *private, const char *buf
, size_t len
)
1095 struct quad8_iio
*const priv
= counter
->priv
;
1096 const int base_offset
= priv
->base
+ 2 * count
->id
;
1099 unsigned int ior_cfg
;
1101 err
= kstrtobool(buf
, &ab_enable
);
1105 mutex_lock(&priv
->lock
);
1107 priv
->ab_enable
[count
->id
] = ab_enable
;
1109 ior_cfg
= ab_enable
| priv
->preset_enable
[count
->id
] << 1;
1111 /* Load I/O control configuration */
1112 outb(QUAD8_CTR_IOR
| ior_cfg
, base_offset
+ 1);
1114 mutex_unlock(&priv
->lock
);
1119 static int quad8_error_noise_get(struct counter_device
*counter
,
1120 struct counter_count
*count
, size_t *noise_error
)
1122 const struct quad8_iio
*const priv
= counter
->priv
;
1123 const int base_offset
= priv
->base
+ 2 * count
->id
+ 1;
1125 *noise_error
= !!(inb(base_offset
) & QUAD8_FLAG_E
);
1130 static struct counter_count_enum_ext quad8_error_noise_enum
= {
1131 .items
= quad8_noise_error_states
,
1132 .num_items
= ARRAY_SIZE(quad8_noise_error_states
),
1133 .get
= quad8_error_noise_get
1136 static ssize_t
quad8_count_preset_read(struct counter_device
*counter
,
1137 struct counter_count
*count
, void *private, char *buf
)
1139 const struct quad8_iio
*const priv
= counter
->priv
;
1141 return sprintf(buf
, "%u\n", priv
->preset
[count
->id
]);
1144 static void quad8_preset_register_set(struct quad8_iio
*quad8iio
, int id
,
1145 unsigned int preset
)
1147 const unsigned int base_offset
= quad8iio
->base
+ 2 * id
;
1150 quad8iio
->preset
[id
] = preset
;
1152 /* Reset Byte Pointer */
1153 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
1155 /* Set Preset Register */
1156 for (i
= 0; i
< 3; i
++)
1157 outb(preset
>> (8 * i
), base_offset
);
1160 static ssize_t
quad8_count_preset_write(struct counter_device
*counter
,
1161 struct counter_count
*count
, void *private, const char *buf
, size_t len
)
1163 struct quad8_iio
*const priv
= counter
->priv
;
1164 unsigned int preset
;
1167 ret
= kstrtouint(buf
, 0, &preset
);
1171 /* Only 24-bit values are supported */
1172 if (preset
> 0xFFFFFF)
1175 mutex_lock(&priv
->lock
);
1177 quad8_preset_register_set(priv
, count
->id
, preset
);
1179 mutex_unlock(&priv
->lock
);
1184 static ssize_t
quad8_count_ceiling_read(struct counter_device
*counter
,
1185 struct counter_count
*count
, void *private, char *buf
)
1187 struct quad8_iio
*const priv
= counter
->priv
;
1189 mutex_lock(&priv
->lock
);
1191 /* Range Limit and Modulo-N count modes use preset value as ceiling */
1192 switch (priv
->count_mode
[count
->id
]) {
1195 mutex_unlock(&priv
->lock
);
1196 return sprintf(buf
, "%u\n", priv
->preset
[count
->id
]);
1199 mutex_unlock(&priv
->lock
);
1201 /* By default 0x1FFFFFF (25 bits unsigned) is maximum count */
1202 return sprintf(buf
, "33554431\n");
1205 static ssize_t
quad8_count_ceiling_write(struct counter_device
*counter
,
1206 struct counter_count
*count
, void *private, const char *buf
, size_t len
)
1208 struct quad8_iio
*const priv
= counter
->priv
;
1209 unsigned int ceiling
;
1212 ret
= kstrtouint(buf
, 0, &ceiling
);
1216 /* Only 24-bit values are supported */
1217 if (ceiling
> 0xFFFFFF)
1220 mutex_lock(&priv
->lock
);
1222 /* Range Limit and Modulo-N count modes use preset value as ceiling */
1223 switch (priv
->count_mode
[count
->id
]) {
1226 quad8_preset_register_set(priv
, count
->id
, ceiling
);
1230 mutex_unlock(&priv
->lock
);
1235 static ssize_t
quad8_count_preset_enable_read(struct counter_device
*counter
,
1236 struct counter_count
*count
, void *private, char *buf
)
1238 const struct quad8_iio
*const priv
= counter
->priv
;
1240 return sprintf(buf
, "%u\n", !priv
->preset_enable
[count
->id
]);
1243 static ssize_t
quad8_count_preset_enable_write(struct counter_device
*counter
,
1244 struct counter_count
*count
, void *private, const char *buf
, size_t len
)
1246 struct quad8_iio
*const priv
= counter
->priv
;
1247 const int base_offset
= priv
->base
+ 2 * count
->id
+ 1;
1250 unsigned int ior_cfg
;
1252 ret
= kstrtobool(buf
, &preset_enable
);
1256 /* Preset enable is active low in Input/Output Control register */
1257 preset_enable
= !preset_enable
;
1259 mutex_lock(&priv
->lock
);
1261 priv
->preset_enable
[count
->id
] = preset_enable
;
1263 ior_cfg
= priv
->ab_enable
[count
->id
] | (unsigned int)preset_enable
<< 1;
1265 /* Load I/O control configuration to Input / Output Control Register */
1266 outb(QUAD8_CTR_IOR
| ior_cfg
, base_offset
);
1268 mutex_unlock(&priv
->lock
);
1273 static ssize_t
quad8_signal_cable_fault_read(struct counter_device
*counter
,
1274 struct counter_signal
*signal
,
1275 void *private, char *buf
)
1277 struct quad8_iio
*const priv
= counter
->priv
;
1278 const size_t channel_id
= signal
->id
/ 2;
1280 unsigned int status
;
1283 mutex_lock(&priv
->lock
);
1285 disabled
= !(priv
->cable_fault_enable
& BIT(channel_id
));
1288 mutex_unlock(&priv
->lock
);
1292 /* Logic 0 = cable fault */
1293 status
= inb(priv
->base
+ QUAD8_DIFF_ENCODER_CABLE_STATUS
);
1295 mutex_unlock(&priv
->lock
);
1297 /* Mask respective channel and invert logic */
1298 fault
= !(status
& BIT(channel_id
));
1300 return sprintf(buf
, "%u\n", fault
);
1303 static ssize_t
quad8_signal_cable_fault_enable_read(
1304 struct counter_device
*counter
, struct counter_signal
*signal
,
1305 void *private, char *buf
)
1307 const struct quad8_iio
*const priv
= counter
->priv
;
1308 const size_t channel_id
= signal
->id
/ 2;
1309 const unsigned int enb
= !!(priv
->cable_fault_enable
& BIT(channel_id
));
1311 return sprintf(buf
, "%u\n", enb
);
1314 static ssize_t
quad8_signal_cable_fault_enable_write(
1315 struct counter_device
*counter
, struct counter_signal
*signal
,
1316 void *private, const char *buf
, size_t len
)
1318 struct quad8_iio
*const priv
= counter
->priv
;
1319 const size_t channel_id
= signal
->id
/ 2;
1322 unsigned int cable_fault_enable
;
1324 ret
= kstrtobool(buf
, &enable
);
1328 mutex_lock(&priv
->lock
);
1331 priv
->cable_fault_enable
|= BIT(channel_id
);
1333 priv
->cable_fault_enable
&= ~BIT(channel_id
);
1335 /* Enable is active low in Differential Encoder Cable Status register */
1336 cable_fault_enable
= ~priv
->cable_fault_enable
;
1338 outb(cable_fault_enable
, priv
->base
+ QUAD8_DIFF_ENCODER_CABLE_STATUS
);
1340 mutex_unlock(&priv
->lock
);
1345 static ssize_t
quad8_signal_fck_prescaler_read(struct counter_device
*counter
,
1346 struct counter_signal
*signal
, void *private, char *buf
)
1348 const struct quad8_iio
*const priv
= counter
->priv
;
1349 const size_t channel_id
= signal
->id
/ 2;
1351 return sprintf(buf
, "%u\n", priv
->fck_prescaler
[channel_id
]);
1354 static ssize_t
quad8_signal_fck_prescaler_write(struct counter_device
*counter
,
1355 struct counter_signal
*signal
, void *private, const char *buf
,
1358 struct quad8_iio
*const priv
= counter
->priv
;
1359 const size_t channel_id
= signal
->id
/ 2;
1360 const int base_offset
= priv
->base
+ 2 * channel_id
;
1364 ret
= kstrtou8(buf
, 0, &prescaler
);
1368 mutex_lock(&priv
->lock
);
1370 priv
->fck_prescaler
[channel_id
] = prescaler
;
1372 /* Reset Byte Pointer */
1373 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
1375 /* Set filter clock factor */
1376 outb(prescaler
, base_offset
);
1377 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
| QUAD8_RLD_PRESET_PSC
,
1380 mutex_unlock(&priv
->lock
);
1385 static const struct counter_signal_ext quad8_signal_ext
[] = {
1387 .name
= "cable_fault",
1388 .read
= quad8_signal_cable_fault_read
1391 .name
= "cable_fault_enable",
1392 .read
= quad8_signal_cable_fault_enable_read
,
1393 .write
= quad8_signal_cable_fault_enable_write
1396 .name
= "filter_clock_prescaler",
1397 .read
= quad8_signal_fck_prescaler_read
,
1398 .write
= quad8_signal_fck_prescaler_write
1402 static const struct counter_signal_ext quad8_index_ext
[] = {
1403 COUNTER_SIGNAL_ENUM("index_polarity", &quad8_index_pol_enum
),
1404 COUNTER_SIGNAL_ENUM_AVAILABLE("index_polarity", &quad8_index_pol_enum
),
1405 COUNTER_SIGNAL_ENUM("synchronous_mode", &quad8_syn_mode_enum
),
1406 COUNTER_SIGNAL_ENUM_AVAILABLE("synchronous_mode", &quad8_syn_mode_enum
)
1409 #define QUAD8_QUAD_SIGNAL(_id, _name) { \
1412 .ext = quad8_signal_ext, \
1413 .num_ext = ARRAY_SIZE(quad8_signal_ext) \
1416 #define QUAD8_INDEX_SIGNAL(_id, _name) { \
1419 .ext = quad8_index_ext, \
1420 .num_ext = ARRAY_SIZE(quad8_index_ext) \
1423 static struct counter_signal quad8_signals
[] = {
1424 QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"),
1425 QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"),
1426 QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"),
1427 QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"),
1428 QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"),
1429 QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"),
1430 QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"),
1431 QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"),
1432 QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"),
1433 QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"),
1434 QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"),
1435 QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"),
1436 QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"),
1437 QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"),
1438 QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"),
1439 QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"),
1440 QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"),
1441 QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"),
1442 QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"),
1443 QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"),
1444 QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"),
1445 QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"),
1446 QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"),
1447 QUAD8_INDEX_SIGNAL(23, "Channel 8 Index")
1450 #define QUAD8_COUNT_SYNAPSES(_id) { \
1452 .actions_list = quad8_synapse_actions_list, \
1453 .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
1454 .signal = quad8_signals + 2 * (_id) \
1457 .actions_list = quad8_synapse_actions_list, \
1458 .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
1459 .signal = quad8_signals + 2 * (_id) + 1 \
1462 .actions_list = quad8_index_actions_list, \
1463 .num_actions = ARRAY_SIZE(quad8_index_actions_list), \
1464 .signal = quad8_signals + 2 * (_id) + 16 \
1468 static struct counter_synapse quad8_count_synapses
[][3] = {
1469 QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1),
1470 QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3),
1471 QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5),
1472 QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7)
1475 static const struct counter_count_ext quad8_count_ext
[] = {
1478 .read
= quad8_count_ceiling_read
,
1479 .write
= quad8_count_ceiling_write
1483 .read
= quad8_count_floor_read
1485 COUNTER_COUNT_ENUM("count_mode", &quad8_cnt_mode_enum
),
1486 COUNTER_COUNT_ENUM_AVAILABLE("count_mode", &quad8_cnt_mode_enum
),
1488 .name
= "direction",
1489 .read
= quad8_count_direction_read
1493 .read
= quad8_count_enable_read
,
1494 .write
= quad8_count_enable_write
1496 COUNTER_COUNT_ENUM("error_noise", &quad8_error_noise_enum
),
1497 COUNTER_COUNT_ENUM_AVAILABLE("error_noise", &quad8_error_noise_enum
),
1500 .read
= quad8_count_preset_read
,
1501 .write
= quad8_count_preset_write
1504 .name
= "preset_enable",
1505 .read
= quad8_count_preset_enable_read
,
1506 .write
= quad8_count_preset_enable_write
1510 #define QUAD8_COUNT(_id, _cntname) { \
1512 .name = (_cntname), \
1513 .functions_list = quad8_count_functions_list, \
1514 .num_functions = ARRAY_SIZE(quad8_count_functions_list), \
1515 .synapses = quad8_count_synapses[(_id)], \
1516 .num_synapses = 2, \
1517 .ext = quad8_count_ext, \
1518 .num_ext = ARRAY_SIZE(quad8_count_ext) \
1521 static struct counter_count quad8_counts
[] = {
1522 QUAD8_COUNT(0, "Channel 1 Count"),
1523 QUAD8_COUNT(1, "Channel 2 Count"),
1524 QUAD8_COUNT(2, "Channel 3 Count"),
1525 QUAD8_COUNT(3, "Channel 4 Count"),
1526 QUAD8_COUNT(4, "Channel 5 Count"),
1527 QUAD8_COUNT(5, "Channel 6 Count"),
1528 QUAD8_COUNT(6, "Channel 7 Count"),
1529 QUAD8_COUNT(7, "Channel 8 Count")
1532 static int quad8_probe(struct device
*dev
, unsigned int id
)
1534 struct iio_dev
*indio_dev
;
1535 struct quad8_iio
*quad8iio
;
1537 unsigned int base_offset
;
1540 if (!devm_request_region(dev
, base
[id
], QUAD8_EXTENT
, dev_name(dev
))) {
1541 dev_err(dev
, "Unable to lock port addresses (0x%X-0x%X)\n",
1542 base
[id
], base
[id
] + QUAD8_EXTENT
);
1546 /* Allocate IIO device; this also allocates driver data structure */
1547 indio_dev
= devm_iio_device_alloc(dev
, sizeof(*quad8iio
));
1551 /* Initialize IIO device */
1552 indio_dev
->info
= &quad8_info
;
1553 indio_dev
->modes
= INDIO_DIRECT_MODE
;
1554 indio_dev
->num_channels
= ARRAY_SIZE(quad8_channels
);
1555 indio_dev
->channels
= quad8_channels
;
1556 indio_dev
->name
= dev_name(dev
);
1558 /* Initialize Counter device and driver data */
1559 quad8iio
= iio_priv(indio_dev
);
1560 quad8iio
->counter
.name
= dev_name(dev
);
1561 quad8iio
->counter
.parent
= dev
;
1562 quad8iio
->counter
.ops
= &quad8_ops
;
1563 quad8iio
->counter
.counts
= quad8_counts
;
1564 quad8iio
->counter
.num_counts
= ARRAY_SIZE(quad8_counts
);
1565 quad8iio
->counter
.signals
= quad8_signals
;
1566 quad8iio
->counter
.num_signals
= ARRAY_SIZE(quad8_signals
);
1567 quad8iio
->counter
.priv
= quad8iio
;
1568 quad8iio
->base
= base
[id
];
1570 /* Initialize mutex */
1571 mutex_init(&quad8iio
->lock
);
1573 /* Reset all counters and disable interrupt function */
1574 outb(QUAD8_CHAN_OP_RESET_COUNTERS
, base
[id
] + QUAD8_REG_CHAN_OP
);
1575 /* Set initial configuration for all counters */
1576 for (i
= 0; i
< QUAD8_NUM_COUNTERS
; i
++) {
1577 base_offset
= base
[id
] + 2 * i
;
1578 /* Reset Byte Pointer */
1579 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
1580 /* Reset filter clock factor */
1581 outb(0, base_offset
);
1582 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
| QUAD8_RLD_PRESET_PSC
,
1584 /* Reset Byte Pointer */
1585 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_BP
, base_offset
+ 1);
1586 /* Reset Preset Register */
1587 for (j
= 0; j
< 3; j
++)
1588 outb(0x00, base_offset
);
1589 /* Reset Borrow, Carry, Compare, and Sign flags */
1590 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_FLAGS
, base_offset
+ 1);
1591 /* Reset Error flag */
1592 outb(QUAD8_CTR_RLD
| QUAD8_RLD_RESET_E
, base_offset
+ 1);
1593 /* Binary encoding; Normal count; non-quadrature mode */
1594 outb(QUAD8_CTR_CMR
, base_offset
+ 1);
1595 /* Disable A and B inputs; preset on index; FLG1 as Carry */
1596 outb(QUAD8_CTR_IOR
, base_offset
+ 1);
1597 /* Disable index function; negative index polarity */
1598 outb(QUAD8_CTR_IDR
, base_offset
+ 1);
1600 /* Disable Differential Encoder Cable Status for all channels */
1601 outb(0xFF, base
[id
] + QUAD8_DIFF_ENCODER_CABLE_STATUS
);
1602 /* Enable all counters */
1603 outb(QUAD8_CHAN_OP_ENABLE_COUNTERS
, base
[id
] + QUAD8_REG_CHAN_OP
);
1605 /* Register IIO device */
1606 err
= devm_iio_device_register(dev
, indio_dev
);
1610 /* Register Counter device */
1611 return devm_counter_register(dev
, &quad8iio
->counter
);
1614 static struct isa_driver quad8_driver
= {
1615 .probe
= quad8_probe
,
1617 .name
= "104-quad-8"
1621 module_isa_driver(quad8_driver
, num_quad8
);
1623 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
1624 MODULE_DESCRIPTION("ACCES 104-QUAD-8 IIO driver");
1625 MODULE_LICENSE("GPL v2");