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Merge tag 'trace-v5.11-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt...
[linux/fpc-iii.git] / drivers / edac / altera_edac.c
blobe91cf1147a4e0f4740a65f39560c35bc5a5ecec0
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
6 */
7
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
13 #include <linux/genalloc.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/altera-sysmgr.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/notifier.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/types.h>
26 #include <linux/uaccess.h>
27
28 #include "altera_edac.h"
29 #include "edac_module.h"
30
31 #define EDAC_MOD_STR "altera_edac"
32 #define EDAC_DEVICE "Altera"
33
34 #ifdef CONFIG_EDAC_ALTERA_SDRAM
35 static const struct altr_sdram_prv_data c5_data = {
36 .ecc_ctrl_offset = CV_CTLCFG_OFST,
37 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
38 .ecc_stat_offset = CV_DRAMSTS_OFST,
39 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
40 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
41 .ecc_saddr_offset = CV_ERRADDR_OFST,
42 .ecc_daddr_offset = CV_ERRADDR_OFST,
43 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
44 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
45 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
46 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
47 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
48 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
49 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
50 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
51 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
52 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
53 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
54 };
55
56 static const struct altr_sdram_prv_data a10_data = {
57 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
58 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
59 .ecc_stat_offset = A10_INTSTAT_OFST,
60 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
61 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
62 .ecc_saddr_offset = A10_SERRADDR_OFST,
63 .ecc_daddr_offset = A10_DERRADDR_OFST,
64 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
65 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
66 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
67 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
68 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
69 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
70 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
71 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
72 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
73 };
74
75 /*********************** EDAC Memory Controller Functions ****************/
76
77 /* The SDRAM controller uses the EDAC Memory Controller framework. */
78
79 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
80 {
81 struct mem_ctl_info *mci = dev_id;
82 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
83 const struct altr_sdram_prv_data *priv = drvdata->data;
84 u32 status, err_count = 1, err_addr;
85
86 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
87
88 if (status & priv->ecc_stat_ue_mask) {
89 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
90 &err_addr);
91 if (priv->ecc_uecnt_offset)
92 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
93 &err_count);
94 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
95 err_count, err_addr);
96 }
97 if (status & priv->ecc_stat_ce_mask) {
98 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
99 &err_addr);
100 if (priv->ecc_uecnt_offset)
101 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
102 &err_count);
103 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
104 err_addr >> PAGE_SHIFT,
105 err_addr & ~PAGE_MASK, 0,
106 0, 0, -1, mci->ctl_name, "");
107 /* Clear IRQ to resume */
108 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
109 priv->ecc_irq_clr_mask);
110
111 return IRQ_HANDLED;
112 }
113 return IRQ_NONE;
114 }
115
116 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
117 const char __user *data,
118 size_t count, loff_t *ppos)
119 {
120 struct mem_ctl_info *mci = file->private_data;
121 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
122 const struct altr_sdram_prv_data *priv = drvdata->data;
123 u32 *ptemp;
124 dma_addr_t dma_handle;
125 u32 reg, read_reg;
126
127 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
128 if (!ptemp) {
129 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
130 edac_printk(KERN_ERR, EDAC_MC,
131 "Inject: Buffer Allocation error\n");
132 return -ENOMEM;
133 }
134
135 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
136 &read_reg);
137 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
138
139 /* Error are injected by writing a word while the SBE or DBE
140 * bit in the CTLCFG register is set. Reading the word will
141 * trigger the SBE or DBE error and the corresponding IRQ.
142 */
143 if (count == 3) {
144 edac_printk(KERN_ALERT, EDAC_MC,
145 "Inject Double bit error\n");
146 local_irq_disable();
147 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
148 (read_reg | priv->ue_set_mask));
149 local_irq_enable();
150 } else {
151 edac_printk(KERN_ALERT, EDAC_MC,
152 "Inject Single bit error\n");
153 local_irq_disable();
154 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
155 (read_reg | priv->ce_set_mask));
156 local_irq_enable();
157 }
158
159 ptemp[0] = 0x5A5A5A5A;
160 ptemp[1] = 0xA5A5A5A5;
161
162 /* Clear the error injection bits */
163 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
164 /* Ensure it has been written out */
165 wmb();
166
167 /*
168 * To trigger the error, we need to read the data back
169 * (the data was written with errors above).
170 * The READ_ONCE macros and printk are used to prevent the
171 * the compiler optimizing these reads out.
172 */
173 reg = READ_ONCE(ptemp[0]);
174 read_reg = READ_ONCE(ptemp[1]);
175 /* Force Read */
176 rmb();
177
178 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
179 reg, read_reg);
180
181 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
182
183 return count;
184 }
185
186 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
187 .open = simple_open,
188 .write = altr_sdr_mc_err_inject_write,
189 .llseek = generic_file_llseek,
190 };
191
192 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
193 {
194 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
195 return;
196
197 if (!mci->debugfs)
198 return;
199
200 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
201 &altr_sdr_mc_debug_inject_fops);
202 }
203
204 /* Get total memory size from Open Firmware DTB */
205 static unsigned long get_total_mem(void)
206 {
207 struct device_node *np = NULL;
208 struct resource res;
209 int ret;
210 unsigned long total_mem = 0;
211
212 for_each_node_by_type(np, "memory") {
213 ret = of_address_to_resource(np, 0, &res);
214 if (ret)
215 continue;
216
217 total_mem += resource_size(&res);
218 }
219 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
220 return total_mem;
221 }
222
223 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
224 { .compatible = "altr,sdram-edac", .data = &c5_data},
225 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
226 {},
227 };
228 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
229
230 static int a10_init(struct regmap *mc_vbase)
231 {
232 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
233 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
234 edac_printk(KERN_ERR, EDAC_MC,
235 "Error setting SB IRQ mode\n");
236 return -ENODEV;
237 }
238
239 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
240 edac_printk(KERN_ERR, EDAC_MC,
241 "Error setting trigger count\n");
242 return -ENODEV;
243 }
244
245 return 0;
246 }
247
248 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
249 {
250 void __iomem *sm_base;
251 int ret = 0;
252
253 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
254 dev_name(&pdev->dev))) {
255 edac_printk(KERN_ERR, EDAC_MC,
256 "Unable to request mem region\n");
257 return -EBUSY;
258 }
259
260 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
261 if (!sm_base) {
262 edac_printk(KERN_ERR, EDAC_MC,
263 "Unable to ioremap device\n");
264
265 ret = -ENOMEM;
266 goto release;
267 }
268
269 iowrite32(mask, sm_base);
270
271 iounmap(sm_base);
272
273 release:
274 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
275
276 return ret;
277 }
278
279 static int altr_sdram_probe(struct platform_device *pdev)
280 {
281 const struct of_device_id *id;
282 struct edac_mc_layer layers[2];
283 struct mem_ctl_info *mci;
284 struct altr_sdram_mc_data *drvdata;
285 const struct altr_sdram_prv_data *priv;
286 struct regmap *mc_vbase;
287 struct dimm_info *dimm;
288 u32 read_reg;
289 int irq, irq2, res = 0;
290 unsigned long mem_size, irqflags = 0;
291
292 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
293 if (!id)
294 return -ENODEV;
295
296 /* Grab the register range from the sdr controller in device tree */
297 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
298 "altr,sdr-syscon");
299 if (IS_ERR(mc_vbase)) {
300 edac_printk(KERN_ERR, EDAC_MC,
301 "regmap for altr,sdr-syscon lookup failed.\n");
302 return -ENODEV;
303 }
304
305 /* Check specific dependencies for the module */
306 priv = of_match_node(altr_sdram_ctrl_of_match,
307 pdev->dev.of_node)->data;
308
309 /* Validate the SDRAM controller has ECC enabled */
310 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
311 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
312 edac_printk(KERN_ERR, EDAC_MC,
313 "No ECC/ECC disabled [0x%08X]\n", read_reg);
314 return -ENODEV;
315 }
316
317 /* Grab memory size from device tree. */
318 mem_size = get_total_mem();
319 if (!mem_size) {
320 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
321 return -ENODEV;
322 }
323
324 /* Ensure the SDRAM Interrupt is disabled */
325 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
326 priv->ecc_irq_en_mask, 0)) {
327 edac_printk(KERN_ERR, EDAC_MC,
328 "Error disabling SDRAM ECC IRQ\n");
329 return -ENODEV;
330 }
331
332 /* Toggle to clear the SDRAM Error count */
333 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
334 priv->ecc_cnt_rst_mask,
335 priv->ecc_cnt_rst_mask)) {
336 edac_printk(KERN_ERR, EDAC_MC,
337 "Error clearing SDRAM ECC count\n");
338 return -ENODEV;
339 }
340
341 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
342 priv->ecc_cnt_rst_mask, 0)) {
343 edac_printk(KERN_ERR, EDAC_MC,
344 "Error clearing SDRAM ECC count\n");
345 return -ENODEV;
346 }
347
348 irq = platform_get_irq(pdev, 0);
349 if (irq < 0) {
350 edac_printk(KERN_ERR, EDAC_MC,
351 "No irq %d in DT\n", irq);
352 return -ENODEV;
353 }
354
355 /* Arria10 has a 2nd IRQ */
356 irq2 = platform_get_irq(pdev, 1);
357
358 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
359 layers[0].size = 1;
360 layers[0].is_virt_csrow = true;
361 layers[1].type = EDAC_MC_LAYER_CHANNEL;
362 layers[1].size = 1;
363 layers[1].is_virt_csrow = false;
364 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
365 sizeof(struct altr_sdram_mc_data));
366 if (!mci)
367 return -ENOMEM;
368
369 mci->pdev = &pdev->dev;
370 drvdata = mci->pvt_info;
371 drvdata->mc_vbase = mc_vbase;
372 drvdata->data = priv;
373 platform_set_drvdata(pdev, mci);
374
375 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
376 edac_printk(KERN_ERR, EDAC_MC,
377 "Unable to get managed device resource\n");
378 res = -ENOMEM;
379 goto free;
380 }
381
382 mci->mtype_cap = MEM_FLAG_DDR3;
383 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
384 mci->edac_cap = EDAC_FLAG_SECDED;
385 mci->mod_name = EDAC_MOD_STR;
386 mci->ctl_name = dev_name(&pdev->dev);
387 mci->scrub_mode = SCRUB_SW_SRC;
388 mci->dev_name = dev_name(&pdev->dev);
389
390 dimm = *mci->dimms;
391 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
392 dimm->grain = 8;
393 dimm->dtype = DEV_X8;
394 dimm->mtype = MEM_DDR3;
395 dimm->edac_mode = EDAC_SECDED;
396
397 res = edac_mc_add_mc(mci);
398 if (res < 0)
399 goto err;
400
401 /* Only the Arria10 has separate IRQs */
402 if (of_machine_is_compatible("altr,socfpga-arria10")) {
403 /* Arria10 specific initialization */
404 res = a10_init(mc_vbase);
405 if (res < 0)
406 goto err2;
407
408 res = devm_request_irq(&pdev->dev, irq2,
409 altr_sdram_mc_err_handler,
410 IRQF_SHARED, dev_name(&pdev->dev), mci);
411 if (res < 0) {
412 edac_mc_printk(mci, KERN_ERR,
413 "Unable to request irq %d\n", irq2);
414 res = -ENODEV;
415 goto err2;
416 }
417
418 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
419 if (res < 0)
420 goto err2;
421
422 irqflags = IRQF_SHARED;
423 }
424
425 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
426 irqflags, dev_name(&pdev->dev), mci);
427 if (res < 0) {
428 edac_mc_printk(mci, KERN_ERR,
429 "Unable to request irq %d\n", irq);
430 res = -ENODEV;
431 goto err2;
432 }
433
434 /* Infrastructure ready - enable the IRQ */
435 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
436 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
437 edac_mc_printk(mci, KERN_ERR,
438 "Error enabling SDRAM ECC IRQ\n");
439 res = -ENODEV;
440 goto err2;
441 }
442
443 altr_sdr_mc_create_debugfs_nodes(mci);
444
445 devres_close_group(&pdev->dev, NULL);
446
447 return 0;
448
449 err2:
450 edac_mc_del_mc(&pdev->dev);
451 err:
452 devres_release_group(&pdev->dev, NULL);
453 free:
454 edac_mc_free(mci);
455 edac_printk(KERN_ERR, EDAC_MC,
456 "EDAC Probe Failed; Error %d\n", res);
457
458 return res;
459 }
460
461 static int altr_sdram_remove(struct platform_device *pdev)
462 {
463 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
464
465 edac_mc_del_mc(&pdev->dev);
466 edac_mc_free(mci);
467 platform_set_drvdata(pdev, NULL);
468
469 return 0;
470 }
471
472 /*
473 * If you want to suspend, need to disable EDAC by removing it
474 * from the device tree or defconfig.
475 */
476 #ifdef CONFIG_PM
477 static int altr_sdram_prepare(struct device *dev)
478 {
479 pr_err("Suspend not allowed when EDAC is enabled.\n");
480
481 return -EPERM;
482 }
483
484 static const struct dev_pm_ops altr_sdram_pm_ops = {
485 .prepare = altr_sdram_prepare,
486 };
487 #endif
488
489 static struct platform_driver altr_sdram_edac_driver = {
490 .probe = altr_sdram_probe,
491 .remove = altr_sdram_remove,
492 .driver = {
493 .name = "altr_sdram_edac",
494 #ifdef CONFIG_PM
495 .pm = &altr_sdram_pm_ops,
496 #endif
497 .of_match_table = altr_sdram_ctrl_of_match,
498 },
499 };
500
501 module_platform_driver(altr_sdram_edac_driver);
502
503 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
504
505 /************************* EDAC Parent Probe *************************/
506
507 static const struct of_device_id altr_edac_device_of_match[];
508
509 static const struct of_device_id altr_edac_of_match[] = {
510 { .compatible = "altr,socfpga-ecc-manager" },
511 {},
512 };
513 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
514
515 static int altr_edac_probe(struct platform_device *pdev)
516 {
517 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
518 NULL, &pdev->dev);
519 return 0;
520 }
521
522 static struct platform_driver altr_edac_driver = {
523 .probe = altr_edac_probe,
524 .driver = {
525 .name = "socfpga_ecc_manager",
526 .of_match_table = altr_edac_of_match,
527 },
528 };
529 module_platform_driver(altr_edac_driver);
530
531 /************************* EDAC Device Functions *************************/
532
533 /*
534 * EDAC Device Functions (shared between various IPs).
535 * The discrete memories use the EDAC Device framework. The probe
536 * and error handling functions are very similar between memories
537 * so they are shared. The memory allocation and freeing for EDAC
538 * trigger testing are different for each memory.
539 */
540
541 static const struct edac_device_prv_data ocramecc_data;
542 static const struct edac_device_prv_data l2ecc_data;
543 static const struct edac_device_prv_data a10_ocramecc_data;
544 static const struct edac_device_prv_data a10_l2ecc_data;
545
546 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
547 {
548 irqreturn_t ret_value = IRQ_NONE;
549 struct edac_device_ctl_info *dci = dev_id;
550 struct altr_edac_device_dev *drvdata = dci->pvt_info;
551 const struct edac_device_prv_data *priv = drvdata->data;
552
553 if (irq == drvdata->sb_irq) {
554 if (priv->ce_clear_mask)
555 writel(priv->ce_clear_mask, drvdata->base);
556 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
557 ret_value = IRQ_HANDLED;
558 } else if (irq == drvdata->db_irq) {
559 if (priv->ue_clear_mask)
560 writel(priv->ue_clear_mask, drvdata->base);
561 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
562 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
563 ret_value = IRQ_HANDLED;
564 } else {
565 WARN_ON(1);
566 }
567
568 return ret_value;
569 }
570
571 static ssize_t altr_edac_device_trig(struct file *file,
572 const char __user *user_buf,
573 size_t count, loff_t *ppos)
574
575 {
576 u32 *ptemp, i, error_mask;
577 int result = 0;
578 u8 trig_type;
579 unsigned long flags;
580 struct edac_device_ctl_info *edac_dci = file->private_data;
581 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
582 const struct edac_device_prv_data *priv = drvdata->data;
583 void *generic_ptr = edac_dci->dev;
584
585 if (!user_buf || get_user(trig_type, user_buf))
586 return -EFAULT;
587
588 if (!priv->alloc_mem)
589 return -ENOMEM;
590
591 /*
592 * Note that generic_ptr is initialized to the device * but in
593 * some alloc_functions, this is overridden and returns data.
594 */
595 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
596 if (!ptemp) {
597 edac_printk(KERN_ERR, EDAC_DEVICE,
598 "Inject: Buffer Allocation error\n");
599 return -ENOMEM;
600 }
601
602 if (trig_type == ALTR_UE_TRIGGER_CHAR)
603 error_mask = priv->ue_set_mask;
604 else
605 error_mask = priv->ce_set_mask;
606
607 edac_printk(KERN_ALERT, EDAC_DEVICE,
608 "Trigger Error Mask (0x%X)\n", error_mask);
609
610 local_irq_save(flags);
611 /* write ECC corrupted data out. */
612 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
613 /* Read data so we're in the correct state */
614 rmb();
615 if (READ_ONCE(ptemp[i]))
616 result = -1;
617 /* Toggle Error bit (it is latched), leave ECC enabled */
618 writel(error_mask, (drvdata->base + priv->set_err_ofst));
619 writel(priv->ecc_enable_mask, (drvdata->base +
620 priv->set_err_ofst));
621 ptemp[i] = i;
622 }
623 /* Ensure it has been written out */
624 wmb();
625 local_irq_restore(flags);
626
627 if (result)
628 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
629
630 /* Read out written data. ECC error caused here */
631 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
632 if (READ_ONCE(ptemp[i]) != i)
633 edac_printk(KERN_ERR, EDAC_DEVICE,
634 "Read doesn't match written data\n");
635
636 if (priv->free_mem)
637 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
638
639 return count;
640 }
641
642 static const struct file_operations altr_edac_device_inject_fops = {
643 .open = simple_open,
644 .write = altr_edac_device_trig,
645 .llseek = generic_file_llseek,
646 };
647
648 static ssize_t altr_edac_a10_device_trig(struct file *file,
649 const char __user *user_buf,
650 size_t count, loff_t *ppos);
651
652 static const struct file_operations altr_edac_a10_device_inject_fops = {
653 .open = simple_open,
654 .write = altr_edac_a10_device_trig,
655 .llseek = generic_file_llseek,
656 };
657
658 static ssize_t altr_edac_a10_device_trig2(struct file *file,
659 const char __user *user_buf,
660 size_t count, loff_t *ppos);
661
662 static const struct file_operations altr_edac_a10_device_inject2_fops = {
663 .open = simple_open,
664 .write = altr_edac_a10_device_trig2,
665 .llseek = generic_file_llseek,
666 };
667
668 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
669 const struct edac_device_prv_data *priv)
670 {
671 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
672
673 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
674 return;
675
676 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
677 if (!drvdata->debugfs_dir)
678 return;
679
680 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
681 drvdata->debugfs_dir, edac_dci,
682 priv->inject_fops))
683 debugfs_remove_recursive(drvdata->debugfs_dir);
684 }
685
686 static const struct of_device_id altr_edac_device_of_match[] = {
687 #ifdef CONFIG_EDAC_ALTERA_L2C
688 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
689 #endif
690 #ifdef CONFIG_EDAC_ALTERA_OCRAM
691 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
692 #endif
693 {},
694 };
695 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
696
697 /*
698 * altr_edac_device_probe()
699 * This is a generic EDAC device driver that will support
700 * various Altera memory devices such as the L2 cache ECC and
701 * OCRAM ECC as well as the memories for other peripherals.
702 * Module specific initialization is done by passing the
703 * function index in the device tree.
704 */
705 static int altr_edac_device_probe(struct platform_device *pdev)
706 {
707 struct edac_device_ctl_info *dci;
708 struct altr_edac_device_dev *drvdata;
709 struct resource *r;
710 int res = 0;
711 struct device_node *np = pdev->dev.of_node;
712 char *ecc_name = (char *)np->name;
713 static int dev_instance;
714
715 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
716 edac_printk(KERN_ERR, EDAC_DEVICE,
717 "Unable to open devm\n");
718 return -ENOMEM;
719 }
720
721 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
722 if (!r) {
723 edac_printk(KERN_ERR, EDAC_DEVICE,
724 "Unable to get mem resource\n");
725 res = -ENODEV;
726 goto fail;
727 }
728
729 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
730 dev_name(&pdev->dev))) {
731 edac_printk(KERN_ERR, EDAC_DEVICE,
732 "%s:Error requesting mem region\n", ecc_name);
733 res = -EBUSY;
734 goto fail;
735 }
736
737 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
738 1, ecc_name, 1, 0, NULL, 0,
739 dev_instance++);
740
741 if (!dci) {
742 edac_printk(KERN_ERR, EDAC_DEVICE,
743 "%s: Unable to allocate EDAC device\n", ecc_name);
744 res = -ENOMEM;
745 goto fail;
746 }
747
748 drvdata = dci->pvt_info;
749 dci->dev = &pdev->dev;
750 platform_set_drvdata(pdev, dci);
751 drvdata->edac_dev_name = ecc_name;
752
753 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
754 if (!drvdata->base) {
755 res = -ENOMEM;
756 goto fail1;
757 }
758
759 /* Get driver specific data for this EDAC device */
760 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
761
762 /* Check specific dependencies for the module */
763 if (drvdata->data->setup) {
764 res = drvdata->data->setup(drvdata);
765 if (res)
766 goto fail1;
767 }
768
769 drvdata->sb_irq = platform_get_irq(pdev, 0);
770 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
771 altr_edac_device_handler,
772 0, dev_name(&pdev->dev), dci);
773 if (res)
774 goto fail1;
775
776 drvdata->db_irq = platform_get_irq(pdev, 1);
777 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
778 altr_edac_device_handler,
779 0, dev_name(&pdev->dev), dci);
780 if (res)
781 goto fail1;
782
783 dci->mod_name = "Altera ECC Manager";
784 dci->dev_name = drvdata->edac_dev_name;
785
786 res = edac_device_add_device(dci);
787 if (res)
788 goto fail1;
789
790 altr_create_edacdev_dbgfs(dci, drvdata->data);
791
792 devres_close_group(&pdev->dev, NULL);
793
794 return 0;
795
796 fail1:
797 edac_device_free_ctl_info(dci);
798 fail:
799 devres_release_group(&pdev->dev, NULL);
800 edac_printk(KERN_ERR, EDAC_DEVICE,
801 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
802
803 return res;
804 }
805
806 static int altr_edac_device_remove(struct platform_device *pdev)
807 {
808 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
809 struct altr_edac_device_dev *drvdata = dci->pvt_info;
810
811 debugfs_remove_recursive(drvdata->debugfs_dir);
812 edac_device_del_device(&pdev->dev);
813 edac_device_free_ctl_info(dci);
814
815 return 0;
816 }
817
818 static struct platform_driver altr_edac_device_driver = {
819 .probe = altr_edac_device_probe,
820 .remove = altr_edac_device_remove,
821 .driver = {
822 .name = "altr_edac_device",
823 .of_match_table = altr_edac_device_of_match,
824 },
825 };
826 module_platform_driver(altr_edac_device_driver);
827
828 /******************* Arria10 Device ECC Shared Functions *****************/
829
830 /*
831 * Test for memory's ECC dependencies upon entry because platform specific
832 * startup should have initialized the memory and enabled the ECC.
833 * Can't turn on ECC here because accessing un-initialized memory will
834 * cause CE/UE errors possibly causing an ABORT.
835 */
836 static int __maybe_unused
837 altr_check_ecc_deps(struct altr_edac_device_dev *device)
838 {
839 void __iomem *base = device->base;
840 const struct edac_device_prv_data *prv = device->data;
841
842 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
843 return 0;
844
845 edac_printk(KERN_ERR, EDAC_DEVICE,
846 "%s: No ECC present or ECC disabled.\n",
847 device->edac_dev_name);
848 return -ENODEV;
849 }
850
851 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
852 {
853 struct altr_edac_device_dev *dci = dev_id;
854 void __iomem *base = dci->base;
855
856 if (irq == dci->sb_irq) {
857 writel(ALTR_A10_ECC_SERRPENA,
858 base + ALTR_A10_ECC_INTSTAT_OFST);
859 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
860
861 return IRQ_HANDLED;
862 } else if (irq == dci->db_irq) {
863 writel(ALTR_A10_ECC_DERRPENA,
864 base + ALTR_A10_ECC_INTSTAT_OFST);
865 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
866 if (dci->data->panic)
867 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
868
869 return IRQ_HANDLED;
870 }
871
872 WARN_ON(1);
873
874 return IRQ_NONE;
875 }
876
877 /******************* Arria10 Memory Buffer Functions *********************/
878
879 static inline int a10_get_irq_mask(struct device_node *np)
880 {
881 int irq;
882 const u32 *handle = of_get_property(np, "interrupts", NULL);
883
884 if (!handle)
885 return -ENODEV;
886 irq = be32_to_cpup(handle);
887 return irq;
888 }
889
890 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
891 {
892 u32 value = readl(ioaddr);
893
894 value |= bit_mask;
895 writel(value, ioaddr);
896 }
897
898 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
899 {
900 u32 value = readl(ioaddr);
901
902 value &= ~bit_mask;
903 writel(value, ioaddr);
904 }
905
906 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
907 {
908 u32 value = readl(ioaddr);
909
910 return (value & bit_mask) ? 1 : 0;
911 }
912
913 /*
914 * This function uses the memory initialization block in the Arria10 ECC
915 * controller to initialize/clear the entire memory data and ECC data.
916 */
917 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
918 {
919 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
920 u32 init_mask, stat_mask, clear_mask;
921 int ret = 0;
922
923 if (port) {
924 init_mask = ALTR_A10_ECC_INITB;
925 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
926 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
927 } else {
928 init_mask = ALTR_A10_ECC_INITA;
929 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
930 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
931 }
932
933 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
934 while (limit--) {
935 if (ecc_test_bits(stat_mask,
936 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
937 break;
938 udelay(1);
939 }
940 if (limit < 0)
941 ret = -EBUSY;
942
943 /* Clear any pending ECC interrupts */
944 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
945
946 return ret;
947 }
948
949 static __init int __maybe_unused
950 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
951 u32 ecc_ctrl_en_mask, bool dual_port)
952 {
953 int ret = 0;
954 void __iomem *ecc_block_base;
955 struct regmap *ecc_mgr_map;
956 char *ecc_name;
957 struct device_node *np_eccmgr;
958
959 ecc_name = (char *)np->name;
960
961 /* Get the ECC Manager - parent of the device EDACs */
962 np_eccmgr = of_get_parent(np);
963
964 ecc_mgr_map =
965 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
966 "altr,sysmgr-syscon");
967
968 of_node_put(np_eccmgr);
969 if (IS_ERR(ecc_mgr_map)) {
970 edac_printk(KERN_ERR, EDAC_DEVICE,
971 "Unable to get syscon altr,sysmgr-syscon\n");
972 return -ENODEV;
973 }
974
975 /* Map the ECC Block */
976 ecc_block_base = of_iomap(np, 0);
977 if (!ecc_block_base) {
978 edac_printk(KERN_ERR, EDAC_DEVICE,
979 "Unable to map %s ECC block\n", ecc_name);
980 return -ENODEV;
981 }
982
983 /* Disable ECC */
984 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
985 writel(ALTR_A10_ECC_SERRINTEN,
986 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
987 ecc_clear_bits(ecc_ctrl_en_mask,
988 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
989 /* Ensure all writes complete */
990 wmb();
991 /* Use HW initialization block to initialize memory for ECC */
992 ret = altr_init_memory_port(ecc_block_base, 0);
993 if (ret) {
994 edac_printk(KERN_ERR, EDAC_DEVICE,
995 "ECC: cannot init %s PORTA memory\n", ecc_name);
996 goto out;
997 }
998
999 if (dual_port) {
1000 ret = altr_init_memory_port(ecc_block_base, 1);
1001 if (ret) {
1002 edac_printk(KERN_ERR, EDAC_DEVICE,
1003 "ECC: cannot init %s PORTB memory\n",
1004 ecc_name);
1005 goto out;
1006 }
1007 }
1008
1009 /* Interrupt mode set to every SBERR */
1010 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1011 ALTR_A10_ECC_INTMODE);
1012 /* Enable ECC */
1013 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1014 ALTR_A10_ECC_CTRL_OFST));
1015 writel(ALTR_A10_ECC_SERRINTEN,
1016 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1017 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1018 /* Ensure all writes complete */
1019 wmb();
1020 out:
1021 iounmap(ecc_block_base);
1022 return ret;
1023 }
1024
1025 static int validate_parent_available(struct device_node *np);
1026 static const struct of_device_id altr_edac_a10_device_of_match[];
1027 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1028 {
1029 int irq;
1030 struct device_node *child, *np;
1031
1032 np = of_find_compatible_node(NULL, NULL,
1033 "altr,socfpga-a10-ecc-manager");
1034 if (!np) {
1035 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1036 return -ENODEV;
1037 }
1038
1039 for_each_child_of_node(np, child) {
1040 const struct of_device_id *pdev_id;
1041 const struct edac_device_prv_data *prv;
1042
1043 if (!of_device_is_available(child))
1044 continue;
1045 if (!of_device_is_compatible(child, compat))
1046 continue;
1047
1048 if (validate_parent_available(child))
1049 continue;
1050
1051 irq = a10_get_irq_mask(child);
1052 if (irq < 0)
1053 continue;
1054
1055 /* Get matching node and check for valid result */
1056 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1057 if (IS_ERR_OR_NULL(pdev_id))
1058 continue;
1059
1060 /* Validate private data pointer before dereferencing */
1061 prv = pdev_id->data;
1062 if (!prv)
1063 continue;
1064
1065 altr_init_a10_ecc_block(child, BIT(irq),
1066 prv->ecc_enable_mask, 0);
1067 }
1068
1069 of_node_put(np);
1070 return 0;
1071 }
1072
1073 /*********************** SDRAM EDAC Device Functions *********************/
1074
1075 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1076
1077 static const struct edac_device_prv_data s10_sdramecc_data = {
1078 .setup = altr_check_ecc_deps,
1079 .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1080 .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1081 .ecc_enable_mask = ALTR_S10_ECC_EN,
1082 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1083 .ce_set_mask = ALTR_S10_ECC_TSERRA,
1084 .ue_set_mask = ALTR_S10_ECC_TDERRA,
1085 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1086 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1087 .inject_fops = &altr_edac_a10_device_inject_fops,
1088 };
1089 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
1090
1091 /*********************** OCRAM EDAC Device Functions *********************/
1092
1093 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1094
1095 static void *ocram_alloc_mem(size_t size, void **other)
1096 {
1097 struct device_node *np;
1098 struct gen_pool *gp;
1099 void *sram_addr;
1100
1101 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1102 if (!np)
1103 return NULL;
1104
1105 gp = of_gen_pool_get(np, "iram", 0);
1106 of_node_put(np);
1107 if (!gp)
1108 return NULL;
1109
1110 sram_addr = (void *)gen_pool_alloc(gp, size);
1111 if (!sram_addr)
1112 return NULL;
1113
1114 memset(sram_addr, 0, size);
1115 /* Ensure data is written out */
1116 wmb();
1117
1118 /* Remember this handle for freeing later */
1119 *other = gp;
1120
1121 return sram_addr;
1122 }
1123
1124 static void ocram_free_mem(void *p, size_t size, void *other)
1125 {
1126 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1127 }
1128
1129 static const struct edac_device_prv_data ocramecc_data = {
1130 .setup = altr_check_ecc_deps,
1131 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1132 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1133 .alloc_mem = ocram_alloc_mem,
1134 .free_mem = ocram_free_mem,
1135 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1136 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1137 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1138 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1139 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1140 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1141 .inject_fops = &altr_edac_device_inject_fops,
1142 };
1143
1144 static int __maybe_unused
1145 altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1146 {
1147 void __iomem *base = device->base;
1148 int ret;
1149
1150 ret = altr_check_ecc_deps(device);
1151 if (ret)
1152 return ret;
1153
1154 /* Verify OCRAM has been initialized */
1155 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1156 (base + ALTR_A10_ECC_INITSTAT_OFST)))
1157 return -ENODEV;
1158
1159 /* Enable IRQ on Single Bit Error */
1160 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1161 /* Ensure all writes complete */
1162 wmb();
1163
1164 return 0;
1165 }
1166
1167 static const struct edac_device_prv_data a10_ocramecc_data = {
1168 .setup = altr_check_ocram_deps_init,
1169 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1170 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1171 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1172 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1173 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1174 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1175 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1176 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1177 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1178 .inject_fops = &altr_edac_a10_device_inject2_fops,
1179 /*
1180 * OCRAM panic on uncorrectable error because sleep/resume
1181 * functions and FPGA contents are stored in OCRAM. Prefer
1182 * a kernel panic over executing/loading corrupted data.
1183 */
1184 .panic = true,
1185 };
1186
1187 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1188
1189 /********************* L2 Cache EDAC Device Functions ********************/
1190
1191 #ifdef CONFIG_EDAC_ALTERA_L2C
1192
1193 static void *l2_alloc_mem(size_t size, void **other)
1194 {
1195 struct device *dev = *other;
1196 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1197
1198 if (!ptemp)
1199 return NULL;
1200
1201 /* Make sure everything is written out */
1202 wmb();
1203
1204 /*
1205 * Clean all cache levels up to LoC (includes L2)
1206 * This ensures the corrupted data is written into
1207 * L2 cache for readback test (which causes ECC error).
1208 */
1209 flush_cache_all();
1210
1211 return ptemp;
1212 }
1213
1214 static void l2_free_mem(void *p, size_t size, void *other)
1215 {
1216 struct device *dev = other;
1217
1218 if (dev && p)
1219 devm_kfree(dev, p);
1220 }
1221
1222 /*
1223 * altr_l2_check_deps()
1224 * Test for L2 cache ECC dependencies upon entry because
1225 * platform specific startup should have initialized the L2
1226 * memory and enabled the ECC.
1227 * Bail if ECC is not enabled.
1228 * Note that L2 Cache Enable is forced at build time.
1229 */
1230 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1231 {
1232 void __iomem *base = device->base;
1233 const struct edac_device_prv_data *prv = device->data;
1234
1235 if ((readl(base) & prv->ecc_enable_mask) ==
1236 prv->ecc_enable_mask)
1237 return 0;
1238
1239 edac_printk(KERN_ERR, EDAC_DEVICE,
1240 "L2: No ECC present, or ECC disabled\n");
1241 return -ENODEV;
1242 }
1243
1244 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1245 {
1246 struct altr_edac_device_dev *dci = dev_id;
1247
1248 if (irq == dci->sb_irq) {
1249 regmap_write(dci->edac->ecc_mgr_map,
1250 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1251 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1252 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1253
1254 return IRQ_HANDLED;
1255 } else if (irq == dci->db_irq) {
1256 regmap_write(dci->edac->ecc_mgr_map,
1257 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1258 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1259 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1260 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1261
1262 return IRQ_HANDLED;
1263 }
1264
1265 WARN_ON(1);
1266
1267 return IRQ_NONE;
1268 }
1269
1270 static const struct edac_device_prv_data l2ecc_data = {
1271 .setup = altr_l2_check_deps,
1272 .ce_clear_mask = 0,
1273 .ue_clear_mask = 0,
1274 .alloc_mem = l2_alloc_mem,
1275 .free_mem = l2_free_mem,
1276 .ecc_enable_mask = ALTR_L2_ECC_EN,
1277 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1278 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1279 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1280 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1281 .inject_fops = &altr_edac_device_inject_fops,
1282 };
1283
1284 static const struct edac_device_prv_data a10_l2ecc_data = {
1285 .setup = altr_l2_check_deps,
1286 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1287 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1288 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1289 .alloc_mem = l2_alloc_mem,
1290 .free_mem = l2_free_mem,
1291 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1292 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1293 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1294 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1295 .ecc_irq_handler = altr_edac_a10_l2_irq,
1296 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1297 .inject_fops = &altr_edac_device_inject_fops,
1298 };
1299
1300 #endif /* CONFIG_EDAC_ALTERA_L2C */
1301
1302 /********************* Ethernet Device Functions ********************/
1303
1304 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1305
1306 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1307 {
1308 int ret;
1309
1310 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1311 if (ret)
1312 return ret;
1313
1314 return altr_check_ecc_deps(dev);
1315 }
1316
1317 static const struct edac_device_prv_data a10_enetecc_data = {
1318 .setup = socfpga_init_ethernet_ecc,
1319 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1320 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1321 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1322 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1323 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1324 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1325 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1326 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1327 .inject_fops = &altr_edac_a10_device_inject2_fops,
1328 };
1329
1330 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1331
1332 /********************** NAND Device Functions **********************/
1333
1334 #ifdef CONFIG_EDAC_ALTERA_NAND
1335
1336 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1337 {
1338 int ret;
1339
1340 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1341 if (ret)
1342 return ret;
1343
1344 return altr_check_ecc_deps(device);
1345 }
1346
1347 static const struct edac_device_prv_data a10_nandecc_data = {
1348 .setup = socfpga_init_nand_ecc,
1349 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1350 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1351 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1352 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1353 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1354 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1355 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1356 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1357 .inject_fops = &altr_edac_a10_device_inject_fops,
1358 };
1359
1360 #endif /* CONFIG_EDAC_ALTERA_NAND */
1361
1362 /********************** DMA Device Functions **********************/
1363
1364 #ifdef CONFIG_EDAC_ALTERA_DMA
1365
1366 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1367 {
1368 int ret;
1369
1370 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1371 if (ret)
1372 return ret;
1373
1374 return altr_check_ecc_deps(device);
1375 }
1376
1377 static const struct edac_device_prv_data a10_dmaecc_data = {
1378 .setup = socfpga_init_dma_ecc,
1379 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1380 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1381 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1382 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1383 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1384 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1385 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1386 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1387 .inject_fops = &altr_edac_a10_device_inject_fops,
1388 };
1389
1390 #endif /* CONFIG_EDAC_ALTERA_DMA */
1391
1392 /********************** USB Device Functions **********************/
1393
1394 #ifdef CONFIG_EDAC_ALTERA_USB
1395
1396 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1397 {
1398 int ret;
1399
1400 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1401 if (ret)
1402 return ret;
1403
1404 return altr_check_ecc_deps(device);
1405 }
1406
1407 static const struct edac_device_prv_data a10_usbecc_data = {
1408 .setup = socfpga_init_usb_ecc,
1409 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1410 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1411 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1412 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1413 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1414 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1415 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1416 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1417 .inject_fops = &altr_edac_a10_device_inject2_fops,
1418 };
1419
1420 #endif /* CONFIG_EDAC_ALTERA_USB */
1421
1422 /********************** QSPI Device Functions **********************/
1423
1424 #ifdef CONFIG_EDAC_ALTERA_QSPI
1425
1426 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1427 {
1428 int ret;
1429
1430 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1431 if (ret)
1432 return ret;
1433
1434 return altr_check_ecc_deps(device);
1435 }
1436
1437 static const struct edac_device_prv_data a10_qspiecc_data = {
1438 .setup = socfpga_init_qspi_ecc,
1439 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1440 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1441 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1442 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1443 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1444 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1445 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1446 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1447 .inject_fops = &altr_edac_a10_device_inject_fops,
1448 };
1449
1450 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1451
1452 /********************* SDMMC Device Functions **********************/
1453
1454 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1455
1456 static const struct edac_device_prv_data a10_sdmmceccb_data;
1457 static int altr_portb_setup(struct altr_edac_device_dev *device)
1458 {
1459 struct edac_device_ctl_info *dci;
1460 struct altr_edac_device_dev *altdev;
1461 char *ecc_name = "sdmmcb-ecc";
1462 int edac_idx, rc;
1463 struct device_node *np;
1464 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1465
1466 rc = altr_check_ecc_deps(device);
1467 if (rc)
1468 return rc;
1469
1470 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1471 if (!np) {
1472 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1473 return -ENODEV;
1474 }
1475
1476 /* Create the PortB EDAC device */
1477 edac_idx = edac_device_alloc_index();
1478 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1479 ecc_name, 1, 0, NULL, 0, edac_idx);
1480 if (!dci) {
1481 edac_printk(KERN_ERR, EDAC_DEVICE,
1482 "%s: Unable to allocate PortB EDAC device\n",
1483 ecc_name);
1484 return -ENOMEM;
1485 }
1486
1487 /* Initialize the PortB EDAC device structure from PortA structure */
1488 altdev = dci->pvt_info;
1489 *altdev = *device;
1490
1491 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1492 return -ENOMEM;
1493
1494 /* Update PortB specific values */
1495 altdev->edac_dev_name = ecc_name;
1496 altdev->edac_idx = edac_idx;
1497 altdev->edac_dev = dci;
1498 altdev->data = prv;
1499 dci->dev = &altdev->ddev;
1500 dci->ctl_name = "Altera ECC Manager";
1501 dci->mod_name = ecc_name;
1502 dci->dev_name = ecc_name;
1503
1504 /* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */
1505 #ifdef CONFIG_ARCH_STRATIX10
1506 altdev->sb_irq = irq_of_parse_and_map(np, 1);
1507 #else
1508 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1509 #endif
1510 if (!altdev->sb_irq) {
1511 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1512 rc = -ENODEV;
1513 goto err_release_group_1;
1514 }
1515 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1516 prv->ecc_irq_handler,
1517 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1518 ecc_name, altdev);
1519 if (rc) {
1520 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1521 goto err_release_group_1;
1522 }
1523
1524 #ifdef CONFIG_ARCH_STRATIX10
1525 /* Use IRQ to determine SError origin instead of assigning IRQ */
1526 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1527 if (rc) {
1528 edac_printk(KERN_ERR, EDAC_DEVICE,
1529 "Error PortB DBIRQ alloc\n");
1530 goto err_release_group_1;
1531 }
1532 #else
1533 altdev->db_irq = irq_of_parse_and_map(np, 3);
1534 if (!altdev->db_irq) {
1535 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1536 rc = -ENODEV;
1537 goto err_release_group_1;
1538 }
1539 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1540 prv->ecc_irq_handler,
1541 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1542 ecc_name, altdev);
1543 if (rc) {
1544 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1545 goto err_release_group_1;
1546 }
1547 #endif
1548
1549 rc = edac_device_add_device(dci);
1550 if (rc) {
1551 edac_printk(KERN_ERR, EDAC_DEVICE,
1552 "edac_device_add_device portB failed\n");
1553 rc = -ENOMEM;
1554 goto err_release_group_1;
1555 }
1556 altr_create_edacdev_dbgfs(dci, prv);
1557
1558 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1559
1560 devres_remove_group(&altdev->ddev, altr_portb_setup);
1561
1562 return 0;
1563
1564 err_release_group_1:
1565 edac_device_free_ctl_info(dci);
1566 devres_release_group(&altdev->ddev, altr_portb_setup);
1567 edac_printk(KERN_ERR, EDAC_DEVICE,
1568 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1569 return rc;
1570 }
1571
1572 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1573 {
1574 int rc = -ENODEV;
1575 struct device_node *child;
1576
1577 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1578 if (!child)
1579 return -ENODEV;
1580
1581 if (!of_device_is_available(child))
1582 goto exit;
1583
1584 if (validate_parent_available(child))
1585 goto exit;
1586
1587 /* Init portB */
1588 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1589 a10_sdmmceccb_data.ecc_enable_mask, 1);
1590 if (rc)
1591 goto exit;
1592
1593 /* Setup portB */
1594 return altr_portb_setup(device);
1595
1596 exit:
1597 of_node_put(child);
1598 return rc;
1599 }
1600
1601 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1602 {
1603 struct altr_edac_device_dev *ad = dev_id;
1604 void __iomem *base = ad->base;
1605 const struct edac_device_prv_data *priv = ad->data;
1606
1607 if (irq == ad->sb_irq) {
1608 writel(priv->ce_clear_mask,
1609 base + ALTR_A10_ECC_INTSTAT_OFST);
1610 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1611 return IRQ_HANDLED;
1612 } else if (irq == ad->db_irq) {
1613 writel(priv->ue_clear_mask,
1614 base + ALTR_A10_ECC_INTSTAT_OFST);
1615 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1616 return IRQ_HANDLED;
1617 }
1618
1619 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1620
1621 return IRQ_NONE;
1622 }
1623
1624 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1625 .setup = socfpga_init_sdmmc_ecc,
1626 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1627 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1628 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1629 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1630 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1631 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1632 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1633 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1634 .inject_fops = &altr_edac_a10_device_inject_fops,
1635 };
1636
1637 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1638 .setup = socfpga_init_sdmmc_ecc,
1639 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1640 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1641 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1642 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1643 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1644 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1645 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1646 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1647 .inject_fops = &altr_edac_a10_device_inject_fops,
1648 };
1649
1650 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1651
1652 /********************* Arria10 EDAC Device Functions *************************/
1653 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1654 #ifdef CONFIG_EDAC_ALTERA_L2C
1655 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1656 #endif
1657 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1658 { .compatible = "altr,socfpga-a10-ocram-ecc",
1659 .data = &a10_ocramecc_data },
1660 #endif
1661 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1662 { .compatible = "altr,socfpga-eth-mac-ecc",
1663 .data = &a10_enetecc_data },
1664 #endif
1665 #ifdef CONFIG_EDAC_ALTERA_NAND
1666 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1667 #endif
1668 #ifdef CONFIG_EDAC_ALTERA_DMA
1669 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1670 #endif
1671 #ifdef CONFIG_EDAC_ALTERA_USB
1672 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1673 #endif
1674 #ifdef CONFIG_EDAC_ALTERA_QSPI
1675 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1676 #endif
1677 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1678 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1679 #endif
1680 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1681 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1682 #endif
1683 {},
1684 };
1685 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1686
1687 /*
1688 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1689 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1690 * manager manages the IRQs and the children.
1691 * Based on xgene_edac.c peripheral code.
1692 */
1693
1694 static ssize_t altr_edac_a10_device_trig(struct file *file,
1695 const char __user *user_buf,
1696 size_t count, loff_t *ppos)
1697 {
1698 struct edac_device_ctl_info *edac_dci = file->private_data;
1699 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1700 const struct edac_device_prv_data *priv = drvdata->data;
1701 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1702 unsigned long flags;
1703 u8 trig_type;
1704
1705 if (!user_buf || get_user(trig_type, user_buf))
1706 return -EFAULT;
1707
1708 local_irq_save(flags);
1709 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1710 writel(priv->ue_set_mask, set_addr);
1711 else
1712 writel(priv->ce_set_mask, set_addr);
1713
1714 /* Ensure the interrupt test bits are set */
1715 wmb();
1716 local_irq_restore(flags);
1717
1718 return count;
1719 }
1720
1721 /*
1722 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1723 * slightly. A few Arria10 peripherals can use this injection function.
1724 * Inject the error into the memory and then readback to trigger the IRQ.
1725 */
1726 static ssize_t altr_edac_a10_device_trig2(struct file *file,
1727 const char __user *user_buf,
1728 size_t count, loff_t *ppos)
1729 {
1730 struct edac_device_ctl_info *edac_dci = file->private_data;
1731 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1732 const struct edac_device_prv_data *priv = drvdata->data;
1733 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1734 unsigned long flags;
1735 u8 trig_type;
1736
1737 if (!user_buf || get_user(trig_type, user_buf))
1738 return -EFAULT;
1739
1740 local_irq_save(flags);
1741 if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1742 writel(priv->ue_set_mask, set_addr);
1743 } else {
1744 /* Setup read/write of 4 bytes */
1745 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1746 /* Setup Address to 0 */
1747 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1748 /* Setup accctrl to read & ecc & data override */
1749 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1750 /* Kick it. */
1751 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1752 /* Setup write for single bit change */
1753 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1754 drvdata->base + ECC_BLK_WDATA0_OFST);
1755 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1756 drvdata->base + ECC_BLK_WDATA1_OFST);
1757 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1758 drvdata->base + ECC_BLK_WDATA2_OFST);
1759 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1760 drvdata->base + ECC_BLK_WDATA3_OFST);
1761
1762 /* Copy Read ECC to Write ECC */
1763 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1764 drvdata->base + ECC_BLK_WECC0_OFST);
1765 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1766 drvdata->base + ECC_BLK_WECC1_OFST);
1767 /* Setup accctrl to write & ecc override & data override */
1768 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1769 /* Kick it. */
1770 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1771 /* Setup accctrl to read & ecc overwrite & data overwrite */
1772 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1773 /* Kick it. */
1774 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1775 }
1776
1777 /* Ensure the interrupt test bits are set */
1778 wmb();
1779 local_irq_restore(flags);
1780
1781 return count;
1782 }
1783
1784 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1785 {
1786 int dberr, bit, sm_offset, irq_status;
1787 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1788 struct irq_chip *chip = irq_desc_get_chip(desc);
1789 int irq = irq_desc_get_irq(desc);
1790 unsigned long bits;
1791
1792 dberr = (irq == edac->db_irq) ? 1 : 0;
1793 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1794 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1795
1796 chained_irq_enter(chip, desc);
1797
1798 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1799
1800 bits = irq_status;
1801 for_each_set_bit(bit, &bits, 32) {
1802 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1803 if (irq)
1804 generic_handle_irq(irq);
1805 }
1806
1807 chained_irq_exit(chip, desc);
1808 }
1809
1810 static int validate_parent_available(struct device_node *np)
1811 {
1812 struct device_node *parent;
1813 int ret = 0;
1814
1815 /* SDRAM must be present for Linux (implied parent) */
1816 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1817 return 0;
1818
1819 /* Ensure parent device is enabled if parent node exists */
1820 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1821 if (parent && !of_device_is_available(parent))
1822 ret = -ENODEV;
1823
1824 of_node_put(parent);
1825 return ret;
1826 }
1827
1828 static int get_s10_sdram_edac_resource(struct device_node *np,
1829 struct resource *res)
1830 {
1831 struct device_node *parent;
1832 int ret;
1833
1834 parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1835 if (!parent)
1836 return -ENODEV;
1837
1838 ret = of_address_to_resource(parent, 0, res);
1839 of_node_put(parent);
1840
1841 return ret;
1842 }
1843
1844 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1845 struct device_node *np)
1846 {
1847 struct edac_device_ctl_info *dci;
1848 struct altr_edac_device_dev *altdev;
1849 char *ecc_name = (char *)np->name;
1850 struct resource res;
1851 int edac_idx;
1852 int rc = 0;
1853 const struct edac_device_prv_data *prv;
1854 /* Get matching node and check for valid result */
1855 const struct of_device_id *pdev_id =
1856 of_match_node(altr_edac_a10_device_of_match, np);
1857 if (IS_ERR_OR_NULL(pdev_id))
1858 return -ENODEV;
1859
1860 /* Get driver specific data for this EDAC device */
1861 prv = pdev_id->data;
1862 if (IS_ERR_OR_NULL(prv))
1863 return -ENODEV;
1864
1865 if (validate_parent_available(np))
1866 return -ENODEV;
1867
1868 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1869 return -ENOMEM;
1870
1871 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1872 rc = get_s10_sdram_edac_resource(np, &res);
1873 else
1874 rc = of_address_to_resource(np, 0, &res);
1875
1876 if (rc < 0) {
1877 edac_printk(KERN_ERR, EDAC_DEVICE,
1878 "%s: no resource address\n", ecc_name);
1879 goto err_release_group;
1880 }
1881
1882 edac_idx = edac_device_alloc_index();
1883 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1884 1, ecc_name, 1, 0, NULL, 0,
1885 edac_idx);
1886
1887 if (!dci) {
1888 edac_printk(KERN_ERR, EDAC_DEVICE,
1889 "%s: Unable to allocate EDAC device\n", ecc_name);
1890 rc = -ENOMEM;
1891 goto err_release_group;
1892 }
1893
1894 altdev = dci->pvt_info;
1895 dci->dev = edac->dev;
1896 altdev->edac_dev_name = ecc_name;
1897 altdev->edac_idx = edac_idx;
1898 altdev->edac = edac;
1899 altdev->edac_dev = dci;
1900 altdev->data = prv;
1901 altdev->ddev = *edac->dev;
1902 dci->dev = &altdev->ddev;
1903 dci->ctl_name = "Altera ECC Manager";
1904 dci->mod_name = ecc_name;
1905 dci->dev_name = ecc_name;
1906
1907 altdev->base = devm_ioremap_resource(edac->dev, &res);
1908 if (IS_ERR(altdev->base)) {
1909 rc = PTR_ERR(altdev->base);
1910 goto err_release_group1;
1911 }
1912
1913 /* Check specific dependencies for the module */
1914 if (altdev->data->setup) {
1915 rc = altdev->data->setup(altdev);
1916 if (rc)
1917 goto err_release_group1;
1918 }
1919
1920 altdev->sb_irq = irq_of_parse_and_map(np, 0);
1921 if (!altdev->sb_irq) {
1922 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1923 rc = -ENODEV;
1924 goto err_release_group1;
1925 }
1926 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1927 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1928 ecc_name, altdev);
1929 if (rc) {
1930 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1931 goto err_release_group1;
1932 }
1933
1934 #ifdef CONFIG_ARCH_STRATIX10
1935 /* Use IRQ to determine SError origin instead of assigning IRQ */
1936 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
1937 if (rc) {
1938 edac_printk(KERN_ERR, EDAC_DEVICE,
1939 "Unable to parse DB IRQ index\n");
1940 goto err_release_group1;
1941 }
1942 #else
1943 altdev->db_irq = irq_of_parse_and_map(np, 1);
1944 if (!altdev->db_irq) {
1945 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1946 rc = -ENODEV;
1947 goto err_release_group1;
1948 }
1949 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1950 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1951 ecc_name, altdev);
1952 if (rc) {
1953 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1954 goto err_release_group1;
1955 }
1956 #endif
1957
1958 rc = edac_device_add_device(dci);
1959 if (rc) {
1960 dev_err(edac->dev, "edac_device_add_device failed\n");
1961 rc = -ENOMEM;
1962 goto err_release_group1;
1963 }
1964
1965 altr_create_edacdev_dbgfs(dci, prv);
1966
1967 list_add(&altdev->next, &edac->a10_ecc_devices);
1968
1969 devres_remove_group(edac->dev, altr_edac_a10_device_add);
1970
1971 return 0;
1972
1973 err_release_group1:
1974 edac_device_free_ctl_info(dci);
1975 err_release_group:
1976 devres_release_group(edac->dev, NULL);
1977 edac_printk(KERN_ERR, EDAC_DEVICE,
1978 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1979
1980 return rc;
1981 }
1982
1983 static void a10_eccmgr_irq_mask(struct irq_data *d)
1984 {
1985 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1986
1987 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
1988 BIT(d->hwirq));
1989 }
1990
1991 static void a10_eccmgr_irq_unmask(struct irq_data *d)
1992 {
1993 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1994
1995 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
1996 BIT(d->hwirq));
1997 }
1998
1999 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2000 irq_hw_number_t hwirq)
2001 {
2002 struct altr_arria10_edac *edac = d->host_data;
2003
2004 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2005 irq_set_chip_data(irq, edac);
2006 irq_set_noprobe(irq);
2007
2008 return 0;
2009 }
2010
2011 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2012 .map = a10_eccmgr_irqdomain_map,
2013 .xlate = irq_domain_xlate_twocell,
2014 };
2015
2016 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2017 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2018
2019 #ifdef CONFIG_ARCH_STRATIX10
2020 /* panic routine issues reboot on non-zero panic_timeout */
2021 extern int panic_timeout;
2022
2023 /*
2024 * The double bit error is handled through SError which is fatal. This is
2025 * called as a panic notifier to printout ECC error info as part of the panic.
2026 */
2027 static int s10_edac_dberr_handler(struct notifier_block *this,
2028 unsigned long event, void *ptr)
2029 {
2030 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2031 int err_addr, dberror;
2032
2033 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2034 &dberror);
2035 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2036 if (dberror & S10_DBE_IRQ_MASK) {
2037 struct list_head *position;
2038 struct altr_edac_device_dev *ed;
2039 struct arm_smccc_res result;
2040
2041 /* Find the matching DBE in the list of devices */
2042 list_for_each(position, &edac->a10_ecc_devices) {
2043 ed = list_entry(position, struct altr_edac_device_dev,
2044 next);
2045 if (!(BIT(ed->db_irq) & dberror))
2046 continue;
2047
2048 writel(ALTR_A10_ECC_DERRPENA,
2049 ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2050 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2051 regmap_write(edac->ecc_mgr_map,
2052 S10_SYSMGR_UE_ADDR_OFST, err_addr);
2053 edac_printk(KERN_ERR, EDAC_DEVICE,
2054 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2055 ed->edac_dev_name, err_addr);
2056 break;
2057 }
2058 /* Notify the System through SMC. Reboot delay = 1 second */
2059 panic_timeout = 1;
2060 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2061 0, 0, &result);
2062 }
2063
2064 return NOTIFY_DONE;
2065 }
2066 #endif
2067
2068 /****************** Arria 10 EDAC Probe Function *********************/
2069 static int altr_edac_a10_probe(struct platform_device *pdev)
2070 {
2071 struct altr_arria10_edac *edac;
2072 struct device_node *child;
2073
2074 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2075 if (!edac)
2076 return -ENOMEM;
2077
2078 edac->dev = &pdev->dev;
2079 platform_set_drvdata(pdev, edac);
2080 INIT_LIST_HEAD(&edac->a10_ecc_devices);
2081
2082 edac->ecc_mgr_map =
2083 altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
2084 "altr,sysmgr-syscon");
2085
2086 if (IS_ERR(edac->ecc_mgr_map)) {
2087 edac_printk(KERN_ERR, EDAC_DEVICE,
2088 "Unable to get syscon altr,sysmgr-syscon\n");
2089 return PTR_ERR(edac->ecc_mgr_map);
2090 }
2091
2092 edac->irq_chip.name = pdev->dev.of_node->name;
2093 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2094 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2095 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2096 &a10_eccmgr_ic_ops, edac);
2097 if (!edac->domain) {
2098 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2099 return -ENOMEM;
2100 }
2101
2102 edac->sb_irq = platform_get_irq(pdev, 0);
2103 if (edac->sb_irq < 0) {
2104 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2105 return edac->sb_irq;
2106 }
2107
2108 irq_set_chained_handler_and_data(edac->sb_irq,
2109 altr_edac_a10_irq_handler,
2110 edac);
2111
2112 #ifdef CONFIG_ARCH_STRATIX10
2113 {
2114 int dberror, err_addr;
2115
2116 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2117 atomic_notifier_chain_register(&panic_notifier_list,
2118 &edac->panic_notifier);
2119
2120 /* Printout a message if uncorrectable error previously. */
2121 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2122 &dberror);
2123 if (dberror) {
2124 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2125 &err_addr);
2126 edac_printk(KERN_ERR, EDAC_DEVICE,
2127 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2128 dberror, err_addr);
2129 /* Reset the sticky registers */
2130 regmap_write(edac->ecc_mgr_map,
2131 S10_SYSMGR_UE_VAL_OFST, 0);
2132 regmap_write(edac->ecc_mgr_map,
2133 S10_SYSMGR_UE_ADDR_OFST, 0);
2134 }
2135 }
2136 #else
2137 edac->db_irq = platform_get_irq(pdev, 1);
2138 if (edac->db_irq < 0) {
2139 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2140 return edac->db_irq;
2141 }
2142 irq_set_chained_handler_and_data(edac->db_irq,
2143 altr_edac_a10_irq_handler, edac);
2144 #endif
2145
2146 for_each_child_of_node(pdev->dev.of_node, child) {
2147 if (!of_device_is_available(child))
2148 continue;
2149
2150 if (of_match_node(altr_edac_a10_device_of_match, child))
2151 altr_edac_a10_device_add(edac, child);
2152
2153 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2154 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2155 of_platform_populate(pdev->dev.of_node,
2156 altr_sdram_ctrl_of_match,
2157 NULL, &pdev->dev);
2158 #endif
2159 }
2160
2161 return 0;
2162 }
2163
2164 static const struct of_device_id altr_edac_a10_of_match[] = {
2165 { .compatible = "altr,socfpga-a10-ecc-manager" },
2166 { .compatible = "altr,socfpga-s10-ecc-manager" },
2167 {},
2168 };
2169 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2170
2171 static struct platform_driver altr_edac_a10_driver = {
2172 .probe = altr_edac_a10_probe,
2173 .driver = {
2174 .name = "socfpga_a10_ecc_manager",
2175 .of_match_table = altr_edac_a10_of_match,
2176 },
2177 };
2178 module_platform_driver(altr_edac_a10_driver);
2179
2180 MODULE_LICENSE("GPL v2");
2181 MODULE_AUTHOR("Thor Thayer");
2182 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
Linux with added FPC-III support